From: Paolo Bonzini <pbonzini@redhat.com>
To: qemu-devel@nongnu.org
Cc: Zhao Liu <zhao1.liu@intel.com>
Subject: [PULL 21/34] rust: add SysBusDeviceImpl
Date: Thu, 27 Feb 2025 15:19:39 +0100 [thread overview]
Message-ID: <20250227141952.811410-22-pbonzini@redhat.com> (raw)
In-Reply-To: <20250227141952.811410-1-pbonzini@redhat.com>
The only function, right now, is to ensure that anything with a
SysBusDeviceClass class is a SysBusDevice.
Reviewed-by: Zhao Liu <zhao1.liu@intel.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
---
rust/hw/char/pl011/src/device.rs | 5 ++++-
rust/hw/timer/hpet/src/hpet.rs | 4 +++-
rust/qemu-api/src/sysbus.rs | 8 +++++---
3 files changed, 12 insertions(+), 5 deletions(-)
diff --git a/rust/hw/char/pl011/src/device.rs b/rust/hw/char/pl011/src/device.rs
index 59a689fdcd7..bea9723aed8 100644
--- a/rust/hw/char/pl011/src/device.rs
+++ b/rust/hw/char/pl011/src/device.rs
@@ -20,7 +20,7 @@
prelude::*,
qdev::{Clock, ClockEvent, DeviceImpl, DeviceState, Property, ResetType, ResettablePhasesImpl},
qom::{ClassInitImpl, ObjectImpl, Owned, ParentField},
- sysbus::{SysBusDevice, SysBusDeviceClass},
+ sysbus::{SysBusDevice, SysBusDeviceClass, SysBusDeviceImpl},
vmstate::VMStateDescription,
};
@@ -176,6 +176,8 @@ impl ResettablePhasesImpl for PL011State {
const HOLD: Option<fn(&Self, ResetType)> = Some(Self::reset_hold);
}
+impl SysBusDeviceImpl for PL011State {}
+
impl PL011Registers {
pub(self) fn read(&mut self, offset: RegisterOffset) -> (bool, u32) {
use RegisterOffset::*;
@@ -746,3 +748,4 @@ impl ObjectImpl for PL011Luminary {
impl DeviceImpl for PL011Luminary {}
impl ResettablePhasesImpl for PL011Luminary {}
+impl SysBusDeviceImpl for PL011Luminary {}
diff --git a/rust/hw/timer/hpet/src/hpet.rs b/rust/hw/timer/hpet/src/hpet.rs
index 75ff5b3e8d6..b4ffccf815f 100644
--- a/rust/hw/timer/hpet/src/hpet.rs
+++ b/rust/hw/timer/hpet/src/hpet.rs
@@ -23,7 +23,7 @@
qdev::{DeviceImpl, DeviceMethods, DeviceState, Property, ResetType, ResettablePhasesImpl},
qom::{ObjectImpl, ObjectType, ParentField},
qom_isa,
- sysbus::SysBusDevice,
+ sysbus::{SysBusDevice, SysBusDeviceImpl},
timer::{Timer, CLOCK_VIRTUAL},
};
@@ -887,3 +887,5 @@ fn properties() -> &'static [Property] {
impl ResettablePhasesImpl for HPETState {
const HOLD: Option<fn(&Self, ResetType)> = Some(Self::reset_hold);
}
+
+impl SysBusDeviceImpl for HPETState {}
diff --git a/rust/qemu-api/src/sysbus.rs b/rust/qemu-api/src/sysbus.rs
index fa36e12178f..fee2e3d478f 100644
--- a/rust/qemu-api/src/sysbus.rs
+++ b/rust/qemu-api/src/sysbus.rs
@@ -14,7 +14,7 @@
irq::{IRQState, InterruptSource},
memory::MemoryRegion,
prelude::*,
- qdev::{DeviceClass, DeviceState},
+ qdev::{DeviceClass, DeviceImpl, DeviceState},
qom::{ClassInitImpl, Owned},
};
@@ -25,10 +25,12 @@ unsafe impl ObjectType for SysBusDevice {
}
qom_isa!(SysBusDevice: DeviceState, Object);
-// TODO: add SysBusDeviceImpl
+// TODO: add virtual methods
+pub trait SysBusDeviceImpl: DeviceImpl + IsA<SysBusDevice> {}
+
impl<T> ClassInitImpl<SysBusDeviceClass> for T
where
- T: ClassInitImpl<DeviceClass>,
+ T: SysBusDeviceImpl + ClassInitImpl<DeviceClass>,
{
fn class_init(sdc: &mut SysBusDeviceClass) {
<T as ClassInitImpl<DeviceClass>>::class_init(&mut sdc.parent_class);
--
2.48.1
next prev parent reply other threads:[~2025-02-27 14:29 UTC|newest]
Thread overview: 36+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-02-27 14:19 [PULL 00/34] i386, Rust, build system, QOM patches for 2025-02-27 Paolo Bonzini
2025-02-27 14:19 ` [PULL 01/34] qom: Use command line syntax for default values in help Paolo Bonzini
2025-02-27 14:19 ` [PULL 02/34] hpet: do not overwrite properties on post_load Paolo Bonzini
2025-02-27 14:19 ` [PULL 03/34] i386: Fix the missing Rust HPET configuration option Paolo Bonzini
2025-02-27 14:19 ` [PULL 04/34] rust: subprojects: add libc crate Paolo Bonzini
2025-02-27 14:19 ` [PULL 05/34] rust: add module to convert between success/-errno and io::Result Paolo Bonzini
2025-02-27 14:19 ` [PULL 06/34] rust: tests: do not import bindings::* Paolo Bonzini
2025-02-27 14:19 ` [PULL 07/34] rust: prefer importing std::ptr over core::ptr Paolo Bonzini
2025-02-27 14:19 ` [PULL 08/34] docs: rust: fix typos Paolo Bonzini
2025-02-27 14:19 ` [PULL 09/34] docs: rust: update description of crates Paolo Bonzini
2025-02-27 14:19 ` [PULL 10/34] stub: Remove monitor-fd.c Paolo Bonzini
2025-02-27 14:19 ` [PULL 11/34] physmem: replace assertion with error Paolo Bonzini
2025-02-27 14:19 ` [PULL 12/34] pvg: do not enable it on cross-architecture targets Paolo Bonzini
2025-02-27 14:19 ` [PULL 13/34] pvg: add option to configure it out Paolo Bonzini
2025-02-27 14:19 ` [PULL 14/34] target/i386/hvf: fix a typo in a type name Paolo Bonzini
2025-02-27 14:19 ` [PULL 15/34] target/i386/hvf: fix the declaration of hvf_handle_io Paolo Bonzini
2025-02-27 14:19 ` [PULL 16/34] target/i386/hvf: use x86_segment in x86_decode.c Paolo Bonzini
2025-02-27 14:19 ` [PULL 17/34] target/i386/hvf: move and rename {load, store}_regs Paolo Bonzini
2025-02-27 14:19 ` [PULL 18/34] target/i386/hvf: move and rename simulate_{rdmsr, wrmsr} Paolo Bonzini
2025-02-27 14:19 ` [PULL 19/34] target/i386/hvf: drop some dead code Paolo Bonzini
2025-02-27 14:19 ` [PULL 20/34] rust: add IsA bounds to QOM implementation traits Paolo Bonzini
2025-02-27 14:19 ` Paolo Bonzini [this message]
2025-02-27 14:19 ` [PULL 22/34] rust: qom: add ObjectImpl::CLASS_INIT Paolo Bonzini
2025-02-27 14:19 ` [PULL 23/34] rust: pl011, qemu_api tests: do not use ClassInitImpl Paolo Bonzini
2025-02-27 14:19 ` [PULL 24/34] rust: qom: get rid of ClassInitImpl Paolo Bonzini
2025-02-27 14:19 ` [PULL 25/34] i386/cpu: Support module level cache topology Paolo Bonzini
2025-02-27 14:19 ` [PULL 26/34] i386/cpu: Update cache topology with machine's configuration Paolo Bonzini
2025-02-27 14:19 ` [PULL 27/34] i386/pc: Support cache topology in -machine for PC machine Paolo Bonzini
2025-02-27 14:19 ` [PULL 28/34] i386/cpu: add has_caches flag to check smp_cache configuration Paolo Bonzini
2025-02-27 14:19 ` [PULL 29/34] target/riscv: remove unused macro DEFINE_CPU Paolo Bonzini
2025-02-27 14:19 ` [PULL 30/34] target/riscv: move 128-bit check to TCG realize Paolo Bonzini
2025-02-27 14:19 ` [PULL 31/34] target/i386: Add support for Zhaoxin CPU vendor identification Paolo Bonzini
2025-02-27 14:19 ` [PULL 32/34] target/i386: Add CPUID leaf 0xC000_0001 EDX definitions Paolo Bonzini
2025-02-27 14:19 ` [PULL 33/34] target/i386: Introduce Zhaoxin Yongfeng CPU model Paolo Bonzini
2025-02-27 14:19 ` [PULL 34/34] target/i386: Mask CMPLegacy bit in CPUID[0x80000001].ECX for Zhaoxin CPUs Paolo Bonzini
2025-03-03 12:12 ` [PULL 00/34] i386, Rust, build system, QOM patches for 2025-02-27 Stefan Hajnoczi
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