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Fri, 28 Feb 2025 05:10:30 -0800 (PST) Received: from localhost ([2a02:8308:a00c:e200::688c]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-43b73717ac0sm55102405e9.20.2025.02.28.05.10.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 28 Feb 2025 05:10:29 -0800 (PST) Date: Fri, 28 Feb 2025 14:10:29 +0100 From: Andrew Jones To: Yong-Xuan Wang Cc: qemu-devel@nongnu.org, qemu-riscv@nongnu.org, greentime.hu@sifive.com, vincent.chen@sifive.com, frank.chang@sifive.com, jim.shu@sifive.com, Palmer Dabbelt , Alistair Francis , Weiwei Li , Daniel Henrique Barboza , Liu Zhiwei , Philippe =?utf-8?Q?Mathieu-Daud=C3=A9?= Subject: Re: [PATCH v2 1/8] target/riscv/kvm: rewrite get/set for KVM_REG_RISCV_CSR Message-ID: <20250228-0947621811d6951e12ae55ab@orel> References: <20250224082417.31382-1-yongxuan.wang@sifive.com> <20250224082417.31382-2-yongxuan.wang@sifive.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20250224082417.31382-2-yongxuan.wang@sifive.com> Received-SPF: pass client-ip=2a00:1450:4864:20::333; envelope-from=ajones@ventanamicro.com; helo=mail-wm1-x333.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On Mon, Feb 24, 2025 at 04:24:08PM +0800, Yong-Xuan Wang wrote: > As KVM_REG_RISCV_CSR includes several subtypes of CSR, rewrite the > related macros and functions to prepare for other subtypes. > > Signed-off-by: Yong-Xuan Wang > --- > target/riscv/kvm/kvm-cpu.c | 70 +++++++++++++++++++++++--------------- > 1 file changed, 43 insertions(+), 27 deletions(-) > > diff --git a/target/riscv/kvm/kvm-cpu.c b/target/riscv/kvm/kvm-cpu.c > index 471fd554b369..ff1211d2fe39 100644 > --- a/target/riscv/kvm/kvm-cpu.c > +++ b/target/riscv/kvm/kvm-cpu.c > @@ -111,9 +111,8 @@ static uint64_t kvm_riscv_vector_reg_id(RISCVCPU *cpu, > kvm_riscv_reg_id_ulong(env, KVM_REG_RISCV_CORE, \ > KVM_REG_RISCV_CORE_REG(name)) > > -#define RISCV_CSR_REG(env, name) \ > - kvm_riscv_reg_id_ulong(env, KVM_REG_RISCV_CSR, \ > - KVM_REG_RISCV_CSR_REG(name)) > +#define RISCV_CSR_REG(env, idx) \ > + kvm_riscv_reg_id_ulong(env, KVM_REG_RISCV_CSR, idx) > > #define RISCV_CONFIG_REG(env, name) \ > kvm_riscv_reg_id_ulong(env, KVM_REG_RISCV_CONFIG, \ > @@ -130,17 +129,20 @@ static uint64_t kvm_riscv_vector_reg_id(RISCVCPU *cpu, > kvm_riscv_reg_id_ulong(env, KVM_REG_RISCV_VECTOR, \ > KVM_REG_RISCV_VECTOR_CSR_REG(name)) > > -#define KVM_RISCV_GET_CSR(cs, env, csr, reg) \ > +#define RISCV_GENERAL_CSR_REG(name) \ > + (KVM_REG_RISCV_CSR_GENERAL | KVM_REG_RISCV_CSR_REG(name)) > + > +#define KVM_RISCV_GET_CSR(cs, env, idx, reg) \ > do { \ > - int _ret = kvm_get_one_reg(cs, RISCV_CSR_REG(env, csr), ®); \ > + int _ret = kvm_get_one_reg(cs, RISCV_CSR_REG(env, idx), ®); \ > if (_ret) { \ > return _ret; \ > } \ > } while (0) > > -#define KVM_RISCV_SET_CSR(cs, env, csr, reg) \ > +#define KVM_RISCV_SET_CSR(cs, env, idx, reg) \ > do { \ > - int _ret = kvm_set_one_reg(cs, RISCV_CSR_REG(env, csr), ®); \ > + int _ret = kvm_set_one_reg(cs, RISCV_CSR_REG(env, idx), ®); \ > if (_ret) { \ > return _ret; \ > } \ > @@ -608,36 +610,50 @@ static int kvm_riscv_put_regs_core(CPUState *cs) > return ret; > } > > -static int kvm_riscv_get_regs_csr(CPUState *cs) > +static int kvm_riscv_get_regs_general_csr(CPUState *cs) > { > CPURISCVState *env = &RISCV_CPU(cs)->env; > > - KVM_RISCV_GET_CSR(cs, env, sstatus, env->mstatus); > - KVM_RISCV_GET_CSR(cs, env, sie, env->mie); > - KVM_RISCV_GET_CSR(cs, env, stvec, env->stvec); > - KVM_RISCV_GET_CSR(cs, env, sscratch, env->sscratch); > - KVM_RISCV_GET_CSR(cs, env, sepc, env->sepc); > - KVM_RISCV_GET_CSR(cs, env, scause, env->scause); > - KVM_RISCV_GET_CSR(cs, env, stval, env->stval); > - KVM_RISCV_GET_CSR(cs, env, sip, env->mip); > - KVM_RISCV_GET_CSR(cs, env, satp, env->satp); > + KVM_RISCV_GET_CSR(cs, env, RISCV_GENERAL_CSR_REG(sstatus), env->mstatus); > + KVM_RISCV_GET_CSR(cs, env, RISCV_GENERAL_CSR_REG(sie), env->mie); > + KVM_RISCV_GET_CSR(cs, env, RISCV_GENERAL_CSR_REG(stvec), env->stvec); > + KVM_RISCV_GET_CSR(cs, env, RISCV_GENERAL_CSR_REG(sscratch), env->sscratch); > + KVM_RISCV_GET_CSR(cs, env, RISCV_GENERAL_CSR_REG(sepc), env->sepc); > + KVM_RISCV_GET_CSR(cs, env, RISCV_GENERAL_CSR_REG(scause), env->scause); > + KVM_RISCV_GET_CSR(cs, env, RISCV_GENERAL_CSR_REG(stval), env->stval); > + KVM_RISCV_GET_CSR(cs, env, RISCV_GENERAL_CSR_REG(sip), env->mip); > + KVM_RISCV_GET_CSR(cs, env, RISCV_GENERAL_CSR_REG(satp), env->satp); > > return 0; > } > > -static int kvm_riscv_put_regs_csr(CPUState *cs) > +static int kvm_riscv_put_regs_general_csr(CPUState *cs) > { > CPURISCVState *env = &RISCV_CPU(cs)->env; > > - KVM_RISCV_SET_CSR(cs, env, sstatus, env->mstatus); > - KVM_RISCV_SET_CSR(cs, env, sie, env->mie); > - KVM_RISCV_SET_CSR(cs, env, stvec, env->stvec); > - KVM_RISCV_SET_CSR(cs, env, sscratch, env->sscratch); > - KVM_RISCV_SET_CSR(cs, env, sepc, env->sepc); > - KVM_RISCV_SET_CSR(cs, env, scause, env->scause); > - KVM_RISCV_SET_CSR(cs, env, stval, env->stval); > - KVM_RISCV_SET_CSR(cs, env, sip, env->mip); > - KVM_RISCV_SET_CSR(cs, env, satp, env->satp); > + KVM_RISCV_SET_CSR(cs, env, RISCV_GENERAL_CSR_REG(sstatus), env->mstatus); > + KVM_RISCV_SET_CSR(cs, env, RISCV_GENERAL_CSR_REG(sie), env->mie); > + KVM_RISCV_SET_CSR(cs, env, RISCV_GENERAL_CSR_REG(stvec), env->stvec); > + KVM_RISCV_SET_CSR(cs, env, RISCV_GENERAL_CSR_REG(sscratch), env->sscratch); > + KVM_RISCV_SET_CSR(cs, env, RISCV_GENERAL_CSR_REG(sepc), env->sepc); > + KVM_RISCV_SET_CSR(cs, env, RISCV_GENERAL_CSR_REG(scause), env->scause); > + KVM_RISCV_SET_CSR(cs, env, RISCV_GENERAL_CSR_REG(stval), env->stval); > + KVM_RISCV_SET_CSR(cs, env, RISCV_GENERAL_CSR_REG(sip), env->mip); > + KVM_RISCV_SET_CSR(cs, env, RISCV_GENERAL_CSR_REG(satp), env->satp); > + > + return 0; > +} > + > +static int kvm_riscv_get_regs_csr(CPUState *cs) > +{ > + kvm_riscv_get_regs_general_csr(cs); KVM_RISCV_GET/SET_CSR() can return errors so the return value should be checked here and below (just kvm_arch_get/put_registers() checks the returns values of kvm_riscv_get/put_regs_csr()). Otherwise, Reviewed-by: Andrew Jones > + > + return 0; > +} > + > +static int kvm_riscv_put_regs_csr(CPUState *cs) > +{ > + kvm_riscv_put_regs_general_csr(cs); > > return 0; > } > -- > 2.17.1 >