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Fri, 28 Feb 2025 05:36:16 -0800 (PST) Received: from localhost ([2a02:8308:a00c:e200::688c]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-390e47b7cdbsm5381648f8f.54.2025.02.28.05.36.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 28 Feb 2025 05:36:15 -0800 (PST) Date: Fri, 28 Feb 2025 14:36:15 +0100 From: Andrew Jones To: Yong-Xuan Wang Cc: qemu-devel@nongnu.org, qemu-riscv@nongnu.org, greentime.hu@sifive.com, vincent.chen@sifive.com, frank.chang@sifive.com, jim.shu@sifive.com, Palmer Dabbelt , Alistair Francis , Weiwei Li , Daniel Henrique Barboza , Liu Zhiwei Subject: Re: [PATCH v2 8/8] hw/intc/imsic: prevent to use IMSIC when host doesn't support AIA extension Message-ID: <20250228-70b318f083760cd552b3fcf3@orel> References: <20250224082417.31382-1-yongxuan.wang@sifive.com> <20250224082417.31382-9-yongxuan.wang@sifive.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20250224082417.31382-9-yongxuan.wang@sifive.com> Received-SPF: pass client-ip=2a00:1450:4864:20::42d; envelope-from=ajones@ventanamicro.com; helo=mail-wr1-x42d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On Mon, Feb 24, 2025 at 04:24:15PM +0800, Yong-Xuan Wang wrote: > Currently QEMU will continue to create the IMSIC devices and enable the > AIA extension for guest OS when the host kernel doesn't support the AIA > extension. This will cause an illegal instruction exception when the > guest OS access the AIA CSRs. Add additional checks to ensure the > guest OS only uses the IMSIC devices when the host kernel supports > the AIA extension. > > Signed-off-by: Yong-Xuan Wang > --- > hw/intc/riscv_imsic.c | 17 +++++++++++++---- > 1 file changed, 13 insertions(+), 4 deletions(-) > > diff --git a/hw/intc/riscv_imsic.c b/hw/intc/riscv_imsic.c > index dc8162c0a7c9..8c64f2c21274 100644 > --- a/hw/intc/riscv_imsic.c > +++ b/hw/intc/riscv_imsic.c > @@ -375,12 +375,21 @@ static void riscv_imsic_realize(DeviceState *dev, Error **errp) > > /* Force select AIA feature and setup CSR read-modify-write callback */ > if (env) { > - if (!imsic->mmode) { > - rcpu->cfg.ext_ssaia = true; > - riscv_cpu_set_geilen(env, imsic->num_pages - 1); > + if (kvm_enabled()) { > + if (!rcpu->cfg.ext_ssaia) { > + error_report("Host machine doesn't support AIA extension. " > + "Do not use IMSIC as interrupt controller."); > + exit(1); > + } > } else { > - rcpu->cfg.ext_smaia = true; > + if (!imsic->mmode) { > + rcpu->cfg.ext_ssaia = true; > + riscv_cpu_set_geilen(env, imsic->num_pages - 1); > + } else { > + rcpu->cfg.ext_smaia = true; > + } > } > + > riscv_cpu_set_aia_ireg_rmw_fn(env, (imsic->mmode) ? PRV_M : PRV_S, > riscv_imsic_rmw, imsic); > } > -- > 2.17.1 > > Reviewed-by: Andrew Jones