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Fri, 28 Feb 2025 05:18:01 -0800 (PST) Received: from localhost ([2a02:8308:a00c:e200::688c]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-43b7371701esm58217235e9.17.2025.02.28.05.18.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 28 Feb 2025 05:18:01 -0800 (PST) Date: Fri, 28 Feb 2025 14:18:00 +0100 From: Andrew Jones To: Yong-Xuan Wang Cc: qemu-devel@nongnu.org, qemu-riscv@nongnu.org, greentime.hu@sifive.com, vincent.chen@sifive.com, frank.chang@sifive.com, jim.shu@sifive.com, Palmer Dabbelt , Alistair Francis , Weiwei Li , Daniel Henrique Barboza , Liu Zhiwei , Philippe =?utf-8?Q?Mathieu-Daud=C3=A9?= Subject: Re: [PATCH v2 2/8] target/riscv/kvm: add KVM_REG_RISCV_CSR_AIA Message-ID: <20250228-7b19a9cfc42f2b5fcc2ab85e@orel> References: <20250224082417.31382-1-yongxuan.wang@sifive.com> <20250224082417.31382-3-yongxuan.wang@sifive.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20250224082417.31382-3-yongxuan.wang@sifive.com> Received-SPF: pass client-ip=2a00:1450:4864:20::32b; envelope-from=ajones@ventanamicro.com; helo=mail-wm1-x32b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On Mon, Feb 24, 2025 at 04:24:09PM +0800, Yong-Xuan Wang wrote: > Add KVM_REG_RISCV_CSR_AIA support to get/set the context of AIA > extension in VS mode. > > Signed-off-by: Yong-Xuan Wang > --- > target/riscv/kvm/kvm-cpu.c | 45 ++++++++++++++++++++++++++++++++++++++ > 1 file changed, 45 insertions(+) > > diff --git a/target/riscv/kvm/kvm-cpu.c b/target/riscv/kvm/kvm-cpu.c > index ff1211d2fe39..c7318f64cf12 100644 > --- a/target/riscv/kvm/kvm-cpu.c > +++ b/target/riscv/kvm/kvm-cpu.c > @@ -132,6 +132,9 @@ static uint64_t kvm_riscv_vector_reg_id(RISCVCPU *cpu, > #define RISCV_GENERAL_CSR_REG(name) \ > (KVM_REG_RISCV_CSR_GENERAL | KVM_REG_RISCV_CSR_REG(name)) > > +#define RISCV_AIA_CSR_REG(name) \ > + (KVM_REG_RISCV_CSR_AIA | KVM_REG_RISCV_CSR_AIA_REG(name)) > + > #define KVM_RISCV_GET_CSR(cs, env, idx, reg) \ > do { \ > int _ret = kvm_get_one_reg(cs, RISCV_CSR_REG(env, idx), ®); \ > @@ -644,9 +647,50 @@ static int kvm_riscv_put_regs_general_csr(CPUState *cs) > return 0; > } > > +static int kvm_riscv_get_regs_aia_csr(CPUState *cs) > +{ > + CPURISCVState *env = &RISCV_CPU(cs)->env; > + uint64_t mask = MAKE_64BIT_MASK(32, 32); > + uint64_t val; > + > + KVM_RISCV_GET_CSR(cs, env, RISCV_AIA_CSR_REG(siselect), env->siselect); > + KVM_RISCV_GET_CSR(cs, env, RISCV_AIA_CSR_REG(iprio1), env->siprio[0]); > + KVM_RISCV_GET_CSR(cs, env, RISCV_AIA_CSR_REG(iprio1h), env->siprio[8]); > + KVM_RISCV_GET_CSR(cs, env, RISCV_AIA_CSR_REG(iprio2), env->siprio[16]); > + KVM_RISCV_GET_CSR(cs, env, RISCV_AIA_CSR_REG(iprio2h), env->siprio[24]); > + > + KVM_RISCV_GET_CSR(cs, env, RISCV_AIA_CSR_REG(sieh), val); > + env->sie = set_field(env->sie, mask, val); > + KVM_RISCV_GET_CSR(cs, env, RISCV_AIA_CSR_REG(siph), val); > + riscv_cpu_update_mip(env, mask, val); The *h registers should only s/r on 32-bit targets. > + > + return 0; > +} > + > +static int kvm_riscv_put_regs_aia_csr(CPUState *cs) > +{ > + CPURISCVState *env = &RISCV_CPU(cs)->env; > + uint64_t mask = MAKE_64BIT_MASK(32, 32); > + uint64_t val; > + > + KVM_RISCV_SET_CSR(cs, env, RISCV_AIA_CSR_REG(siselect), env->siselect); > + KVM_RISCV_SET_CSR(cs, env, RISCV_AIA_CSR_REG(iprio1), env->siprio[0]); > + KVM_RISCV_SET_CSR(cs, env, RISCV_AIA_CSR_REG(iprio1h), env->siprio[8]); > + KVM_RISCV_SET_CSR(cs, env, RISCV_AIA_CSR_REG(iprio2), env->siprio[16]); > + KVM_RISCV_SET_CSR(cs, env, RISCV_AIA_CSR_REG(iprio2h), env->siprio[24]); > + > + val = get_field(env->sie, mask); > + KVM_RISCV_SET_CSR(cs, env, RISCV_AIA_CSR_REG(sieh), val); > + val = get_field(env->mip, mask); > + KVM_RISCV_SET_CSR(cs, env, RISCV_AIA_CSR_REG(siph), val); > + > + return 0; > +} > + > static int kvm_riscv_get_regs_csr(CPUState *cs) > { > kvm_riscv_get_regs_general_csr(cs); > + kvm_riscv_get_regs_aia_csr(cs); > > return 0; > } > @@ -654,6 +698,7 @@ static int kvm_riscv_get_regs_csr(CPUState *cs) > static int kvm_riscv_put_regs_csr(CPUState *cs) > { > kvm_riscv_put_regs_general_csr(cs); > + kvm_riscv_put_regs_aia_csr(cs); > > return 0; > } > -- > 2.17.1 > Thanks, drew