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From: Andrew Jones <ajones@ventanamicro.com>
To: Yong-Xuan Wang <yongxuan.wang@sifive.com>
Cc: qemu-devel@nongnu.org, qemu-riscv@nongnu.org,
	greentime.hu@sifive.com,  vincent.chen@sifive.com,
	frank.chang@sifive.com, jim.shu@sifive.com,
	 Palmer Dabbelt <palmer@dabbelt.com>,
	Alistair Francis <alistair.francis@wdc.com>,
	 Weiwei Li <liwei1518@gmail.com>,
	Daniel Henrique Barboza <dbarboza@ventanamicro.com>,
	 Liu Zhiwei <zhiwei_liu@linux.alibaba.com>
Subject: Re: [PATCH v2 4/8] target/riscv: add helper to get CSR name
Date: Fri, 28 Feb 2025 14:23:23 +0100	[thread overview]
Message-ID: <20250228-91bf13b18026d1640fd75255@orel> (raw)
In-Reply-To: <20250224082417.31382-5-yongxuan.wang@sifive.com>

On Mon, Feb 24, 2025 at 04:24:11PM +0800, Yong-Xuan Wang wrote:
> Add a helper function to get CSR name from CSR number.
> 
> Signed-off-by: Yong-Xuan Wang <yongxuan.wang@sifive.com>
> ---
>  target/riscv/cpu.h | 8 +++++++-
>  1 file changed, 7 insertions(+), 1 deletion(-)
> 
> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> index 616c3bdc1c24..df10ff63474b 100644
> --- a/target/riscv/cpu.h
> +++ b/target/riscv/cpu.h
> @@ -920,8 +920,14 @@ extern const bool valid_vm_1_10_32[], valid_vm_1_10_64[];
>  void riscv_get_csr_ops(int csrno, riscv_csr_operations *ops);
>  void riscv_set_csr_ops(int csrno, riscv_csr_operations *ops);
>  
> -void riscv_cpu_register_gdb_regs_for_features(CPUState *cs);
> +static inline const char *riscv_get_csr_name(int csr_no)
> +{
> +    g_assert(csr_no > 0 && csr_no < CSR_TABLE_SIZE);
>  
> +    return csr_ops[csr_no].name;
> +}
> +
> +void riscv_cpu_register_gdb_regs_for_features(CPUState *cs);
>  target_ulong riscv_new_csr_seed(target_ulong new_value,
>                                  target_ulong write_mask);
>  
> -- 
> 2.17.1
> 
>

Reviewed-by: Andrew Jones <ajones@ventanamicro.com>


  reply	other threads:[~2025-02-28 13:24 UTC|newest]

Thread overview: 18+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-02-24  8:24 [PATCH v2 0/8] riscv: AIA: kernel-irqchip=off support Yong-Xuan Wang
2025-02-24  8:24 ` [PATCH v2 1/8] target/riscv/kvm: rewrite get/set for KVM_REG_RISCV_CSR Yong-Xuan Wang
2025-02-28 13:10   ` Andrew Jones
2025-02-24  8:24 ` [PATCH v2 2/8] target/riscv/kvm: add KVM_REG_RISCV_CSR_AIA Yong-Xuan Wang
2025-02-28 13:18   ` Andrew Jones
2025-02-24  8:24 ` [PATCH v2 3/8] target/riscv/kvm: add KVM_REG_RISCV_CSR_SMSTATEEN Yong-Xuan Wang
2025-02-28 13:21   ` Andrew Jones
2025-02-24  8:24 ` [PATCH v2 4/8] target/riscv: add helper to get CSR name Yong-Xuan Wang
2025-02-28 13:23   ` Andrew Jones [this message]
2025-02-24  8:24 ` [PATCH v2 5/8] target/riscv/kvm: rewrite kvm_riscv_handle_csr Yong-Xuan Wang
2025-03-04 15:45   ` Andrew Jones
2025-02-24  8:24 ` [PATCH v2 6/8] target/riscv/kvm: add CSR_SIREG and CSR_STOPEI emulation Yong-Xuan Wang
2025-03-04 15:52   ` Andrew Jones
2025-02-24  8:24 ` [PATCH v2 7/8] docs: update the description about RISC-V AIA Yong-Xuan Wang
2025-02-28 13:33   ` Andrew Jones
2025-02-24  8:24 ` [PATCH v2 8/8] hw/intc/imsic: prevent to use IMSIC when host doesn't support AIA extension Yong-Xuan Wang
2025-02-28 13:36   ` Andrew Jones
2025-03-03 19:19 ` [PATCH v2 0/8] riscv: AIA: kernel-irqchip=off support Kashyap Chamarthy

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