From: Andrew Jones <ajones@ventanamicro.com>
To: Yong-Xuan Wang <yongxuan.wang@sifive.com>
Cc: qemu-devel@nongnu.org, qemu-riscv@nongnu.org,
greentime.hu@sifive.com, vincent.chen@sifive.com,
frank.chang@sifive.com, jim.shu@sifive.com,
"Palmer Dabbelt" <palmer@dabbelt.com>,
"Alistair Francis" <alistair.francis@wdc.com>,
"Weiwei Li" <liwei1518@gmail.com>,
"Daniel Henrique Barboza" <dbarboza@ventanamicro.com>,
"Liu Zhiwei" <zhiwei_liu@linux.alibaba.com>,
"Philippe Mathieu-Daudé" <philmd@linaro.org>
Subject: Re: [PATCH v2 3/8] target/riscv/kvm: add KVM_REG_RISCV_CSR_SMSTATEEN
Date: Fri, 28 Feb 2025 14:21:03 +0100 [thread overview]
Message-ID: <20250228-aa65cab1325f4717a41d038f@orel> (raw)
In-Reply-To: <20250224082417.31382-4-yongxuan.wang@sifive.com>
On Mon, Feb 24, 2025 at 04:24:10PM +0800, Yong-Xuan Wang wrote:
> Add KVM_REG_RISCV_CSR_SMSTATEEN support to get/set the context of
> Smstateen extension in VS mode.
>
> Signed-off-by: Yong-Xuan Wang <yongxuan.wang@sifive.com>
> ---
> target/riscv/kvm/kvm-cpu.c | 25 +++++++++++++++++++++++++
> 1 file changed, 25 insertions(+)
>
> diff --git a/target/riscv/kvm/kvm-cpu.c b/target/riscv/kvm/kvm-cpu.c
> index c7318f64cf12..d421c7a1b65d 100644
> --- a/target/riscv/kvm/kvm-cpu.c
> +++ b/target/riscv/kvm/kvm-cpu.c
> @@ -135,6 +135,9 @@ static uint64_t kvm_riscv_vector_reg_id(RISCVCPU *cpu,
> #define RISCV_AIA_CSR_REG(name) \
> (KVM_REG_RISCV_CSR_AIA | KVM_REG_RISCV_CSR_AIA_REG(name))
>
> +#define RISCV_SMSTATEEN_CSR_REG(name) \
> + (KVM_REG_RISCV_CSR_SMSTATEEN | KVM_REG_RISCV_CSR_SMSTATEEN_REG(name))
> +
> #define KVM_RISCV_GET_CSR(cs, env, idx, reg) \
> do { \
> int _ret = kvm_get_one_reg(cs, RISCV_CSR_REG(env, idx), ®); \
> @@ -687,10 +690,31 @@ static int kvm_riscv_put_regs_aia_csr(CPUState *cs)
> return 0;
> }
>
> +static int kvm_riscv_get_regs_smstateen_csr(CPUState *cs)
> +{
> + CPURISCVState *env = &RISCV_CPU(cs)->env;
> +
> + KVM_RISCV_GET_CSR(cs, env,
> + RISCV_SMSTATEEN_CSR_REG(sstateen0), env->sstateen[0]);
> +
> + return 0;
> +}
> +
> +static int kvm_riscv_put_regs_smstateen_csr(CPUState *cs)
> +{
> + CPURISCVState *env = &RISCV_CPU(cs)->env;
> +
> + KVM_RISCV_SET_CSR(cs, env,
> + RISCV_SMSTATEEN_CSR_REG(sstateen0), env->sstateen[0]);
> +
> + return 0;
> +}
> +
> static int kvm_riscv_get_regs_csr(CPUState *cs)
> {
> kvm_riscv_get_regs_general_csr(cs);
> kvm_riscv_get_regs_aia_csr(cs);
> + kvm_riscv_get_regs_smstateen_csr(cs);
>
> return 0;
> }
> @@ -699,6 +723,7 @@ static int kvm_riscv_put_regs_csr(CPUState *cs)
> {
> kvm_riscv_put_regs_general_csr(cs);
> kvm_riscv_put_regs_aia_csr(cs);
> + kvm_riscv_put_regs_smstateen_csr(cs);
>
> return 0;
> }
> --
> 2.17.1
>
Looks good other than the missing error checking/propagating in
kvm_riscv_get/put_regs_csr() which the general and aia registers are also
missing.
Thanks,
drew
next prev parent reply other threads:[~2025-02-28 13:21 UTC|newest]
Thread overview: 18+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-02-24 8:24 [PATCH v2 0/8] riscv: AIA: kernel-irqchip=off support Yong-Xuan Wang
2025-02-24 8:24 ` [PATCH v2 1/8] target/riscv/kvm: rewrite get/set for KVM_REG_RISCV_CSR Yong-Xuan Wang
2025-02-28 13:10 ` Andrew Jones
2025-02-24 8:24 ` [PATCH v2 2/8] target/riscv/kvm: add KVM_REG_RISCV_CSR_AIA Yong-Xuan Wang
2025-02-28 13:18 ` Andrew Jones
2025-02-24 8:24 ` [PATCH v2 3/8] target/riscv/kvm: add KVM_REG_RISCV_CSR_SMSTATEEN Yong-Xuan Wang
2025-02-28 13:21 ` Andrew Jones [this message]
2025-02-24 8:24 ` [PATCH v2 4/8] target/riscv: add helper to get CSR name Yong-Xuan Wang
2025-02-28 13:23 ` Andrew Jones
2025-02-24 8:24 ` [PATCH v2 5/8] target/riscv/kvm: rewrite kvm_riscv_handle_csr Yong-Xuan Wang
2025-03-04 15:45 ` Andrew Jones
2025-02-24 8:24 ` [PATCH v2 6/8] target/riscv/kvm: add CSR_SIREG and CSR_STOPEI emulation Yong-Xuan Wang
2025-03-04 15:52 ` Andrew Jones
2025-02-24 8:24 ` [PATCH v2 7/8] docs: update the description about RISC-V AIA Yong-Xuan Wang
2025-02-28 13:33 ` Andrew Jones
2025-02-24 8:24 ` [PATCH v2 8/8] hw/intc/imsic: prevent to use IMSIC when host doesn't support AIA extension Yong-Xuan Wang
2025-02-28 13:36 ` Andrew Jones
2025-03-03 19:19 ` [PATCH v2 0/8] riscv: AIA: kernel-irqchip=off support Kashyap Chamarthy
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