From: Paolo Bonzini <pbonzini@redhat.com>
To: qemu-devel@nongnu.org
Cc: alistair.francis@wdc.com
Subject: [PATCH 09/22] target/riscv: do not make RISCVCPUConfig fields conditional
Date: Fri, 28 Feb 2025 11:27:33 +0100 [thread overview]
Message-ID: <20250228102747.867770-10-pbonzini@redhat.com> (raw)
In-Reply-To: <20250228102747.867770-1-pbonzini@redhat.com>
Avoid the need for #ifdefs in CPU declarations, keeping them
simple. After all class_data used to be specified for all
emulators, not just system ones.
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
---
target/riscv/cpu_cfg_fields.h.inc | 2 --
target/riscv/cpu.c | 3 ---
2 files changed, 5 deletions(-)
diff --git a/target/riscv/cpu_cfg_fields.h.inc b/target/riscv/cpu_cfg_fields.h.inc
index a42f298017f..a08d85aec26 100644
--- a/target/riscv/cpu_cfg_fields.h.inc
+++ b/target/riscv/cpu_cfg_fields.h.inc
@@ -159,9 +159,7 @@ TYPED_FIELD(uint16_t, cbom_blocksize)
TYPED_FIELD(uint16_t, cbop_blocksize)
TYPED_FIELD(uint16_t, cboz_blocksize)
-#ifndef CONFIG_USER_ONLY
TYPED_FIELD(int8_t, max_satp_mode)
-#endif
#undef BOOL_FIELD
#undef TYPED_FIELD
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index e9d8126360e..cbb6cde082b 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -1483,10 +1483,7 @@ static void riscv_cpu_init(Object *obj)
cpu->cfg.cbop_blocksize = 64;
cpu->cfg.cboz_blocksize = 64;
cpu->env.vext_ver = VEXT_VERSION_1_00_0;
-
-#ifndef CONFIG_USER_ONLY
cpu->cfg.max_satp_mode = -1;
-#endif /* CONFIG_USER_ONLY */
env->misa_ext_mask = env->misa_ext = mcc->def->misa_ext;
riscv_cpu_cfg_merge(&cpu->cfg, &mcc->def->cfg);
--
2.48.1
next prev parent reply other threads:[~2025-02-28 10:28 UTC|newest]
Thread overview: 31+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-02-28 10:27 [PATCH v2 00/22] target/riscv: declarative CPU definitions Paolo Bonzini
2025-02-28 10:27 ` [PATCH 01/22] target/riscv: Declare RISCVCPUClass::misa_mxl_max as RISCVMXL Paolo Bonzini
2025-03-06 0:46 ` Alistair Francis
2025-02-28 10:27 ` [PATCH 02/22] target/riscv: Convert misa_mxl_max using GLib macros Paolo Bonzini
2025-03-06 0:47 ` Alistair Francis
2025-02-28 10:27 ` [PATCH 03/22] target/riscv: introduce RISCVCPUDef Paolo Bonzini
2025-02-28 17:19 ` Richard Henderson
2025-02-28 10:27 ` [PATCH 04/22] target/riscv: store RISCVCPUDef struct directly in the class Paolo Bonzini
2025-03-06 0:50 ` Alistair Francis
2025-02-28 10:27 ` [PATCH 05/22] target/riscv: merge riscv_cpu_class_init with the class_base function Paolo Bonzini
2025-03-06 0:52 ` Alistair Francis
2025-02-28 10:27 ` [PATCH 06/22] target/riscv: move RISCVCPUConfig fields to a header file Paolo Bonzini
2025-03-06 0:53 ` Alistair Francis
2025-02-28 10:27 ` [PATCH 07/22] target/riscv: add more RISCVCPUDef fields Paolo Bonzini
2025-02-28 10:27 ` [PATCH 08/22] target/riscv: convert abstract CPU classes to RISCVCPUDef Paolo Bonzini
2025-02-28 10:27 ` Paolo Bonzini [this message]
2025-02-28 10:27 ` [PATCH 10/22] target/riscv: convert profile CPU models " Paolo Bonzini
2025-02-28 10:27 ` [PATCH 11/22] target/riscv: convert bare " Paolo Bonzini
2025-02-28 10:27 ` [PATCH 12/22] target/riscv: convert dynamic " Paolo Bonzini
2025-02-28 10:27 ` [PATCH 13/22] target/riscv: convert SiFive E " Paolo Bonzini
2025-02-28 10:27 ` [PATCH 14/22] target/riscv: convert ibex " Paolo Bonzini
2025-02-28 10:27 ` [PATCH 15/22] target/riscv: convert SiFive U " Paolo Bonzini
2025-02-28 10:27 ` [PATCH 16/22] target/riscv: th: make CSR insertion test a bit more intuitive Paolo Bonzini
2025-02-28 10:27 ` [PATCH 17/22] target/riscv: generalize custom CSR functionality Paolo Bonzini
2025-02-28 10:27 ` [PATCH 18/22] target/riscv: convert TT C906 to RISCVCPUDef Paolo Bonzini
2025-02-28 10:27 ` [PATCH 19/22] target/riscv: convert TT Ascalon " Paolo Bonzini
2025-02-28 10:27 ` [PATCH 20/22] target/riscv: convert Ventana V1 " Paolo Bonzini
2025-02-28 10:27 ` [PATCH 21/22] target/riscv: convert Xiangshan Nanhu " Paolo Bonzini
2025-02-28 10:27 ` [PATCH 22/22] target/riscv: remove .instance_post_init Paolo Bonzini
2025-04-17 13:40 ` [PATCH v2 00/22] target/riscv: declarative CPU definitions Paolo Bonzini
2025-04-24 10:37 ` Alistair Francis
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