From: Paolo Bonzini <pbonzini@redhat.com>
To: qemu-devel@nongnu.org
Cc: alistair.francis@wdc.com
Subject: [PATCH 16/22] target/riscv: th: make CSR insertion test a bit more intuitive
Date: Fri, 28 Feb 2025 11:27:40 +0100 [thread overview]
Message-ID: <20250228102747.867770-17-pbonzini@redhat.com> (raw)
In-Reply-To: <20250228102747.867770-1-pbonzini@redhat.com>
In preparation for generalizing the custom CSR functionality,
make the test return bool instead of int. Make the insertion_test
optional, too.
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
---
target/riscv/th_csr.c | 13 ++++---------
1 file changed, 4 insertions(+), 9 deletions(-)
diff --git a/target/riscv/th_csr.c b/target/riscv/th_csr.c
index 6c970d4e813..969a9fe3c80 100644
--- a/target/riscv/th_csr.c
+++ b/target/riscv/th_csr.c
@@ -29,7 +29,7 @@
typedef struct {
int csrno;
- int (*insertion_test)(RISCVCPU *cpu);
+ bool (*insertion_test)(RISCVCPU *cpu);
riscv_csr_operations csr_ops;
} riscv_csr;
@@ -42,13 +42,9 @@ static RISCVException smode(CPURISCVState *env, int csrno)
return RISCV_EXCP_ILLEGAL_INST;
}
-static int test_thead_mvendorid(RISCVCPU *cpu)
+static bool test_thead_mvendorid(RISCVCPU *cpu)
{
- if (cpu->cfg.mvendorid != THEAD_VENDOR_ID) {
- return -1;
- }
-
- return 0;
+ return cpu->cfg.mvendorid == THEAD_VENDOR_ID;
}
static RISCVException read_th_sxstatus(CPURISCVState *env, int csrno,
@@ -66,13 +62,12 @@ static riscv_csr th_csr_list[] = {
.csr_ops = { "th.sxstatus", smode, read_th_sxstatus }
}
};
-
void th_register_custom_csrs(RISCVCPU *cpu)
{
for (size_t i = 0; i < ARRAY_SIZE(th_csr_list); i++) {
int csrno = th_csr_list[i].csrno;
riscv_csr_operations *csr_ops = &th_csr_list[i].csr_ops;
- if (!th_csr_list[i].insertion_test(cpu)) {
+ if (!th_csr_list[i].insertion_test || th_csr_list[i].insertion_test(cpu)) {
riscv_set_csr_ops(csrno, csr_ops);
}
}
--
2.48.1
next prev parent reply other threads:[~2025-02-28 10:30 UTC|newest]
Thread overview: 31+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-02-28 10:27 [PATCH v2 00/22] target/riscv: declarative CPU definitions Paolo Bonzini
2025-02-28 10:27 ` [PATCH 01/22] target/riscv: Declare RISCVCPUClass::misa_mxl_max as RISCVMXL Paolo Bonzini
2025-03-06 0:46 ` Alistair Francis
2025-02-28 10:27 ` [PATCH 02/22] target/riscv: Convert misa_mxl_max using GLib macros Paolo Bonzini
2025-03-06 0:47 ` Alistair Francis
2025-02-28 10:27 ` [PATCH 03/22] target/riscv: introduce RISCVCPUDef Paolo Bonzini
2025-02-28 17:19 ` Richard Henderson
2025-02-28 10:27 ` [PATCH 04/22] target/riscv: store RISCVCPUDef struct directly in the class Paolo Bonzini
2025-03-06 0:50 ` Alistair Francis
2025-02-28 10:27 ` [PATCH 05/22] target/riscv: merge riscv_cpu_class_init with the class_base function Paolo Bonzini
2025-03-06 0:52 ` Alistair Francis
2025-02-28 10:27 ` [PATCH 06/22] target/riscv: move RISCVCPUConfig fields to a header file Paolo Bonzini
2025-03-06 0:53 ` Alistair Francis
2025-02-28 10:27 ` [PATCH 07/22] target/riscv: add more RISCVCPUDef fields Paolo Bonzini
2025-02-28 10:27 ` [PATCH 08/22] target/riscv: convert abstract CPU classes to RISCVCPUDef Paolo Bonzini
2025-02-28 10:27 ` [PATCH 09/22] target/riscv: do not make RISCVCPUConfig fields conditional Paolo Bonzini
2025-02-28 10:27 ` [PATCH 10/22] target/riscv: convert profile CPU models to RISCVCPUDef Paolo Bonzini
2025-02-28 10:27 ` [PATCH 11/22] target/riscv: convert bare " Paolo Bonzini
2025-02-28 10:27 ` [PATCH 12/22] target/riscv: convert dynamic " Paolo Bonzini
2025-02-28 10:27 ` [PATCH 13/22] target/riscv: convert SiFive E " Paolo Bonzini
2025-02-28 10:27 ` [PATCH 14/22] target/riscv: convert ibex " Paolo Bonzini
2025-02-28 10:27 ` [PATCH 15/22] target/riscv: convert SiFive U " Paolo Bonzini
2025-02-28 10:27 ` Paolo Bonzini [this message]
2025-02-28 10:27 ` [PATCH 17/22] target/riscv: generalize custom CSR functionality Paolo Bonzini
2025-02-28 10:27 ` [PATCH 18/22] target/riscv: convert TT C906 to RISCVCPUDef Paolo Bonzini
2025-02-28 10:27 ` [PATCH 19/22] target/riscv: convert TT Ascalon " Paolo Bonzini
2025-02-28 10:27 ` [PATCH 20/22] target/riscv: convert Ventana V1 " Paolo Bonzini
2025-02-28 10:27 ` [PATCH 21/22] target/riscv: convert Xiangshan Nanhu " Paolo Bonzini
2025-02-28 10:27 ` [PATCH 22/22] target/riscv: remove .instance_post_init Paolo Bonzini
2025-04-17 13:40 ` [PATCH v2 00/22] target/riscv: declarative CPU definitions Paolo Bonzini
2025-04-24 10:37 ` Alistair Francis
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