From: Paolo Bonzini <pbonzini@redhat.com>
To: qemu-devel@nongnu.org
Cc: alistair.francis@wdc.com
Subject: [PATCH 18/22] target/riscv: convert TT C906 to RISCVCPUDef
Date: Fri, 28 Feb 2025 11:27:42 +0100 [thread overview]
Message-ID: <20250228102747.867770-19-pbonzini@redhat.com> (raw)
In-Reply-To: <20250228102747.867770-1-pbonzini@redhat.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
---
target/riscv/cpu.c | 61 +++++++++++++++++++++-------------------------
1 file changed, 28 insertions(+), 33 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 4d6756a97ce..a249e48da6c 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -497,38 +497,6 @@ static void riscv_register_custom_csrs(RISCVCPU *cpu, const RISCVCSR *csr_list)
#endif
#if defined(TARGET_RISCV64)
-static void rv64_thead_c906_cpu_init(Object *obj)
-{
- CPURISCVState *env = &RISCV_CPU(obj)->env;
- RISCVCPU *cpu = RISCV_CPU(obj);
-
- riscv_cpu_set_misa_ext(env, RVG | RVC | RVS | RVU);
- env->priv_ver = PRIV_VERSION_1_11_0;
-
- cpu->cfg.ext_zfa = true;
- cpu->cfg.ext_zfh = true;
- cpu->cfg.mmu = true;
- cpu->cfg.ext_xtheadba = true;
- cpu->cfg.ext_xtheadbb = true;
- cpu->cfg.ext_xtheadbs = true;
- cpu->cfg.ext_xtheadcmo = true;
- cpu->cfg.ext_xtheadcondmov = true;
- cpu->cfg.ext_xtheadfmemidx = true;
- cpu->cfg.ext_xtheadmac = true;
- cpu->cfg.ext_xtheadmemidx = true;
- cpu->cfg.ext_xtheadmempair = true;
- cpu->cfg.ext_xtheadsync = true;
-
- cpu->cfg.mvendorid = THEAD_VENDOR_ID;
-#ifndef CONFIG_USER_ONLY
- set_satp_mode_max_supported(cpu, VM_1_10_SV39);
- riscv_register_custom_csrs(cpu, th_csr_list);
-#endif
-
- /* inherited from parent obj via riscv_cpu_init() */
- cpu->cfg.pmp = true;
-}
-
static void rv64_veyron_v1_cpu_init(Object *obj)
{
CPURISCVState *env = &RISCV_CPU(obj)->env;
@@ -3098,7 +3066,34 @@ static const TypeInfo riscv_cpu_type_infos[] = {
.misa_mxl_max = MXL_RV64,
),
- DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_THEAD_C906, MXL_RV64, rv64_thead_c906_cpu_init),
+ DEFINE_RISCV_CPU(TYPE_RISCV_CPU_THEAD_C906, TYPE_RISCV_VENDOR_CPU,
+ .misa_mxl_max = MXL_RV64,
+ .misa_ext = RVG | RVC | RVS | RVU,
+ .priv_spec = PRIV_VERSION_1_11_0,
+
+ .cfg.ext_zfa = true,
+ .cfg.ext_zfh = true,
+ .cfg.mmu = true,
+ .cfg.ext_xtheadba = true,
+ .cfg.ext_xtheadbb = true,
+ .cfg.ext_xtheadbs = true,
+ .cfg.ext_xtheadcmo = true,
+ .cfg.ext_xtheadcondmov = true,
+ .cfg.ext_xtheadfmemidx = true,
+ .cfg.ext_xtheadmac = true,
+ .cfg.ext_xtheadmemidx = true,
+ .cfg.ext_xtheadmempair = true,
+ .cfg.ext_xtheadsync = true,
+ .cfg.pmp = true,
+
+ .cfg.mvendorid = THEAD_VENDOR_ID,
+
+ .cfg.max_satp_mode = VM_1_10_SV39,
+#ifndef CONFIG_USER_ONLY
+ .custom_csrs = th_csr_list,
+#endif
+ ),
+
DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_TT_ASCALON, MXL_RV64, rv64_tt_ascalon_cpu_init),
DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_VEYRON_V1, MXL_RV64, rv64_veyron_v1_cpu_init),
DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_XIANGSHAN_NANHU,
--
2.48.1
next prev parent reply other threads:[~2025-02-28 10:29 UTC|newest]
Thread overview: 31+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-02-28 10:27 [PATCH v2 00/22] target/riscv: declarative CPU definitions Paolo Bonzini
2025-02-28 10:27 ` [PATCH 01/22] target/riscv: Declare RISCVCPUClass::misa_mxl_max as RISCVMXL Paolo Bonzini
2025-03-06 0:46 ` Alistair Francis
2025-02-28 10:27 ` [PATCH 02/22] target/riscv: Convert misa_mxl_max using GLib macros Paolo Bonzini
2025-03-06 0:47 ` Alistair Francis
2025-02-28 10:27 ` [PATCH 03/22] target/riscv: introduce RISCVCPUDef Paolo Bonzini
2025-02-28 17:19 ` Richard Henderson
2025-02-28 10:27 ` [PATCH 04/22] target/riscv: store RISCVCPUDef struct directly in the class Paolo Bonzini
2025-03-06 0:50 ` Alistair Francis
2025-02-28 10:27 ` [PATCH 05/22] target/riscv: merge riscv_cpu_class_init with the class_base function Paolo Bonzini
2025-03-06 0:52 ` Alistair Francis
2025-02-28 10:27 ` [PATCH 06/22] target/riscv: move RISCVCPUConfig fields to a header file Paolo Bonzini
2025-03-06 0:53 ` Alistair Francis
2025-02-28 10:27 ` [PATCH 07/22] target/riscv: add more RISCVCPUDef fields Paolo Bonzini
2025-02-28 10:27 ` [PATCH 08/22] target/riscv: convert abstract CPU classes to RISCVCPUDef Paolo Bonzini
2025-02-28 10:27 ` [PATCH 09/22] target/riscv: do not make RISCVCPUConfig fields conditional Paolo Bonzini
2025-02-28 10:27 ` [PATCH 10/22] target/riscv: convert profile CPU models to RISCVCPUDef Paolo Bonzini
2025-02-28 10:27 ` [PATCH 11/22] target/riscv: convert bare " Paolo Bonzini
2025-02-28 10:27 ` [PATCH 12/22] target/riscv: convert dynamic " Paolo Bonzini
2025-02-28 10:27 ` [PATCH 13/22] target/riscv: convert SiFive E " Paolo Bonzini
2025-02-28 10:27 ` [PATCH 14/22] target/riscv: convert ibex " Paolo Bonzini
2025-02-28 10:27 ` [PATCH 15/22] target/riscv: convert SiFive U " Paolo Bonzini
2025-02-28 10:27 ` [PATCH 16/22] target/riscv: th: make CSR insertion test a bit more intuitive Paolo Bonzini
2025-02-28 10:27 ` [PATCH 17/22] target/riscv: generalize custom CSR functionality Paolo Bonzini
2025-02-28 10:27 ` Paolo Bonzini [this message]
2025-02-28 10:27 ` [PATCH 19/22] target/riscv: convert TT Ascalon to RISCVCPUDef Paolo Bonzini
2025-02-28 10:27 ` [PATCH 20/22] target/riscv: convert Ventana V1 " Paolo Bonzini
2025-02-28 10:27 ` [PATCH 21/22] target/riscv: convert Xiangshan Nanhu " Paolo Bonzini
2025-02-28 10:27 ` [PATCH 22/22] target/riscv: remove .instance_post_init Paolo Bonzini
2025-04-17 13:40 ` [PATCH v2 00/22] target/riscv: declarative CPU definitions Paolo Bonzini
2025-04-24 10:37 ` Alistair Francis
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