From: Paolo Bonzini <pbonzini@redhat.com>
To: qemu-devel@nongnu.org
Cc: alistair.francis@wdc.com
Subject: [PATCH 21/22] target/riscv: convert Xiangshan Nanhu to RISCVCPUDef
Date: Fri, 28 Feb 2025 11:27:45 +0100 [thread overview]
Message-ID: <20250228102747.867770-22-pbonzini@redhat.com> (raw)
In-Reply-To: <20250228102747.867770-1-pbonzini@redhat.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
---
target/riscv/cpu.c | 77 ++++++++++++++--------------------------------
1 file changed, 23 insertions(+), 54 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index a6c97a43799..ceda1a6e630 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -438,16 +438,6 @@ const char *satp_mode_str(uint8_t satp_mode, bool is_32_bit)
g_assert_not_reached();
}
-static void set_satp_mode_max_supported(RISCVCPU *cpu,
- int satp_mode)
-{
- bool rv32 = riscv_cpu_mxl(&cpu->env) == MXL_RV32;
- const bool *valid_vm = rv32 ? valid_vm_1_10_32 : valid_vm_1_10_64;
-
- assert(valid_vm[satp_mode]);
- cpu->cfg.max_satp_mode = satp_mode;
-}
-
static bool get_satp_mode_supported(RISCVCPU *cpu, uint16_t *supported)
{
bool rv32 = riscv_cpu_is_32bit(cpu);
@@ -496,38 +486,6 @@ static void riscv_register_custom_csrs(RISCVCPU *cpu, const RISCVCSR *csr_list)
}
#endif
-#if defined(TARGET_RISCV64)
-
-static void rv64_xiangshan_nanhu_cpu_init(Object *obj)
-{
- CPURISCVState *env = &RISCV_CPU(obj)->env;
- RISCVCPU *cpu = RISCV_CPU(obj);
-
- riscv_cpu_set_misa_ext(env, RVG | RVC | RVB | RVS | RVU);
- env->priv_ver = PRIV_VERSION_1_12_0;
-
- /* Enable ISA extensions */
- cpu->cfg.ext_zbc = true;
- cpu->cfg.ext_zbkb = true;
- cpu->cfg.ext_zbkc = true;
- cpu->cfg.ext_zbkx = true;
- cpu->cfg.ext_zknd = true;
- cpu->cfg.ext_zkne = true;
- cpu->cfg.ext_zknh = true;
- cpu->cfg.ext_zksed = true;
- cpu->cfg.ext_zksh = true;
- cpu->cfg.ext_svinval = true;
-
- cpu->cfg.mmu = true;
- cpu->cfg.pmp = true;
-
-#ifndef CONFIG_USER_ONLY
- set_satp_mode_max_supported(cpu, VM_1_10_SV39);
-#endif
-}
-
-#endif /* !TARGET_RISCV64 */
-
static ObjectClass *riscv_cpu_class_by_name(const char *cpu_model)
{
ObjectClass *oc;
@@ -2777,16 +2735,6 @@ void riscv_isa_write_fdt(RISCVCPU *cpu, void *fdt, char *nodename)
}
#endif
-#define DEFINE_VENDOR_CPU(type_name, misa_mxl_max_, initfn) \
- { \
- .name = (type_name), \
- .parent = TYPE_RISCV_VENDOR_CPU, \
- .instance_init = (initfn), \
- .class_data = (void*) &((const RISCVCPUDef) { \
- .misa_mxl_max = (misa_mxl_max_), \
- }), \
- }
-
#define DEFINE_ABSTRACT_RISCV_CPU(type_name, parent_type_name, ...) \
{ \
.name = (type_name), \
@@ -3084,8 +3032,29 @@ static const TypeInfo riscv_cpu_type_infos[] = {
.cfg.max_satp_mode = VM_1_10_SV48,
),
- DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_XIANGSHAN_NANHU,
- MXL_RV64, rv64_xiangshan_nanhu_cpu_init),
+ DEFINE_RISCV_CPU(TYPE_RISCV_CPU_XIANGSHAN_NANHU, TYPE_RISCV_VENDOR_CPU,
+ .misa_mxl_max = MXL_RV64,
+ .misa_ext = RVG | RVC | RVB | RVS | RVU,
+ .priv_spec = PRIV_VERSION_1_12_0,
+
+ /* ISA extensions */
+ .cfg.ext_zbc = true,
+ .cfg.ext_zbkb = true,
+ .cfg.ext_zbkc = true,
+ .cfg.ext_zbkx = true,
+ .cfg.ext_zknd = true,
+ .cfg.ext_zkne = true,
+ .cfg.ext_zknh = true,
+ .cfg.ext_zksed = true,
+ .cfg.ext_zksh = true,
+ .cfg.ext_svinval = true,
+
+ .cfg.mmu = true,
+ .cfg.pmp = true,
+
+ .cfg.max_satp_mode = VM_1_10_SV39,
+ ),
+
#ifdef CONFIG_TCG
DEFINE_RISCV_CPU(TYPE_RISCV_CPU_BASE128, TYPE_RISCV_DYNAMIC_CPU,
.cfg.max_satp_mode = VM_1_10_SV57,
--
2.48.1
next prev parent reply other threads:[~2025-02-28 10:33 UTC|newest]
Thread overview: 31+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-02-28 10:27 [PATCH v2 00/22] target/riscv: declarative CPU definitions Paolo Bonzini
2025-02-28 10:27 ` [PATCH 01/22] target/riscv: Declare RISCVCPUClass::misa_mxl_max as RISCVMXL Paolo Bonzini
2025-03-06 0:46 ` Alistair Francis
2025-02-28 10:27 ` [PATCH 02/22] target/riscv: Convert misa_mxl_max using GLib macros Paolo Bonzini
2025-03-06 0:47 ` Alistair Francis
2025-02-28 10:27 ` [PATCH 03/22] target/riscv: introduce RISCVCPUDef Paolo Bonzini
2025-02-28 17:19 ` Richard Henderson
2025-02-28 10:27 ` [PATCH 04/22] target/riscv: store RISCVCPUDef struct directly in the class Paolo Bonzini
2025-03-06 0:50 ` Alistair Francis
2025-02-28 10:27 ` [PATCH 05/22] target/riscv: merge riscv_cpu_class_init with the class_base function Paolo Bonzini
2025-03-06 0:52 ` Alistair Francis
2025-02-28 10:27 ` [PATCH 06/22] target/riscv: move RISCVCPUConfig fields to a header file Paolo Bonzini
2025-03-06 0:53 ` Alistair Francis
2025-02-28 10:27 ` [PATCH 07/22] target/riscv: add more RISCVCPUDef fields Paolo Bonzini
2025-02-28 10:27 ` [PATCH 08/22] target/riscv: convert abstract CPU classes to RISCVCPUDef Paolo Bonzini
2025-02-28 10:27 ` [PATCH 09/22] target/riscv: do not make RISCVCPUConfig fields conditional Paolo Bonzini
2025-02-28 10:27 ` [PATCH 10/22] target/riscv: convert profile CPU models to RISCVCPUDef Paolo Bonzini
2025-02-28 10:27 ` [PATCH 11/22] target/riscv: convert bare " Paolo Bonzini
2025-02-28 10:27 ` [PATCH 12/22] target/riscv: convert dynamic " Paolo Bonzini
2025-02-28 10:27 ` [PATCH 13/22] target/riscv: convert SiFive E " Paolo Bonzini
2025-02-28 10:27 ` [PATCH 14/22] target/riscv: convert ibex " Paolo Bonzini
2025-02-28 10:27 ` [PATCH 15/22] target/riscv: convert SiFive U " Paolo Bonzini
2025-02-28 10:27 ` [PATCH 16/22] target/riscv: th: make CSR insertion test a bit more intuitive Paolo Bonzini
2025-02-28 10:27 ` [PATCH 17/22] target/riscv: generalize custom CSR functionality Paolo Bonzini
2025-02-28 10:27 ` [PATCH 18/22] target/riscv: convert TT C906 to RISCVCPUDef Paolo Bonzini
2025-02-28 10:27 ` [PATCH 19/22] target/riscv: convert TT Ascalon " Paolo Bonzini
2025-02-28 10:27 ` [PATCH 20/22] target/riscv: convert Ventana V1 " Paolo Bonzini
2025-02-28 10:27 ` Paolo Bonzini [this message]
2025-02-28 10:27 ` [PATCH 22/22] target/riscv: remove .instance_post_init Paolo Bonzini
2025-04-17 13:40 ` [PATCH v2 00/22] target/riscv: declarative CPU definitions Paolo Bonzini
2025-04-24 10:37 ` Alistair Francis
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