From: Paolo Bonzini <pbonzini@redhat.com>
To: qemu-devel@nongnu.org
Cc: alistair.francis@wdc.com
Subject: [PATCH 22/22] target/riscv: remove .instance_post_init
Date: Fri, 28 Feb 2025 11:27:46 +0100 [thread overview]
Message-ID: <20250228102747.867770-23-pbonzini@redhat.com> (raw)
In-Reply-To: <20250228102747.867770-1-pbonzini@redhat.com>
Unlike other uses of .instance_post_init, accel_cpu_instance_init()
*registers* properties, and therefore must be run before
device_post_init() which sets them to their values from -global.
In order to move all registration of properties to .instance_init,
call accel_cpu_instance_init() at the end of riscv_cpu_init().
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
---
target/riscv/cpu.c | 8 ++------
1 file changed, 2 insertions(+), 6 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index ceda1a6e630..e261b24a21a 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -1079,11 +1079,6 @@ static bool riscv_cpu_is_dynamic(Object *cpu_obj)
return object_dynamic_cast(cpu_obj, TYPE_RISCV_DYNAMIC_CPU) != NULL;
}
-static void riscv_cpu_post_init(Object *obj)
-{
- accel_cpu_instance_init(CPU(obj));
-}
-
static void riscv_cpu_init(Object *obj)
{
RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(obj);
@@ -1139,6 +1134,8 @@ static void riscv_cpu_init(Object *obj)
riscv_register_custom_csrs(cpu, mcc->def->custom_csrs);
}
#endif
+
+ accel_cpu_instance_init(CPU(obj));
}
typedef struct misa_ext_info {
@@ -2769,7 +2766,6 @@ static const TypeInfo riscv_cpu_type_infos[] = {
.instance_size = sizeof(RISCVCPU),
.instance_align = __alignof(RISCVCPU),
.instance_init = riscv_cpu_init,
- .instance_post_init = riscv_cpu_post_init,
.abstract = true,
.class_size = sizeof(RISCVCPUClass),
.class_init = riscv_cpu_common_class_init,
--
2.48.1
next prev parent reply other threads:[~2025-02-28 10:33 UTC|newest]
Thread overview: 31+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-02-28 10:27 [PATCH v2 00/22] target/riscv: declarative CPU definitions Paolo Bonzini
2025-02-28 10:27 ` [PATCH 01/22] target/riscv: Declare RISCVCPUClass::misa_mxl_max as RISCVMXL Paolo Bonzini
2025-03-06 0:46 ` Alistair Francis
2025-02-28 10:27 ` [PATCH 02/22] target/riscv: Convert misa_mxl_max using GLib macros Paolo Bonzini
2025-03-06 0:47 ` Alistair Francis
2025-02-28 10:27 ` [PATCH 03/22] target/riscv: introduce RISCVCPUDef Paolo Bonzini
2025-02-28 17:19 ` Richard Henderson
2025-02-28 10:27 ` [PATCH 04/22] target/riscv: store RISCVCPUDef struct directly in the class Paolo Bonzini
2025-03-06 0:50 ` Alistair Francis
2025-02-28 10:27 ` [PATCH 05/22] target/riscv: merge riscv_cpu_class_init with the class_base function Paolo Bonzini
2025-03-06 0:52 ` Alistair Francis
2025-02-28 10:27 ` [PATCH 06/22] target/riscv: move RISCVCPUConfig fields to a header file Paolo Bonzini
2025-03-06 0:53 ` Alistair Francis
2025-02-28 10:27 ` [PATCH 07/22] target/riscv: add more RISCVCPUDef fields Paolo Bonzini
2025-02-28 10:27 ` [PATCH 08/22] target/riscv: convert abstract CPU classes to RISCVCPUDef Paolo Bonzini
2025-02-28 10:27 ` [PATCH 09/22] target/riscv: do not make RISCVCPUConfig fields conditional Paolo Bonzini
2025-02-28 10:27 ` [PATCH 10/22] target/riscv: convert profile CPU models to RISCVCPUDef Paolo Bonzini
2025-02-28 10:27 ` [PATCH 11/22] target/riscv: convert bare " Paolo Bonzini
2025-02-28 10:27 ` [PATCH 12/22] target/riscv: convert dynamic " Paolo Bonzini
2025-02-28 10:27 ` [PATCH 13/22] target/riscv: convert SiFive E " Paolo Bonzini
2025-02-28 10:27 ` [PATCH 14/22] target/riscv: convert ibex " Paolo Bonzini
2025-02-28 10:27 ` [PATCH 15/22] target/riscv: convert SiFive U " Paolo Bonzini
2025-02-28 10:27 ` [PATCH 16/22] target/riscv: th: make CSR insertion test a bit more intuitive Paolo Bonzini
2025-02-28 10:27 ` [PATCH 17/22] target/riscv: generalize custom CSR functionality Paolo Bonzini
2025-02-28 10:27 ` [PATCH 18/22] target/riscv: convert TT C906 to RISCVCPUDef Paolo Bonzini
2025-02-28 10:27 ` [PATCH 19/22] target/riscv: convert TT Ascalon " Paolo Bonzini
2025-02-28 10:27 ` [PATCH 20/22] target/riscv: convert Ventana V1 " Paolo Bonzini
2025-02-28 10:27 ` [PATCH 21/22] target/riscv: convert Xiangshan Nanhu " Paolo Bonzini
2025-02-28 10:27 ` Paolo Bonzini [this message]
2025-04-17 13:40 ` [PATCH v2 00/22] target/riscv: declarative CPU definitions Paolo Bonzini
2025-04-24 10:37 ` Alistair Francis
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