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From: Brian Cain <brian.cain@oss.qualcomm.com>
To: qemu-devel@nongnu.org
Cc: brian.cain@oss.qualcomm.com, richard.henderson@linaro.org,
	philmd@linaro.org, quic_mathbern@quicinc.com, ale@rev.ng,
	anjo@rev.ng, quic_mliebel@quicinc.com, ltaylorsimpson@gmail.com,
	alex.bennee@linaro.org, quic_mburton@quicinc.com,
	sidneym@quicinc.com, Brian Cain <bcain@quicinc.com>
Subject: [PATCH 15/39] target/hexagon: Implement hex_tlb_entry_get_perm()
Date: Fri, 28 Feb 2025 21:28:21 -0800	[thread overview]
Message-ID: <20250301052845.1012069-16-brian.cain@oss.qualcomm.com> (raw)
In-Reply-To: <20250301052845.1012069-1-brian.cain@oss.qualcomm.com>

From: Brian Cain <bcain@quicinc.com>

Signed-off-by: Brian Cain <brian.cain@oss.qualcomm.com>
---
 target/hexagon/hex_mmu.c | 54 +++++++++++++++++++++++++++++++++++++++-
 1 file changed, 53 insertions(+), 1 deletion(-)

diff --git a/target/hexagon/hex_mmu.c b/target/hexagon/hex_mmu.c
index 54c4ba2dbf..d2297c036d 100644
--- a/target/hexagon/hex_mmu.c
+++ b/target/hexagon/hex_mmu.c
@@ -267,7 +267,59 @@ static inline void hex_tlb_entry_get_perm(CPUHexagonState *env, uint64_t entry,
                                           int mmu_idx, int *prot,
                                           int32_t *excp)
 {
-    g_assert_not_reached();
+    bool perm_x = GET_TLB_FIELD(entry, PTE_X);
+    bool perm_w = GET_TLB_FIELD(entry, PTE_W);
+    bool perm_r = GET_TLB_FIELD(entry, PTE_R);
+    bool perm_u = GET_TLB_FIELD(entry, PTE_U);
+    bool user_idx = mmu_idx == MMU_USER_IDX;
+
+    if (mmu_idx == MMU_KERNEL_IDX) {
+        *prot = PAGE_VALID | PAGE_READ | PAGE_WRITE | PAGE_EXEC;
+        return;
+    }
+
+    *prot = PAGE_VALID;
+    switch (access_type) {
+    case MMU_INST_FETCH:
+        if (user_idx && !perm_u) {
+            *excp = HEX_EVENT_PRECISE;
+            env->cause_code = HEX_CAUSE_FETCH_NO_UPAGE;
+        } else if (!perm_x) {
+            *excp = HEX_EVENT_PRECISE;
+            env->cause_code = HEX_CAUSE_FETCH_NO_XPAGE;
+        }
+        break;
+    case MMU_DATA_LOAD:
+        if (user_idx && !perm_u) {
+            *excp = HEX_EVENT_PRECISE;
+            env->cause_code = HEX_CAUSE_PRIV_NO_UREAD;
+        } else if (!perm_r) {
+            *excp = HEX_EVENT_PRECISE;
+            env->cause_code = HEX_CAUSE_PRIV_NO_READ;
+        }
+        break;
+    case MMU_DATA_STORE:
+        if (user_idx && !perm_u) {
+            *excp = HEX_EVENT_PRECISE;
+            env->cause_code = HEX_CAUSE_PRIV_NO_UWRITE;
+        } else if (!perm_w) {
+            *excp = HEX_EVENT_PRECISE;
+            env->cause_code = HEX_CAUSE_PRIV_NO_WRITE;
+        }
+        break;
+    }
+
+    if (!user_idx || perm_u) {
+        if (perm_x) {
+            *prot |= PAGE_EXEC;
+        }
+        if (perm_r) {
+            *prot |= PAGE_READ;
+        }
+        if (perm_w) {
+            *prot |= PAGE_WRITE;
+        }
+    }
 }
 
 static inline bool hex_tlb_entry_match(CPUHexagonState *env, uint64_t entry,
-- 
2.34.1


  parent reply	other threads:[~2025-03-01  5:31 UTC|newest]

Thread overview: 112+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-03-01  5:28 [PATCH 00/39] hexagon system emu, part 2/3 Brian Cain
2025-03-01  5:28 ` [PATCH 01/39] target/hexagon: Implement ciad helper Brian Cain
2025-03-17 16:08   ` ltaylorsimpson
2025-03-18 14:44     ` Sid Manning
2025-09-02  1:32     ` Brian Cain
2025-03-01  5:28 ` [PATCH 02/39] target/hexagon: Implement {c,}swi helpers Brian Cain
2025-03-17 16:09   ` ltaylorsimpson
2025-03-01  5:28 ` [PATCH 03/39] target/hexagon: Implement iassign{r,w} helpers Brian Cain
2025-03-17 16:20   ` ltaylorsimpson
2025-03-01  5:28 ` [PATCH 04/39] target/hexagon: Implement start/stop helpers Brian Cain
2025-03-17 16:35   ` ltaylorsimpson
2025-09-02  1:33     ` Brian Cain
2025-03-01  5:28 ` [PATCH 05/39] target/hexagon: Implement modify SSR Brian Cain
2025-03-17 17:37   ` ltaylorsimpson
2025-03-18 18:34     ` Sid Manning
2025-03-18 19:14       ` ltaylorsimpson
2025-03-18 23:47         ` Brian Cain
2025-03-19 16:39           ` ltaylorsimpson
2025-03-19 16:58             ` Richard Henderson
2025-09-02  1:39               ` Brian Cain
2025-03-01  5:28 ` [PATCH 06/39] target/hexagon: Implement {g,s}etimask helpers Brian Cain
2025-03-17 17:44   ` ltaylorsimpson
2025-03-21 21:48     ` Sid Manning
2025-09-02  1:44       ` Brian Cain
2025-03-01  5:28 ` [PATCH 07/39] target/hexagon: Implement wait helper Brian Cain
2025-03-17 18:37   ` ltaylorsimpson
2025-09-02  1:46     ` Brian Cain
2025-03-01  5:28 ` [PATCH 08/39] target/hexagon: Implement get_exe_mode() Brian Cain
2025-03-17 18:43   ` ltaylorsimpson
2025-04-02  2:03     ` Brian Cain
2025-03-01  5:28 ` [PATCH 09/39] target/hexagon: Implement arch_get_system_reg() Brian Cain
2025-03-17 18:46   ` ltaylorsimpson
2025-03-01  5:28 ` [PATCH 10/39] target/hexagon: Implement arch_{s, g}et_{thread, system}_reg() Brian Cain via
2025-03-17 19:24   ` ltaylorsimpson
2025-09-02  1:50     ` [PATCH 10/39] target/hexagon: Implement arch_{s,g}et_{thread,system}_reg() Brian Cain
2025-03-01  5:28 ` [PATCH 11/39] target/hexagon: Add representation to count cycles Brian Cain
2025-03-17 19:33   ` ltaylorsimpson
2025-09-02  1:52     ` Brian Cain
2025-03-01  5:28 ` [PATCH 12/39] target/hexagon: Add implementation of cycle counters Brian Cain
2025-03-19 19:50   ` ltaylorsimpson
2025-04-02  2:44     ` Brian Cain
     [not found]     ` <7274cd69-f4e7-40b5-b850-cbd9099ed8ac@oss.qualcomm.com>
2025-09-02  1:56       ` Brian Cain
2025-03-01  5:28 ` [PATCH 13/39] target/hexagon: Implement modify_syscfg() Brian Cain
2025-03-19 21:12   ` ltaylorsimpson
2025-09-02  1:58     ` Brian Cain
2025-03-01  5:28 ` [PATCH 14/39] target/hexagon: Add system event, cause codes Brian Cain
2025-03-17 19:40   ` ltaylorsimpson
2025-03-01  5:28 ` Brian Cain [this message]
2025-03-17 19:37   ` [PATCH 15/39] target/hexagon: Implement hex_tlb_entry_get_perm() ltaylorsimpson
2025-03-01  5:28 ` [PATCH 16/39] target/hexagon: Implement hex_tlb_lookup_by_asid() Brian Cain
2025-03-17 19:42   ` ltaylorsimpson
2025-03-01  5:28 ` [PATCH 17/39] target/hexagon: Implement software interrupt Brian Cain
2025-03-19 21:28   ` ltaylorsimpson
2025-03-24 15:51     ` Sid Manning
2025-09-02  2:03     ` Brian Cain
2025-03-01  5:28 ` [PATCH 18/39] target/hexagon: Implement exec_interrupt, set_irq Brian Cain
2025-03-19 21:33   ` ltaylorsimpson
2025-03-01  5:28 ` [PATCH 19/39] target/hexagon: Implement hexagon_tlb_fill() Brian Cain
2025-03-17 19:55   ` ltaylorsimpson
2025-03-01  5:28 ` [PATCH 20/39] target/hexagon: Implement siad inst Brian Cain
2025-03-17 19:57   ` ltaylorsimpson
2025-03-01  5:28 ` [PATCH 21/39] target/hexagon: Implement hexagon_resume_threads() Brian Cain
2025-03-19 21:36   ` ltaylorsimpson
2025-03-01  5:28 ` [PATCH 22/39] target/hexagon: Implement setprio, resched Brian Cain
2025-03-20 19:44   ` ltaylorsimpson
2025-03-20 20:25     ` Sid Manning
2025-03-20 22:28       ` ltaylorsimpson
2025-09-02  2:08         ` Brian Cain
2025-03-01  5:28 ` [PATCH 23/39] target/hexagon: Add sysemu_ops, cpu_get_phys_page_debug() Brian Cain
2025-03-20 20:02   ` ltaylorsimpson
2025-03-01  5:28 ` [PATCH 24/39] target/hexagon: Add exec-start-addr prop Brian Cain
2025-03-17 20:03   ` ltaylorsimpson
2025-09-02  2:12     ` Brian Cain
2025-03-01  5:28 ` [PATCH 25/39] target/hexagon: Add hexagon_cpu_mmu_index() Brian Cain
2025-03-17 20:07   ` ltaylorsimpson
2025-03-01  5:28 ` [PATCH 26/39] target/hexagon: Decode trap1, rte as COF Brian Cain
2025-03-17 20:08   ` ltaylorsimpson
2025-03-01  5:28 ` [PATCH 27/39] target/hexagon: Implement hexagon_find_last_irq() Brian Cain
2025-03-17 20:09   ` ltaylorsimpson
2025-03-01  5:28 ` [PATCH 28/39] target/hexagon: Implement modify_ssr, resched, pending_interrupt Brian Cain
2025-03-17 20:12   ` ltaylorsimpson
2025-03-01  5:28 ` [PATCH 29/39] target/hexagon: Add pkt_ends_tb to translation Brian Cain
2025-03-17 20:20   ` ltaylorsimpson
2025-03-01  5:28 ` [PATCH 30/39] target/hexagon: Add next_PC, {s,g}reg writes Brian Cain
2025-03-18 18:50   ` ltaylorsimpson
2025-09-02  2:35     ` Brian Cain
2025-03-01  5:28 ` [PATCH 31/39] target/hexagon: Add implicit sysreg writes Brian Cain
2025-03-18 19:18   ` ltaylorsimpson
2025-03-01  5:28 ` [PATCH 32/39] target/hexagon: Define system, guest reg names Brian Cain
2025-03-19 16:48   ` ltaylorsimpson
2025-03-01  5:28 ` [PATCH 33/39] target/hexagon: initialize sys/guest reg TCGvs Brian Cain
2025-03-19 16:53   ` ltaylorsimpson
2025-03-01  5:28 ` [PATCH 34/39] target/hexagon: Add TLB, k0 {un,}lock Brian Cain
2025-03-03 16:24   ` Brian Cain
2025-03-04 23:09     ` ltaylorsimpson
2025-03-04 23:57       ` Philippe Mathieu-Daudé
2025-03-05  0:05         ` ltaylorsimpson
2025-03-05  0:19           ` Philippe Mathieu-Daudé
2025-03-05  0:45             ` ltaylorsimpson
2025-03-19 17:01   ` ltaylorsimpson
2025-03-01  5:28 ` [PATCH 35/39] target/hexagon: Define gen_precise_exception() Brian Cain
2025-03-19 17:20   ` ltaylorsimpson
2025-03-01  5:28 ` [PATCH 36/39] target/hexagon: Add TCG overrides for transfer insts Brian Cain
2025-03-19 17:22   ` ltaylorsimpson
2025-03-01  5:28 ` [PATCH 37/39] target/hexagon: Add support for loadw_phys Brian Cain
2025-03-20 20:04   ` ltaylorsimpson
2025-03-01  5:28 ` [PATCH 38/39] target/hexagon: Add guest reg reading functionality Brian Cain
2025-03-19 18:36   ` ltaylorsimpson
2025-09-02  2:40     ` Brian Cain
2025-03-01  5:28 ` [PATCH 39/39] target/hexagon: Add pcycle setting functionality Brian Cain
2025-03-19 18:49   ` ltaylorsimpson
2025-09-02  2:42     ` Brian Cain

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