From: Brian Cain <brian.cain@oss.qualcomm.com>
To: qemu-devel@nongnu.org
Cc: brian.cain@oss.qualcomm.com, richard.henderson@linaro.org,
philmd@linaro.org, quic_mathbern@quicinc.com, ale@rev.ng,
anjo@rev.ng, quic_mliebel@quicinc.com, ltaylorsimpson@gmail.com,
alex.bennee@linaro.org, quic_mburton@quicinc.com,
sidneym@quicinc.com, Brian Cain <bcain@quicinc.com>
Subject: [PATCH 22/39] target/hexagon: Implement setprio, resched
Date: Fri, 28 Feb 2025 21:28:28 -0800 [thread overview]
Message-ID: <20250301052845.1012069-23-brian.cain@oss.qualcomm.com> (raw)
In-Reply-To: <20250301052845.1012069-1-brian.cain@oss.qualcomm.com>
From: Brian Cain <bcain@quicinc.com>
The hardware-assisted scheduler helps manage tasks on the run queue
and interrupt steering.
This instruction is defined in the Qualcomm Hexagon V71 Programmer's Reference
Manual -
https://docs.qualcomm.com/bundle/publicresource/80-N2040-51_REV_AB_Hexagon_V71_ProgrammerS_Reference_Manual.pdf
See §11.9.2 SYSTEM MONITOR.
Signed-off-by: Brian Cain <brian.cain@oss.qualcomm.com>
---
target/hexagon/op_helper.c | 65 ++++++++++++++++++++++++++++++++++++++
1 file changed, 65 insertions(+)
diff --git a/target/hexagon/op_helper.c b/target/hexagon/op_helper.c
index 0dce133d3a..d0dc4afac7 100644
--- a/target/hexagon/op_helper.c
+++ b/target/hexagon/op_helper.c
@@ -1465,6 +1465,57 @@ void HELPER(stop)(CPUHexagonState *env)
hexagon_stop_thread(env);
}
+static inline QEMU_ALWAYS_INLINE void resched(CPUHexagonState *env)
+{
+ uint32_t schedcfg;
+ uint32_t schedcfg_en;
+ int int_number;
+ CPUState *cs;
+ uint32_t lowest_th_prio = 0; /* 0 is highest prio */
+ uint32_t bestwait_reg;
+ uint32_t best_prio;
+
+ BQL_LOCK_GUARD();
+ qemu_log_mask(CPU_LOG_INT, "%s: check resched\n", __func__);
+ schedcfg = arch_get_system_reg(env, HEX_SREG_SCHEDCFG);
+ schedcfg_en = GET_FIELD(SCHEDCFG_EN, schedcfg);
+ int_number = GET_FIELD(SCHEDCFG_INTNO, schedcfg);
+
+ if (!schedcfg_en) {
+ return;
+ }
+
+ CPU_FOREACH(cs) {
+ HexagonCPU *thread = HEXAGON_CPU(cs);
+ CPUHexagonState *thread_env = &(thread->env);
+ uint32_t th_prio = GET_FIELD(
+ STID_PRIO, arch_get_system_reg(thread_env, HEX_SREG_STID));
+ if (!hexagon_thread_is_enabled(thread_env)) {
+ continue;
+ }
+
+ lowest_th_prio = (lowest_th_prio > th_prio)
+ ? lowest_th_prio
+ : th_prio;
+ }
+
+ bestwait_reg = arch_get_system_reg(env, HEX_SREG_BESTWAIT);
+ best_prio = GET_FIELD(BESTWAIT_PRIO, bestwait_reg);
+
+ /*
+ * If the lowest priority thread is lower priority than the
+ * value in the BESTWAIT register, we must raise the reschedule
+ * interrupt on the lowest priority thread.
+ */
+ if (lowest_th_prio > best_prio) {
+ qemu_log_mask(CPU_LOG_INT,
+ "%s: raising resched int %d, cur PC 0x" TARGET_FMT_lx "\n",
+ __func__, int_number, arch_get_thread_reg(env, HEX_REG_PC));
+ SET_SYSTEM_FIELD(env, HEX_SREG_BESTWAIT, BESTWAIT_PRIO, 0x1ff);
+ hex_raise_interrupts(env, 1 << int_number, CPU_INTERRUPT_SWI);
+ }
+}
+
void HELPER(wait)(CPUHexagonState *env, target_ulong PC)
{
BQL_LOCK_GUARD();
@@ -1715,6 +1766,20 @@ uint64_t HELPER(greg_read_pair)(CPUHexagonState *env, uint32_t reg)
void HELPER(setprio)(CPUHexagonState *env, uint32_t thread, uint32_t prio)
{
+ CPUState *cs;
+
+ BQL_LOCK_GUARD();
+ CPU_FOREACH(cs) {
+ HexagonCPU *found_cpu = HEXAGON_CPU(cs);
+ CPUHexagonState *found_env = &found_cpu->env;
+ if (thread == found_env->threadId) {
+ SET_SYSTEM_FIELD(found_env, HEX_SREG_STID, STID_PRIO, prio);
+ qemu_log_mask(CPU_LOG_INT, "%s: tid %d prio = 0x%x\n",
+ __func__, found_env->threadId, prio);
+ resched(env);
+ return;
+ }
+ }
g_assert_not_reached();
}
--
2.34.1
next prev parent reply other threads:[~2025-03-01 5:37 UTC|newest]
Thread overview: 112+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-03-01 5:28 [PATCH 00/39] hexagon system emu, part 2/3 Brian Cain
2025-03-01 5:28 ` [PATCH 01/39] target/hexagon: Implement ciad helper Brian Cain
2025-03-17 16:08 ` ltaylorsimpson
2025-03-18 14:44 ` Sid Manning
2025-09-02 1:32 ` Brian Cain
2025-03-01 5:28 ` [PATCH 02/39] target/hexagon: Implement {c,}swi helpers Brian Cain
2025-03-17 16:09 ` ltaylorsimpson
2025-03-01 5:28 ` [PATCH 03/39] target/hexagon: Implement iassign{r,w} helpers Brian Cain
2025-03-17 16:20 ` ltaylorsimpson
2025-03-01 5:28 ` [PATCH 04/39] target/hexagon: Implement start/stop helpers Brian Cain
2025-03-17 16:35 ` ltaylorsimpson
2025-09-02 1:33 ` Brian Cain
2025-03-01 5:28 ` [PATCH 05/39] target/hexagon: Implement modify SSR Brian Cain
2025-03-17 17:37 ` ltaylorsimpson
2025-03-18 18:34 ` Sid Manning
2025-03-18 19:14 ` ltaylorsimpson
2025-03-18 23:47 ` Brian Cain
2025-03-19 16:39 ` ltaylorsimpson
2025-03-19 16:58 ` Richard Henderson
2025-09-02 1:39 ` Brian Cain
2025-03-01 5:28 ` [PATCH 06/39] target/hexagon: Implement {g,s}etimask helpers Brian Cain
2025-03-17 17:44 ` ltaylorsimpson
2025-03-21 21:48 ` Sid Manning
2025-09-02 1:44 ` Brian Cain
2025-03-01 5:28 ` [PATCH 07/39] target/hexagon: Implement wait helper Brian Cain
2025-03-17 18:37 ` ltaylorsimpson
2025-09-02 1:46 ` Brian Cain
2025-03-01 5:28 ` [PATCH 08/39] target/hexagon: Implement get_exe_mode() Brian Cain
2025-03-17 18:43 ` ltaylorsimpson
2025-04-02 2:03 ` Brian Cain
2025-03-01 5:28 ` [PATCH 09/39] target/hexagon: Implement arch_get_system_reg() Brian Cain
2025-03-17 18:46 ` ltaylorsimpson
2025-03-01 5:28 ` [PATCH 10/39] target/hexagon: Implement arch_{s, g}et_{thread, system}_reg() Brian Cain via
2025-03-17 19:24 ` ltaylorsimpson
2025-09-02 1:50 ` [PATCH 10/39] target/hexagon: Implement arch_{s,g}et_{thread,system}_reg() Brian Cain
2025-03-01 5:28 ` [PATCH 11/39] target/hexagon: Add representation to count cycles Brian Cain
2025-03-17 19:33 ` ltaylorsimpson
2025-09-02 1:52 ` Brian Cain
2025-03-01 5:28 ` [PATCH 12/39] target/hexagon: Add implementation of cycle counters Brian Cain
2025-03-19 19:50 ` ltaylorsimpson
2025-04-02 2:44 ` Brian Cain
[not found] ` <7274cd69-f4e7-40b5-b850-cbd9099ed8ac@oss.qualcomm.com>
2025-09-02 1:56 ` Brian Cain
2025-03-01 5:28 ` [PATCH 13/39] target/hexagon: Implement modify_syscfg() Brian Cain
2025-03-19 21:12 ` ltaylorsimpson
2025-09-02 1:58 ` Brian Cain
2025-03-01 5:28 ` [PATCH 14/39] target/hexagon: Add system event, cause codes Brian Cain
2025-03-17 19:40 ` ltaylorsimpson
2025-03-01 5:28 ` [PATCH 15/39] target/hexagon: Implement hex_tlb_entry_get_perm() Brian Cain
2025-03-17 19:37 ` ltaylorsimpson
2025-03-01 5:28 ` [PATCH 16/39] target/hexagon: Implement hex_tlb_lookup_by_asid() Brian Cain
2025-03-17 19:42 ` ltaylorsimpson
2025-03-01 5:28 ` [PATCH 17/39] target/hexagon: Implement software interrupt Brian Cain
2025-03-19 21:28 ` ltaylorsimpson
2025-03-24 15:51 ` Sid Manning
2025-09-02 2:03 ` Brian Cain
2025-03-01 5:28 ` [PATCH 18/39] target/hexagon: Implement exec_interrupt, set_irq Brian Cain
2025-03-19 21:33 ` ltaylorsimpson
2025-03-01 5:28 ` [PATCH 19/39] target/hexagon: Implement hexagon_tlb_fill() Brian Cain
2025-03-17 19:55 ` ltaylorsimpson
2025-03-01 5:28 ` [PATCH 20/39] target/hexagon: Implement siad inst Brian Cain
2025-03-17 19:57 ` ltaylorsimpson
2025-03-01 5:28 ` [PATCH 21/39] target/hexagon: Implement hexagon_resume_threads() Brian Cain
2025-03-19 21:36 ` ltaylorsimpson
2025-03-01 5:28 ` Brian Cain [this message]
2025-03-20 19:44 ` [PATCH 22/39] target/hexagon: Implement setprio, resched ltaylorsimpson
2025-03-20 20:25 ` Sid Manning
2025-03-20 22:28 ` ltaylorsimpson
2025-09-02 2:08 ` Brian Cain
2025-03-01 5:28 ` [PATCH 23/39] target/hexagon: Add sysemu_ops, cpu_get_phys_page_debug() Brian Cain
2025-03-20 20:02 ` ltaylorsimpson
2025-03-01 5:28 ` [PATCH 24/39] target/hexagon: Add exec-start-addr prop Brian Cain
2025-03-17 20:03 ` ltaylorsimpson
2025-09-02 2:12 ` Brian Cain
2025-03-01 5:28 ` [PATCH 25/39] target/hexagon: Add hexagon_cpu_mmu_index() Brian Cain
2025-03-17 20:07 ` ltaylorsimpson
2025-03-01 5:28 ` [PATCH 26/39] target/hexagon: Decode trap1, rte as COF Brian Cain
2025-03-17 20:08 ` ltaylorsimpson
2025-03-01 5:28 ` [PATCH 27/39] target/hexagon: Implement hexagon_find_last_irq() Brian Cain
2025-03-17 20:09 ` ltaylorsimpson
2025-03-01 5:28 ` [PATCH 28/39] target/hexagon: Implement modify_ssr, resched, pending_interrupt Brian Cain
2025-03-17 20:12 ` ltaylorsimpson
2025-03-01 5:28 ` [PATCH 29/39] target/hexagon: Add pkt_ends_tb to translation Brian Cain
2025-03-17 20:20 ` ltaylorsimpson
2025-03-01 5:28 ` [PATCH 30/39] target/hexagon: Add next_PC, {s,g}reg writes Brian Cain
2025-03-18 18:50 ` ltaylorsimpson
2025-09-02 2:35 ` Brian Cain
2025-03-01 5:28 ` [PATCH 31/39] target/hexagon: Add implicit sysreg writes Brian Cain
2025-03-18 19:18 ` ltaylorsimpson
2025-03-01 5:28 ` [PATCH 32/39] target/hexagon: Define system, guest reg names Brian Cain
2025-03-19 16:48 ` ltaylorsimpson
2025-03-01 5:28 ` [PATCH 33/39] target/hexagon: initialize sys/guest reg TCGvs Brian Cain
2025-03-19 16:53 ` ltaylorsimpson
2025-03-01 5:28 ` [PATCH 34/39] target/hexagon: Add TLB, k0 {un,}lock Brian Cain
2025-03-03 16:24 ` Brian Cain
2025-03-04 23:09 ` ltaylorsimpson
2025-03-04 23:57 ` Philippe Mathieu-Daudé
2025-03-05 0:05 ` ltaylorsimpson
2025-03-05 0:19 ` Philippe Mathieu-Daudé
2025-03-05 0:45 ` ltaylorsimpson
2025-03-19 17:01 ` ltaylorsimpson
2025-03-01 5:28 ` [PATCH 35/39] target/hexagon: Define gen_precise_exception() Brian Cain
2025-03-19 17:20 ` ltaylorsimpson
2025-03-01 5:28 ` [PATCH 36/39] target/hexagon: Add TCG overrides for transfer insts Brian Cain
2025-03-19 17:22 ` ltaylorsimpson
2025-03-01 5:28 ` [PATCH 37/39] target/hexagon: Add support for loadw_phys Brian Cain
2025-03-20 20:04 ` ltaylorsimpson
2025-03-01 5:28 ` [PATCH 38/39] target/hexagon: Add guest reg reading functionality Brian Cain
2025-03-19 18:36 ` ltaylorsimpson
2025-09-02 2:40 ` Brian Cain
2025-03-01 5:28 ` [PATCH 39/39] target/hexagon: Add pcycle setting functionality Brian Cain
2025-03-19 18:49 ` ltaylorsimpson
2025-09-02 2:42 ` Brian Cain
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