From: Brian Cain <brian.cain@oss.qualcomm.com>
To: qemu-devel@nongnu.org
Cc: brian.cain@oss.qualcomm.com, richard.henderson@linaro.org,
philmd@linaro.org, quic_mathbern@quicinc.com, ale@rev.ng,
anjo@rev.ng, quic_mliebel@quicinc.com, ltaylorsimpson@gmail.com,
alex.bennee@linaro.org, quic_mburton@quicinc.com,
sidneym@quicinc.com, Brian Cain <bcain@quicinc.com>
Subject: [PATCH 29/39] target/hexagon: Add pkt_ends_tb to translation
Date: Fri, 28 Feb 2025 21:28:35 -0800 [thread overview]
Message-ID: <20250301052845.1012069-30-brian.cain@oss.qualcomm.com> (raw)
In-Reply-To: <20250301052845.1012069-1-brian.cain@oss.qualcomm.com>
From: Brian Cain <bcain@quicinc.com>
Signed-off-by: Brian Cain <brian.cain@oss.qualcomm.com>
---
target/hexagon/translate.h | 1 +
target/hexagon/translate.c | 99 +++++++++++++++++++++++++++++++++++++-
2 files changed, 99 insertions(+), 1 deletion(-)
diff --git a/target/hexagon/translate.h b/target/hexagon/translate.h
index 9bc4b3ce8b..c9533fee1f 100644
--- a/target/hexagon/translate.h
+++ b/target/hexagon/translate.h
@@ -84,6 +84,7 @@ typedef struct DisasContext {
TCGv branch_taken;
TCGv dczero_addr;
bool pcycle_enabled;
+ bool pkt_ends_tb;
uint32_t num_cycles;
} DisasContext;
diff --git a/target/hexagon/translate.c b/target/hexagon/translate.c
index 060df6e5eb..475726388a 100644
--- a/target/hexagon/translate.c
+++ b/target/hexagon/translate.c
@@ -259,6 +259,18 @@ static bool check_for_attrib(Packet *pkt, int attrib)
return false;
}
+#ifndef CONFIG_USER_ONLY
+static bool check_for_opcode(Packet *pkt, uint16_t opcode)
+{
+ for (int i = 0; i < pkt->num_insns; i++) {
+ if (pkt->insn[i].opcode == opcode) {
+ return true;
+ }
+ }
+ return false;
+}
+#endif
+
static bool need_slot_cancelled(Packet *pkt)
{
/* We only need slot_cancelled for conditional store instructions */
@@ -272,6 +284,90 @@ static bool need_slot_cancelled(Packet *pkt)
return false;
}
+#ifndef CONFIG_USER_ONLY
+static bool sreg_write_to_global(int reg_num)
+{
+ return reg_num == HEX_SREG_SSR ||
+ reg_num == HEX_SREG_STID ||
+ reg_num == HEX_SREG_IMASK ||
+ reg_num == HEX_SREG_IPENDAD ||
+ reg_num == HEX_SREG_BESTWAIT ||
+ reg_num == HEX_SREG_SCHEDCFG;
+}
+
+static bool has_sreg_write_to_global(Packet const *pkt)
+{
+ for (int i = 0; i < pkt->num_insns; i++) {
+ Insn const *insn = &pkt->insn[i];
+ uint16_t opcode = insn->opcode;
+ if (opcode == Y2_tfrsrcr) {
+ /* Write to a single sreg */
+ int reg_num = insn->regno[0];
+ if (sreg_write_to_global(reg_num)) {
+ return true;
+ }
+ } else if (opcode == Y4_tfrspcp) {
+ /* Write to a sreg pair */
+ int reg_num = insn->regno[0];
+ if (sreg_write_to_global(reg_num)) {
+ return true;
+ }
+ if (sreg_write_to_global(reg_num + 1)) {
+ return true;
+ }
+ }
+ }
+ return false;
+}
+#endif
+
+static bool pkt_ends_tb(Packet *pkt)
+{
+ if (pkt->pkt_has_cof) {
+ return true;
+ }
+#ifndef CONFIG_USER_ONLY
+ /* System mode instructions that end TLB */
+ if (check_for_opcode(pkt, Y2_swi) ||
+ check_for_opcode(pkt, Y2_cswi) ||
+ check_for_opcode(pkt, Y2_ciad) ||
+ check_for_opcode(pkt, Y4_siad) ||
+ check_for_opcode(pkt, Y2_wait) ||
+ check_for_opcode(pkt, Y2_resume) ||
+ check_for_opcode(pkt, Y2_iassignw) ||
+ check_for_opcode(pkt, Y2_setimask) ||
+ check_for_opcode(pkt, Y4_nmi) ||
+ check_for_opcode(pkt, Y2_setprio) ||
+ check_for_opcode(pkt, Y2_start) ||
+ check_for_opcode(pkt, Y2_stop) ||
+ check_for_opcode(pkt, Y2_k0lock) ||
+ check_for_opcode(pkt, Y2_k0unlock) ||
+ check_for_opcode(pkt, Y2_tlblock) ||
+ check_for_opcode(pkt, Y2_tlbunlock) ||
+ check_for_opcode(pkt, Y2_break) ||
+ check_for_opcode(pkt, Y2_isync) ||
+ check_for_opcode(pkt, Y2_syncht) ||
+ check_for_opcode(pkt, Y2_tlbp) ||
+ check_for_opcode(pkt, Y2_tlbw) ||
+ check_for_opcode(pkt, Y5_ctlbw) ||
+ check_for_opcode(pkt, Y5_tlbasidi)) {
+ return true;
+ }
+
+ /*
+ * Check for sreg writes that would end the TB
+ */
+ if (check_for_attrib(pkt, A_IMPLICIT_WRITES_SSR)) {
+ return true;
+ }
+ if (has_sreg_write_to_global(pkt)) {
+ return true;
+ }
+#endif
+ return false;
+}
+
+
static bool need_next_PC(DisasContext *ctx)
{
Packet *pkt = ctx->pkt;
@@ -473,6 +569,7 @@ static void gen_start_packet(DisasContext *ctx)
tcg_gen_movi_tl(hex_slot_cancelled, 0);
}
ctx->branch_taken = NULL;
+ ctx->pkt_ends_tb = pkt_ends_tb(pkt);
if (pkt->pkt_has_cof) {
ctx->branch_taken = tcg_temp_new();
if (pkt->pkt_has_multi_cof) {
@@ -927,7 +1024,7 @@ static void gen_commit_packet(DisasContext *ctx)
pkt->vhist_insn->generate(ctx);
}
- if (pkt->pkt_has_cof) {
+ if (ctx->pkt_ends_tb || ctx->base.is_jmp == DISAS_NORETURN) {
gen_end_tb(ctx);
}
}
--
2.34.1
next prev parent reply other threads:[~2025-03-01 5:35 UTC|newest]
Thread overview: 112+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-03-01 5:28 [PATCH 00/39] hexagon system emu, part 2/3 Brian Cain
2025-03-01 5:28 ` [PATCH 01/39] target/hexagon: Implement ciad helper Brian Cain
2025-03-17 16:08 ` ltaylorsimpson
2025-03-18 14:44 ` Sid Manning
2025-09-02 1:32 ` Brian Cain
2025-03-01 5:28 ` [PATCH 02/39] target/hexagon: Implement {c,}swi helpers Brian Cain
2025-03-17 16:09 ` ltaylorsimpson
2025-03-01 5:28 ` [PATCH 03/39] target/hexagon: Implement iassign{r,w} helpers Brian Cain
2025-03-17 16:20 ` ltaylorsimpson
2025-03-01 5:28 ` [PATCH 04/39] target/hexagon: Implement start/stop helpers Brian Cain
2025-03-17 16:35 ` ltaylorsimpson
2025-09-02 1:33 ` Brian Cain
2025-03-01 5:28 ` [PATCH 05/39] target/hexagon: Implement modify SSR Brian Cain
2025-03-17 17:37 ` ltaylorsimpson
2025-03-18 18:34 ` Sid Manning
2025-03-18 19:14 ` ltaylorsimpson
2025-03-18 23:47 ` Brian Cain
2025-03-19 16:39 ` ltaylorsimpson
2025-03-19 16:58 ` Richard Henderson
2025-09-02 1:39 ` Brian Cain
2025-03-01 5:28 ` [PATCH 06/39] target/hexagon: Implement {g,s}etimask helpers Brian Cain
2025-03-17 17:44 ` ltaylorsimpson
2025-03-21 21:48 ` Sid Manning
2025-09-02 1:44 ` Brian Cain
2025-03-01 5:28 ` [PATCH 07/39] target/hexagon: Implement wait helper Brian Cain
2025-03-17 18:37 ` ltaylorsimpson
2025-09-02 1:46 ` Brian Cain
2025-03-01 5:28 ` [PATCH 08/39] target/hexagon: Implement get_exe_mode() Brian Cain
2025-03-17 18:43 ` ltaylorsimpson
2025-04-02 2:03 ` Brian Cain
2025-03-01 5:28 ` [PATCH 09/39] target/hexagon: Implement arch_get_system_reg() Brian Cain
2025-03-17 18:46 ` ltaylorsimpson
2025-03-01 5:28 ` [PATCH 10/39] target/hexagon: Implement arch_{s, g}et_{thread, system}_reg() Brian Cain via
2025-03-17 19:24 ` ltaylorsimpson
2025-09-02 1:50 ` [PATCH 10/39] target/hexagon: Implement arch_{s,g}et_{thread,system}_reg() Brian Cain
2025-03-01 5:28 ` [PATCH 11/39] target/hexagon: Add representation to count cycles Brian Cain
2025-03-17 19:33 ` ltaylorsimpson
2025-09-02 1:52 ` Brian Cain
2025-03-01 5:28 ` [PATCH 12/39] target/hexagon: Add implementation of cycle counters Brian Cain
2025-03-19 19:50 ` ltaylorsimpson
2025-04-02 2:44 ` Brian Cain
[not found] ` <7274cd69-f4e7-40b5-b850-cbd9099ed8ac@oss.qualcomm.com>
2025-09-02 1:56 ` Brian Cain
2025-03-01 5:28 ` [PATCH 13/39] target/hexagon: Implement modify_syscfg() Brian Cain
2025-03-19 21:12 ` ltaylorsimpson
2025-09-02 1:58 ` Brian Cain
2025-03-01 5:28 ` [PATCH 14/39] target/hexagon: Add system event, cause codes Brian Cain
2025-03-17 19:40 ` ltaylorsimpson
2025-03-01 5:28 ` [PATCH 15/39] target/hexagon: Implement hex_tlb_entry_get_perm() Brian Cain
2025-03-17 19:37 ` ltaylorsimpson
2025-03-01 5:28 ` [PATCH 16/39] target/hexagon: Implement hex_tlb_lookup_by_asid() Brian Cain
2025-03-17 19:42 ` ltaylorsimpson
2025-03-01 5:28 ` [PATCH 17/39] target/hexagon: Implement software interrupt Brian Cain
2025-03-19 21:28 ` ltaylorsimpson
2025-03-24 15:51 ` Sid Manning
2025-09-02 2:03 ` Brian Cain
2025-03-01 5:28 ` [PATCH 18/39] target/hexagon: Implement exec_interrupt, set_irq Brian Cain
2025-03-19 21:33 ` ltaylorsimpson
2025-03-01 5:28 ` [PATCH 19/39] target/hexagon: Implement hexagon_tlb_fill() Brian Cain
2025-03-17 19:55 ` ltaylorsimpson
2025-03-01 5:28 ` [PATCH 20/39] target/hexagon: Implement siad inst Brian Cain
2025-03-17 19:57 ` ltaylorsimpson
2025-03-01 5:28 ` [PATCH 21/39] target/hexagon: Implement hexagon_resume_threads() Brian Cain
2025-03-19 21:36 ` ltaylorsimpson
2025-03-01 5:28 ` [PATCH 22/39] target/hexagon: Implement setprio, resched Brian Cain
2025-03-20 19:44 ` ltaylorsimpson
2025-03-20 20:25 ` Sid Manning
2025-03-20 22:28 ` ltaylorsimpson
2025-09-02 2:08 ` Brian Cain
2025-03-01 5:28 ` [PATCH 23/39] target/hexagon: Add sysemu_ops, cpu_get_phys_page_debug() Brian Cain
2025-03-20 20:02 ` ltaylorsimpson
2025-03-01 5:28 ` [PATCH 24/39] target/hexagon: Add exec-start-addr prop Brian Cain
2025-03-17 20:03 ` ltaylorsimpson
2025-09-02 2:12 ` Brian Cain
2025-03-01 5:28 ` [PATCH 25/39] target/hexagon: Add hexagon_cpu_mmu_index() Brian Cain
2025-03-17 20:07 ` ltaylorsimpson
2025-03-01 5:28 ` [PATCH 26/39] target/hexagon: Decode trap1, rte as COF Brian Cain
2025-03-17 20:08 ` ltaylorsimpson
2025-03-01 5:28 ` [PATCH 27/39] target/hexagon: Implement hexagon_find_last_irq() Brian Cain
2025-03-17 20:09 ` ltaylorsimpson
2025-03-01 5:28 ` [PATCH 28/39] target/hexagon: Implement modify_ssr, resched, pending_interrupt Brian Cain
2025-03-17 20:12 ` ltaylorsimpson
2025-03-01 5:28 ` Brian Cain [this message]
2025-03-17 20:20 ` [PATCH 29/39] target/hexagon: Add pkt_ends_tb to translation ltaylorsimpson
2025-03-01 5:28 ` [PATCH 30/39] target/hexagon: Add next_PC, {s,g}reg writes Brian Cain
2025-03-18 18:50 ` ltaylorsimpson
2025-09-02 2:35 ` Brian Cain
2025-03-01 5:28 ` [PATCH 31/39] target/hexagon: Add implicit sysreg writes Brian Cain
2025-03-18 19:18 ` ltaylorsimpson
2025-03-01 5:28 ` [PATCH 32/39] target/hexagon: Define system, guest reg names Brian Cain
2025-03-19 16:48 ` ltaylorsimpson
2025-03-01 5:28 ` [PATCH 33/39] target/hexagon: initialize sys/guest reg TCGvs Brian Cain
2025-03-19 16:53 ` ltaylorsimpson
2025-03-01 5:28 ` [PATCH 34/39] target/hexagon: Add TLB, k0 {un,}lock Brian Cain
2025-03-03 16:24 ` Brian Cain
2025-03-04 23:09 ` ltaylorsimpson
2025-03-04 23:57 ` Philippe Mathieu-Daudé
2025-03-05 0:05 ` ltaylorsimpson
2025-03-05 0:19 ` Philippe Mathieu-Daudé
2025-03-05 0:45 ` ltaylorsimpson
2025-03-19 17:01 ` ltaylorsimpson
2025-03-01 5:28 ` [PATCH 35/39] target/hexagon: Define gen_precise_exception() Brian Cain
2025-03-19 17:20 ` ltaylorsimpson
2025-03-01 5:28 ` [PATCH 36/39] target/hexagon: Add TCG overrides for transfer insts Brian Cain
2025-03-19 17:22 ` ltaylorsimpson
2025-03-01 5:28 ` [PATCH 37/39] target/hexagon: Add support for loadw_phys Brian Cain
2025-03-20 20:04 ` ltaylorsimpson
2025-03-01 5:28 ` [PATCH 38/39] target/hexagon: Add guest reg reading functionality Brian Cain
2025-03-19 18:36 ` ltaylorsimpson
2025-09-02 2:40 ` Brian Cain
2025-03-01 5:28 ` [PATCH 39/39] target/hexagon: Add pcycle setting functionality Brian Cain
2025-03-19 18:49 ` ltaylorsimpson
2025-09-02 2:42 ` Brian Cain
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