[PATCH 2/3] target/ppc: Avoid work if MMU SPRs are written with same value

[Nicholas Piggin <npiggin@gmail.com>]

Avoid TLB flushing and hflags recomputation if LPCR, LPIDR, or PIDR
are written with the same value. This is observed to happen in some
cases (e.g., in hypervisor real-mode exit fastpath handlers).

Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
---
 target/ppc/cpu.c         |  8 +++++++-
 target/ppc/misc_helper.c | 14 +++++++++++++-
 2 files changed, 20 insertions(+), 2 deletions(-)

diff --git a/target/ppc/cpu.c b/target/ppc/cpu.c
index cdd50cb36d6..0fa2ccfcb2f 100644
--- a/target/ppc/cpu.c
+++ b/target/ppc/cpu.c
@@ -97,8 +97,14 @@ void ppc_store_lpcr(PowerPCCPU *cpu, target_ulong val)
 {
     PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
     CPUPPCState *env = &cpu->env;
+    target_ulong old, new;
 
-    env->spr[SPR_LPCR] = val & pcc->lpcr_mask;
+    old = env->spr[SPR_LPCR];
+    new = val & pcc->lpcr_mask;
+    if (old == new) {
+        return;
+    }
+    env->spr[SPR_LPCR] = new;
     /* The gtse bit affects hflags */
     hreg_compute_hflags(env);
 
diff --git a/target/ppc/misc_helper.c b/target/ppc/misc_helper.c
index 179e8b6b4d2..ac439e00326 100644
--- a/target/ppc/misc_helper.c
+++ b/target/ppc/misc_helper.c
@@ -403,12 +403,24 @@ void helper_store_sprd(CPUPPCState *env, target_ulong val)
 
 void helper_store_pidr(CPUPPCState *env, target_ulong val)
 {
+    if (env->spr[SPR_BOOKS_PID] == (uint32_t)val) {
+        return;
+    }
+
     env->spr[SPR_BOOKS_PID] = (uint32_t)val;
-    tlb_flush(env_cpu(env));
+
+    if (env->spr[SPR_LPCR] & LPCR_HR) {
+        /* PID is only relevant to CPU translations when LPCR[HR]=1 */
+        tlb_flush(env_cpu(env));
+    }
 }
 
 void helper_store_lpidr(CPUPPCState *env, target_ulong val)
 {
+    if (env->spr[SPR_LPIDR] == (uint32_t)val) {
+        return;
+    }
+
     env->spr[SPR_LPIDR] = (uint32_t)val;
 
     /*
-- 
2.47.1