From: "Philippe Mathieu-Daudé" <philmd@linaro.org>
To: qemu-devel@nongnu.org
Subject: [PULL 10/54] accel/tcg: Restrict 'icount_align_option' global to TCG
Date: Thu, 6 Mar 2025 16:46:52 +0100 [thread overview]
Message-ID: <20250306154737.70886-11-philmd@linaro.org> (raw)
In-Reply-To: <20250306154737.70886-1-philmd@linaro.org>
Since commit 740b1759734 ("cpu-timers, icount: new modules")
we don't need to expose icount_align_option to all the
system code, we can restrict it to TCG. Since it is used as
a boolean, declare it as 'bool' type.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20250123234415.59850-10-philmd@linaro.org>
---
accel/tcg/internal-common.h | 2 ++
include/system/cpus.h | 2 --
accel/tcg/icount-common.c | 2 ++
system/globals.c | 1 -
4 files changed, 4 insertions(+), 3 deletions(-)
diff --git a/accel/tcg/internal-common.h b/accel/tcg/internal-common.h
index d3186721839..7ef620d9631 100644
--- a/accel/tcg/internal-common.h
+++ b/accel/tcg/internal-common.h
@@ -17,6 +17,8 @@ extern int64_t max_advance;
extern bool one_insn_per_tb;
+extern bool icount_align_option;
+
/*
* Return true if CS is not running in parallel with other cpus, either
* because there are no other cpus or we are within an exclusive context.
diff --git a/include/system/cpus.h b/include/system/cpus.h
index 3d8fd368f32..1cffeaaf5c4 100644
--- a/include/system/cpus.h
+++ b/include/system/cpus.h
@@ -38,8 +38,6 @@ void resume_all_vcpus(void);
void pause_all_vcpus(void);
void cpu_stop_current(void);
-extern int icount_align_option;
-
/* Unblock cpu */
void qemu_cpu_kick_self(void);
diff --git a/accel/tcg/icount-common.c b/accel/tcg/icount-common.c
index b178dccec45..402d3e3f4e8 100644
--- a/accel/tcg/icount-common.c
+++ b/accel/tcg/icount-common.c
@@ -48,6 +48,8 @@ static bool icount_sleep = true;
/* Arbitrarily pick 1MIPS as the minimum allowable speed. */
#define MAX_ICOUNT_SHIFT 10
+bool icount_align_option;
+
/* Do not count executed instructions */
ICountMode use_icount = ICOUNT_DISABLED;
diff --git a/system/globals.c b/system/globals.c
index 316623bd20a..9640c9511e9 100644
--- a/system/globals.c
+++ b/system/globals.c
@@ -58,7 +58,6 @@ unsigned int nb_prom_envs;
const char *prom_envs[MAX_PROM_ENVS];
uint8_t *boot_splash_filedata;
int only_migratable; /* turn it off unless user states otherwise */
-int icount_align_option;
/* The bytes in qemu_uuid are in the order specified by RFC4122, _not_ in the
* little-endian "wire format" described in the SMBIOS 2.6 specification.
--
2.47.1
next prev parent reply other threads:[~2025-03-06 15:54 UTC|newest]
Thread overview: 56+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-03-06 15:46 [PULL 00/54] Accelerators & CPU patches Philippe Mathieu-Daudé
2025-03-06 15:46 ` [PULL 01/54] qemu/compiler: Absorb 'clang-tsa.h' Philippe Mathieu-Daudé
2025-03-06 15:46 ` [PULL 02/54] gdbstub: Clarify no more than @gdb_num_core_regs can be accessed Philippe Mathieu-Daudé
2025-03-06 15:46 ` [PULL 03/54] gdbstub: Check for TCG before calling tb_flush() Philippe Mathieu-Daudé
2025-03-06 15:46 ` [PULL 04/54] cpus: Cache CPUClass early in instance_init() handler Philippe Mathieu-Daudé
2025-03-06 15:46 ` [PULL 05/54] cpus: Keep default fields initialization in cpu_common_initfn() Philippe Mathieu-Daudé
2025-03-06 15:46 ` [PULL 06/54] accel/accel: Make TYPE_ACCEL abstract Philippe Mathieu-Daudé
2025-03-06 15:46 ` [PULL 07/54] accel/tcg: Remove pointless initialization of cflags_next_tb Philippe Mathieu-Daudé
2025-03-06 15:46 ` [PULL 08/54] accel/tcg: Build tcg_flags helpers as common code Philippe Mathieu-Daudé
2025-03-06 15:46 ` [PULL 09/54] accel/tcg: Restrict tlb_init() / destroy() to TCG Philippe Mathieu-Daudé
2025-03-06 15:46 ` Philippe Mathieu-Daudé [this message]
2025-03-06 15:46 ` [PULL 11/54] accel/tcg: Rename 'hw/core/tcg-cpu-ops.h' -> 'accel/tcg/cpu-ops.h' Philippe Mathieu-Daudé
2025-03-06 15:46 ` [PULL 12/54] accel: Rename 'hw/core/accel-cpu.h' -> 'accel/accel-cpu-target.h' Philippe Mathieu-Daudé
2025-03-06 15:46 ` [PULL 13/54] accel: Forward-declare AccelOpsClass in 'qemu/typedefs.h' Philippe Mathieu-Daudé
2025-03-06 15:46 ` [PULL 14/54] accel/accel-cpu-target.h: Include missing 'cpu.h' header Philippe Mathieu-Daudé
2025-03-06 15:46 ` [PULL 15/54] accel/tcg: Include missing bswap headers in user-exec.c Philippe Mathieu-Daudé
2025-03-06 15:46 ` [PULL 16/54] accel/tcg: Take mmap lock in the whole cpu_memory_rw_debug() function Philippe Mathieu-Daudé
2025-03-06 15:46 ` [PULL 17/54] accel/tcg: Avoid using lock_user() in cpu_memory_rw_debug() Philippe Mathieu-Daudé
2025-03-06 15:47 ` [PULL 18/54] accel/tcg: Move cpu_memory_rw_debug() user implementation to user-exec.c Philippe Mathieu-Daudé
2025-03-06 15:47 ` [PULL 19/54] accel/kvm: Remove unused 'system/cpus.h' header in kvm-cpus.h Philippe Mathieu-Daudé
2025-03-06 15:47 ` [PULL 20/54] cpus: Fix style in cpu-target.c Philippe Mathieu-Daudé
2025-03-06 15:47 ` [PULL 21/54] cpus: Restrict cpu_common_post_load() code to TCG Philippe Mathieu-Daudé
2025-03-06 15:47 ` [PULL 22/54] cpus: Have cpu_class_init_props() per user / system emulation Philippe Mathieu-Daudé
2025-03-06 15:47 ` [PULL 23/54] cpus: Have cpu_exec_initfn() " Philippe Mathieu-Daudé
2025-03-06 15:47 ` [PULL 24/54] cpus: Restrict cpu_get_memory_mapping() to " Philippe Mathieu-Daudé
2025-03-06 15:47 ` [PULL 25/54] hw/core/generic-loader: Do not open-code cpu_set_pc() Philippe Mathieu-Daudé
2025-03-06 15:47 ` [PULL 26/54] target/microblaze: Explode MO_TExx -> MO_TE | MO_xx Philippe Mathieu-Daudé
2025-03-06 15:47 ` [PULL 27/54] target/microblaze: Set MO_TE once in do_load() / do_store() Philippe Mathieu-Daudé
2025-03-06 15:47 ` [PULL 28/54] target/microblaze: Introduce mo_endian() helper Philippe Mathieu-Daudé
2025-03-06 15:47 ` [PULL 29/54] target/microblaze: Consider endianness while translating code Philippe Mathieu-Daudé
2025-03-06 15:47 ` [PULL 30/54] target/i386/hvf: Variable type fixup in decoder Philippe Mathieu-Daudé
2025-03-06 15:47 ` [PULL 31/54] target/openrisc: Call cpu_openrisc_clock_init() in cpu_realize() Philippe Mathieu-Daudé
2025-03-06 15:47 ` [PULL 32/54] target/hexagon: Ensure not being build on system emulation Philippe Mathieu-Daudé
2025-03-06 15:47 ` [PULL 33/54] target/rx: Ensure not being build on user emulation Philippe Mathieu-Daudé
2025-03-06 15:47 ` [PULL 34/54] target/tricore: " Philippe Mathieu-Daudé
2025-03-06 15:47 ` [PULL 35/54] target/mips: Fix possible MSA int overflow Philippe Mathieu-Daudé
2025-03-06 15:47 ` [PULL 36/54] target: Set disassemble_info::endian value for little-endian targets Philippe Mathieu-Daudé
2025-03-06 15:47 ` [PULL 37/54] target: Set disassemble_info::endian value for big-endian targets Philippe Mathieu-Daudé
2025-03-06 15:47 ` [PULL 38/54] target/arm: Set disassemble_info::endian value in disas_set_info() Philippe Mathieu-Daudé
2025-03-06 15:47 ` [PULL 39/54] target/microblaze: Set disassemble_info::endian value in disas_set_info Philippe Mathieu-Daudé
2025-03-06 15:47 ` [PULL 40/54] target/mips: Set disassemble_info::endian value in disas_set_info() Philippe Mathieu-Daudé
2025-03-06 15:47 ` [PULL 41/54] target/ppc: " Philippe Mathieu-Daudé
2025-03-06 15:47 ` [PULL 42/54] target/riscv: " Philippe Mathieu-Daudé
2025-03-06 15:47 ` [PULL 43/54] target/sh4: " Philippe Mathieu-Daudé
2025-03-06 15:47 ` [PULL 44/54] target/xtensa: " Philippe Mathieu-Daudé
2025-03-06 15:47 ` [PULL 45/54] disas: Remove target_words_bigendian() call in initialize_debug_target() Philippe Mathieu-Daudé
2025-03-06 15:47 ` [PULL 46/54] target/i386: Constify X86CPUModel uses Philippe Mathieu-Daudé
2025-03-06 15:47 ` [PULL 47/54] target/sparc: Constify SPARCCPUClass::cpu_def Philippe Mathieu-Daudé
2025-03-06 15:47 ` [PULL 48/54] target/xtensa: Finalize config in xtensa_register_core() Philippe Mathieu-Daudé
2025-03-06 15:47 ` [PULL 49/54] target/riscv: Declare RISCVCPUClass::misa_mxl_max as RISCVMXL Philippe Mathieu-Daudé
2025-03-06 15:47 ` [PULL 50/54] target/riscv: Convert misa_mxl_max using GLib macros Philippe Mathieu-Daudé
2025-03-06 15:47 ` [PULL 51/54] target/alpha: Do not mix exception flags and FPCR bits Philippe Mathieu-Daudé
2025-03-06 15:47 ` [PULL 52/54] target/i386: Mark WHPX APIC region as little-endian Philippe Mathieu-Daudé
2025-03-06 15:47 ` [PULL 53/54] system: Open-code qemu_init_arch_modules() using target_name() Philippe Mathieu-Daudé
2025-03-06 15:47 ` [PULL 54/54] include: Poison TARGET_PHYS_ADDR_SPACE_BITS definition Philippe Mathieu-Daudé
2025-03-07 7:18 ` [PULL 00/54] Accelerators & CPU patches Stefan Hajnoczi
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