From: "Philippe Mathieu-Daudé" <philmd@linaro.org>
To: qemu-devel@nongnu.org
Subject: [PULL 18/54] accel/tcg: Move cpu_memory_rw_debug() user implementation to user-exec.c
Date: Thu, 6 Mar 2025 16:47:00 +0100 [thread overview]
Message-ID: <20250306154737.70886-19-philmd@linaro.org> (raw)
In-Reply-To: <20250306154737.70886-1-philmd@linaro.org>
cpu_memory_rw_debug() system implementation is defined in
system/physmem.c. Move the user one to accel/tcg/user-exec.c
to simplify cpu-target.c maintenance.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20250217130610.18313-6-philmd@linaro.org>
---
accel/tcg/user-exec.c | 80 ++++++++++++++++++++++++++++++++++++++
cpu-target.c | 90 +------------------------------------------
2 files changed, 82 insertions(+), 88 deletions(-)
diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c
index 9d53c9440ea..2322181b151 100644
--- a/accel/tcg/user-exec.c
+++ b/accel/tcg/user-exec.c
@@ -19,6 +19,7 @@
#include "qemu/osdep.h"
#include "accel/tcg/cpu-ops.h"
#include "disas/disas.h"
+#include "exec/vaddr.h"
#include "exec/exec-all.h"
#include "tcg/tcg.h"
#include "qemu/bitops.h"
@@ -971,6 +972,85 @@ static void *cpu_mmu_lookup(CPUState *cpu, vaddr addr,
return ret;
}
+/* physical memory access (slow version, mainly for debug) */
+int cpu_memory_rw_debug(CPUState *cpu, vaddr addr,
+ void *ptr, size_t len, bool is_write)
+{
+ int flags;
+ vaddr l, page;
+ uint8_t *buf = ptr;
+ ssize_t written;
+ int ret = -1;
+ int fd = -1;
+
+ mmap_lock();
+
+ while (len > 0) {
+ page = addr & TARGET_PAGE_MASK;
+ l = (page + TARGET_PAGE_SIZE) - addr;
+ if (l > len) {
+ l = len;
+ }
+ flags = page_get_flags(page);
+ if (!(flags & PAGE_VALID)) {
+ goto out_close;
+ }
+ if (is_write) {
+ if (flags & PAGE_WRITE) {
+ memcpy(g2h(cpu, addr), buf, l);
+ } else {
+ /* Bypass the host page protection using ptrace. */
+ if (fd == -1) {
+ fd = open("/proc/self/mem", O_WRONLY);
+ if (fd == -1) {
+ goto out;
+ }
+ }
+ /*
+ * If there is a TranslationBlock and we weren't bypassing the
+ * host page protection, the memcpy() above would SEGV,
+ * ultimately leading to page_unprotect(). So invalidate the
+ * translations manually. Both invalidation and pwrite() must
+ * be under mmap_lock() in order to prevent the creation of
+ * another TranslationBlock in between.
+ */
+ tb_invalidate_phys_range(addr, addr + l - 1);
+ written = pwrite(fd, buf, l,
+ (off_t)(uintptr_t)g2h_untagged(addr));
+ if (written != l) {
+ goto out_close;
+ }
+ }
+ } else if (flags & PAGE_READ) {
+ memcpy(buf, g2h(cpu, addr), l);
+ } else {
+ /* Bypass the host page protection using ptrace. */
+ if (fd == -1) {
+ fd = open("/proc/self/mem", O_RDONLY);
+ if (fd == -1) {
+ goto out;
+ }
+ }
+ if (pread(fd, buf, l,
+ (off_t)(uintptr_t)g2h_untagged(addr)) != l) {
+ goto out_close;
+ }
+ }
+ len -= l;
+ buf += l;
+ addr += l;
+ }
+ ret = 0;
+out_close:
+ if (fd != -1) {
+ close(fd);
+ }
+out:
+ mmap_unlock();
+
+ return ret;
+}
+
#include "ldst_atomicity.c.inc"
static uint8_t do_ld1_mmu(CPUState *cpu, vaddr addr, MemOpIdx oi,
diff --git a/cpu-target.c b/cpu-target.c
index 3892ce12229..83688f1d508 100644
--- a/cpu-target.c
+++ b/cpu-target.c
@@ -19,18 +19,12 @@
#include "qemu/osdep.h"
#include "qapi/error.h"
-
-#include "exec/target_page.h"
-#include "exec/page-protection.h"
#include "hw/qdev-core.h"
#include "hw/qdev-properties.h"
#include "qemu/error-report.h"
#include "qemu/qemu-print.h"
#include "migration/vmstate.h"
-#ifdef CONFIG_USER_ONLY
-#include "qemu.h"
-#include "user/page-protection.h"
-#else
+#ifndef CONFIG_USER_ONLY
#include "hw/core/sysemu-cpu-ops.h"
#include "exec/address-spaces.h"
#include "exec/memory.h"
@@ -43,11 +37,11 @@
#include "exec/cpu-common.h"
#include "exec/exec-all.h"
#include "exec/tb-flush.h"
-#include "exec/translation-block.h"
#include "exec/log.h"
#include "accel/accel-cpu-target.h"
#include "trace/trace-root.h"
#include "qemu/accel.h"
+#include "hw/core/cpu.h"
#ifndef CONFIG_USER_ONLY
static int cpu_common_post_load(void *opaque, int version_id)
@@ -367,86 +361,6 @@ void cpu_abort(CPUState *cpu, const char *fmt, ...)
abort();
}
-/* physical memory access (slow version, mainly for debug) */
-#if defined(CONFIG_USER_ONLY)
-int cpu_memory_rw_debug(CPUState *cpu, vaddr addr,
- void *ptr, size_t len, bool is_write)
-{
- int flags;
- vaddr l, page;
- uint8_t *buf = ptr;
- ssize_t written;
- int ret = -1;
- int fd = -1;
-
- mmap_lock();
-
- while (len > 0) {
- page = addr & TARGET_PAGE_MASK;
- l = (page + TARGET_PAGE_SIZE) - addr;
- if (l > len)
- l = len;
- flags = page_get_flags(page);
- if (!(flags & PAGE_VALID)) {
- goto out_close;
- }
- if (is_write) {
- if (flags & PAGE_WRITE) {
- memcpy(g2h(cpu, addr), buf, l);
- } else {
- /* Bypass the host page protection using ptrace. */
- if (fd == -1) {
- fd = open("/proc/self/mem", O_WRONLY);
- if (fd == -1) {
- goto out;
- }
- }
- /*
- * If there is a TranslationBlock and we weren't bypassing the
- * host page protection, the memcpy() above would SEGV,
- * ultimately leading to page_unprotect(). So invalidate the
- * translations manually. Both invalidation and pwrite() must
- * be under mmap_lock() in order to prevent the creation of
- * another TranslationBlock in between.
- */
- tb_invalidate_phys_range(addr, addr + l - 1);
- written = pwrite(fd, buf, l,
- (off_t)(uintptr_t)g2h_untagged(addr));
- if (written != l) {
- goto out_close;
- }
- }
- } else if (flags & PAGE_READ) {
- memcpy(buf, g2h(cpu, addr), l);
- } else {
- /* Bypass the host page protection using ptrace. */
- if (fd == -1) {
- fd = open("/proc/self/mem", O_RDONLY);
- if (fd == -1) {
- goto out;
- }
- }
- if (pread(fd, buf, l,
- (off_t)(uintptr_t)g2h_untagged(addr)) != l) {
- goto out_close;
- }
- }
- len -= l;
- buf += l;
- addr += l;
- }
- ret = 0;
-out_close:
- if (fd != -1) {
- close(fd);
- }
-out:
- mmap_unlock();
-
- return ret;
-}
-#endif
-
bool target_words_bigendian(void)
{
return TARGET_BIG_ENDIAN;
--
2.47.1
next prev parent reply other threads:[~2025-03-06 15:56 UTC|newest]
Thread overview: 56+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-03-06 15:46 [PULL 00/54] Accelerators & CPU patches Philippe Mathieu-Daudé
2025-03-06 15:46 ` [PULL 01/54] qemu/compiler: Absorb 'clang-tsa.h' Philippe Mathieu-Daudé
2025-03-06 15:46 ` [PULL 02/54] gdbstub: Clarify no more than @gdb_num_core_regs can be accessed Philippe Mathieu-Daudé
2025-03-06 15:46 ` [PULL 03/54] gdbstub: Check for TCG before calling tb_flush() Philippe Mathieu-Daudé
2025-03-06 15:46 ` [PULL 04/54] cpus: Cache CPUClass early in instance_init() handler Philippe Mathieu-Daudé
2025-03-06 15:46 ` [PULL 05/54] cpus: Keep default fields initialization in cpu_common_initfn() Philippe Mathieu-Daudé
2025-03-06 15:46 ` [PULL 06/54] accel/accel: Make TYPE_ACCEL abstract Philippe Mathieu-Daudé
2025-03-06 15:46 ` [PULL 07/54] accel/tcg: Remove pointless initialization of cflags_next_tb Philippe Mathieu-Daudé
2025-03-06 15:46 ` [PULL 08/54] accel/tcg: Build tcg_flags helpers as common code Philippe Mathieu-Daudé
2025-03-06 15:46 ` [PULL 09/54] accel/tcg: Restrict tlb_init() / destroy() to TCG Philippe Mathieu-Daudé
2025-03-06 15:46 ` [PULL 10/54] accel/tcg: Restrict 'icount_align_option' global " Philippe Mathieu-Daudé
2025-03-06 15:46 ` [PULL 11/54] accel/tcg: Rename 'hw/core/tcg-cpu-ops.h' -> 'accel/tcg/cpu-ops.h' Philippe Mathieu-Daudé
2025-03-06 15:46 ` [PULL 12/54] accel: Rename 'hw/core/accel-cpu.h' -> 'accel/accel-cpu-target.h' Philippe Mathieu-Daudé
2025-03-06 15:46 ` [PULL 13/54] accel: Forward-declare AccelOpsClass in 'qemu/typedefs.h' Philippe Mathieu-Daudé
2025-03-06 15:46 ` [PULL 14/54] accel/accel-cpu-target.h: Include missing 'cpu.h' header Philippe Mathieu-Daudé
2025-03-06 15:46 ` [PULL 15/54] accel/tcg: Include missing bswap headers in user-exec.c Philippe Mathieu-Daudé
2025-03-06 15:46 ` [PULL 16/54] accel/tcg: Take mmap lock in the whole cpu_memory_rw_debug() function Philippe Mathieu-Daudé
2025-03-06 15:46 ` [PULL 17/54] accel/tcg: Avoid using lock_user() in cpu_memory_rw_debug() Philippe Mathieu-Daudé
2025-03-06 15:47 ` Philippe Mathieu-Daudé [this message]
2025-03-06 15:47 ` [PULL 19/54] accel/kvm: Remove unused 'system/cpus.h' header in kvm-cpus.h Philippe Mathieu-Daudé
2025-03-06 15:47 ` [PULL 20/54] cpus: Fix style in cpu-target.c Philippe Mathieu-Daudé
2025-03-06 15:47 ` [PULL 21/54] cpus: Restrict cpu_common_post_load() code to TCG Philippe Mathieu-Daudé
2025-03-06 15:47 ` [PULL 22/54] cpus: Have cpu_class_init_props() per user / system emulation Philippe Mathieu-Daudé
2025-03-06 15:47 ` [PULL 23/54] cpus: Have cpu_exec_initfn() " Philippe Mathieu-Daudé
2025-03-06 15:47 ` [PULL 24/54] cpus: Restrict cpu_get_memory_mapping() to " Philippe Mathieu-Daudé
2025-03-06 15:47 ` [PULL 25/54] hw/core/generic-loader: Do not open-code cpu_set_pc() Philippe Mathieu-Daudé
2025-03-06 15:47 ` [PULL 26/54] target/microblaze: Explode MO_TExx -> MO_TE | MO_xx Philippe Mathieu-Daudé
2025-03-06 15:47 ` [PULL 27/54] target/microblaze: Set MO_TE once in do_load() / do_store() Philippe Mathieu-Daudé
2025-03-06 15:47 ` [PULL 28/54] target/microblaze: Introduce mo_endian() helper Philippe Mathieu-Daudé
2025-03-06 15:47 ` [PULL 29/54] target/microblaze: Consider endianness while translating code Philippe Mathieu-Daudé
2025-03-06 15:47 ` [PULL 30/54] target/i386/hvf: Variable type fixup in decoder Philippe Mathieu-Daudé
2025-03-06 15:47 ` [PULL 31/54] target/openrisc: Call cpu_openrisc_clock_init() in cpu_realize() Philippe Mathieu-Daudé
2025-03-06 15:47 ` [PULL 32/54] target/hexagon: Ensure not being build on system emulation Philippe Mathieu-Daudé
2025-03-06 15:47 ` [PULL 33/54] target/rx: Ensure not being build on user emulation Philippe Mathieu-Daudé
2025-03-06 15:47 ` [PULL 34/54] target/tricore: " Philippe Mathieu-Daudé
2025-03-06 15:47 ` [PULL 35/54] target/mips: Fix possible MSA int overflow Philippe Mathieu-Daudé
2025-03-06 15:47 ` [PULL 36/54] target: Set disassemble_info::endian value for little-endian targets Philippe Mathieu-Daudé
2025-03-06 15:47 ` [PULL 37/54] target: Set disassemble_info::endian value for big-endian targets Philippe Mathieu-Daudé
2025-03-06 15:47 ` [PULL 38/54] target/arm: Set disassemble_info::endian value in disas_set_info() Philippe Mathieu-Daudé
2025-03-06 15:47 ` [PULL 39/54] target/microblaze: Set disassemble_info::endian value in disas_set_info Philippe Mathieu-Daudé
2025-03-06 15:47 ` [PULL 40/54] target/mips: Set disassemble_info::endian value in disas_set_info() Philippe Mathieu-Daudé
2025-03-06 15:47 ` [PULL 41/54] target/ppc: " Philippe Mathieu-Daudé
2025-03-06 15:47 ` [PULL 42/54] target/riscv: " Philippe Mathieu-Daudé
2025-03-06 15:47 ` [PULL 43/54] target/sh4: " Philippe Mathieu-Daudé
2025-03-06 15:47 ` [PULL 44/54] target/xtensa: " Philippe Mathieu-Daudé
2025-03-06 15:47 ` [PULL 45/54] disas: Remove target_words_bigendian() call in initialize_debug_target() Philippe Mathieu-Daudé
2025-03-06 15:47 ` [PULL 46/54] target/i386: Constify X86CPUModel uses Philippe Mathieu-Daudé
2025-03-06 15:47 ` [PULL 47/54] target/sparc: Constify SPARCCPUClass::cpu_def Philippe Mathieu-Daudé
2025-03-06 15:47 ` [PULL 48/54] target/xtensa: Finalize config in xtensa_register_core() Philippe Mathieu-Daudé
2025-03-06 15:47 ` [PULL 49/54] target/riscv: Declare RISCVCPUClass::misa_mxl_max as RISCVMXL Philippe Mathieu-Daudé
2025-03-06 15:47 ` [PULL 50/54] target/riscv: Convert misa_mxl_max using GLib macros Philippe Mathieu-Daudé
2025-03-06 15:47 ` [PULL 51/54] target/alpha: Do not mix exception flags and FPCR bits Philippe Mathieu-Daudé
2025-03-06 15:47 ` [PULL 52/54] target/i386: Mark WHPX APIC region as little-endian Philippe Mathieu-Daudé
2025-03-06 15:47 ` [PULL 53/54] system: Open-code qemu_init_arch_modules() using target_name() Philippe Mathieu-Daudé
2025-03-06 15:47 ` [PULL 54/54] include: Poison TARGET_PHYS_ADDR_SPACE_BITS definition Philippe Mathieu-Daudé
2025-03-07 7:18 ` [PULL 00/54] Accelerators & CPU patches Stefan Hajnoczi
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