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From: "Philippe Mathieu-Daudé" <philmd@linaro.org>
To: qemu-devel@nongnu.org
Subject: [PULL 29/54] target/microblaze: Consider endianness while translating code
Date: Thu,  6 Mar 2025 16:47:11 +0100	[thread overview]
Message-ID: <20250306154737.70886-30-philmd@linaro.org> (raw)
In-Reply-To: <20250306154737.70886-1-philmd@linaro.org>

Consider the CPU ENDI bit, swap instructions when the CPU
endianness doesn't match the binary one.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20241105130431.22564-17-philmd@linaro.org>
---
 target/microblaze/cpu.h       | 7 +++++++
 target/microblaze/translate.c | 5 +++--
 2 files changed, 10 insertions(+), 2 deletions(-)

diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h
index f6879eee352..e44ddd53078 100644
--- a/target/microblaze/cpu.h
+++ b/target/microblaze/cpu.h
@@ -414,6 +414,13 @@ void mb_translate_code(CPUState *cs, TranslationBlock *tb,
 /* Ensure there is no overlap between the two masks. */
 QEMU_BUILD_BUG_ON(MSR_TB_MASK & IFLAGS_TB_MASK);
 
+static inline bool mb_cpu_is_big_endian(CPUState *cs)
+{
+    MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs);
+
+    return !cpu->cfg.endi;
+}
+
 static inline void cpu_get_tb_cpu_state(CPUMBState *env, vaddr *pc,
                                         uint64_t *cs_base, uint32_t *flags)
 {
diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c
index b5389d65b2e..b54e5ac4b2f 100644
--- a/target/microblaze/translate.c
+++ b/target/microblaze/translate.c
@@ -710,7 +710,7 @@ static void record_unaligned_ess(DisasContext *dc, int rd,
 
 static inline MemOp mo_endian(DisasContext *dc)
 {
-    return MO_TE;
+    return dc->cfg->endi ? MO_LE : MO_BE;
 }
 
 static bool do_load(DisasContext *dc, int rd, TCGv addr, MemOp mop,
@@ -1647,7 +1647,8 @@ static void mb_tr_translate_insn(DisasContextBase *dcb, CPUState *cs)
 
     dc->tb_flags_to_set = 0;
 
-    ir = translator_ldl(cpu_env(cs), &dc->base, dc->base.pc_next);
+    ir = translator_ldl_swap(cpu_env(cs), &dc->base, dc->base.pc_next,
+                             mb_cpu_is_big_endian(cs) != TARGET_BIG_ENDIAN);
     if (!decode(dc, ir)) {
         trap_illegal(dc, true);
     }
-- 
2.47.1



  parent reply	other threads:[~2025-03-06 15:58 UTC|newest]

Thread overview: 56+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-03-06 15:46 [PULL 00/54] Accelerators & CPU patches Philippe Mathieu-Daudé
2025-03-06 15:46 ` [PULL 01/54] qemu/compiler: Absorb 'clang-tsa.h' Philippe Mathieu-Daudé
2025-03-06 15:46 ` [PULL 02/54] gdbstub: Clarify no more than @gdb_num_core_regs can be accessed Philippe Mathieu-Daudé
2025-03-06 15:46 ` [PULL 03/54] gdbstub: Check for TCG before calling tb_flush() Philippe Mathieu-Daudé
2025-03-06 15:46 ` [PULL 04/54] cpus: Cache CPUClass early in instance_init() handler Philippe Mathieu-Daudé
2025-03-06 15:46 ` [PULL 05/54] cpus: Keep default fields initialization in cpu_common_initfn() Philippe Mathieu-Daudé
2025-03-06 15:46 ` [PULL 06/54] accel/accel: Make TYPE_ACCEL abstract Philippe Mathieu-Daudé
2025-03-06 15:46 ` [PULL 07/54] accel/tcg: Remove pointless initialization of cflags_next_tb Philippe Mathieu-Daudé
2025-03-06 15:46 ` [PULL 08/54] accel/tcg: Build tcg_flags helpers as common code Philippe Mathieu-Daudé
2025-03-06 15:46 ` [PULL 09/54] accel/tcg: Restrict tlb_init() / destroy() to TCG Philippe Mathieu-Daudé
2025-03-06 15:46 ` [PULL 10/54] accel/tcg: Restrict 'icount_align_option' global " Philippe Mathieu-Daudé
2025-03-06 15:46 ` [PULL 11/54] accel/tcg: Rename 'hw/core/tcg-cpu-ops.h' -> 'accel/tcg/cpu-ops.h' Philippe Mathieu-Daudé
2025-03-06 15:46 ` [PULL 12/54] accel: Rename 'hw/core/accel-cpu.h' -> 'accel/accel-cpu-target.h' Philippe Mathieu-Daudé
2025-03-06 15:46 ` [PULL 13/54] accel: Forward-declare AccelOpsClass in 'qemu/typedefs.h' Philippe Mathieu-Daudé
2025-03-06 15:46 ` [PULL 14/54] accel/accel-cpu-target.h: Include missing 'cpu.h' header Philippe Mathieu-Daudé
2025-03-06 15:46 ` [PULL 15/54] accel/tcg: Include missing bswap headers in user-exec.c Philippe Mathieu-Daudé
2025-03-06 15:46 ` [PULL 16/54] accel/tcg: Take mmap lock in the whole cpu_memory_rw_debug() function Philippe Mathieu-Daudé
2025-03-06 15:46 ` [PULL 17/54] accel/tcg: Avoid using lock_user() in cpu_memory_rw_debug() Philippe Mathieu-Daudé
2025-03-06 15:47 ` [PULL 18/54] accel/tcg: Move cpu_memory_rw_debug() user implementation to user-exec.c Philippe Mathieu-Daudé
2025-03-06 15:47 ` [PULL 19/54] accel/kvm: Remove unused 'system/cpus.h' header in kvm-cpus.h Philippe Mathieu-Daudé
2025-03-06 15:47 ` [PULL 20/54] cpus: Fix style in cpu-target.c Philippe Mathieu-Daudé
2025-03-06 15:47 ` [PULL 21/54] cpus: Restrict cpu_common_post_load() code to TCG Philippe Mathieu-Daudé
2025-03-06 15:47 ` [PULL 22/54] cpus: Have cpu_class_init_props() per user / system emulation Philippe Mathieu-Daudé
2025-03-06 15:47 ` [PULL 23/54] cpus: Have cpu_exec_initfn() " Philippe Mathieu-Daudé
2025-03-06 15:47 ` [PULL 24/54] cpus: Restrict cpu_get_memory_mapping() to " Philippe Mathieu-Daudé
2025-03-06 15:47 ` [PULL 25/54] hw/core/generic-loader: Do not open-code cpu_set_pc() Philippe Mathieu-Daudé
2025-03-06 15:47 ` [PULL 26/54] target/microblaze: Explode MO_TExx -> MO_TE | MO_xx Philippe Mathieu-Daudé
2025-03-06 15:47 ` [PULL 27/54] target/microblaze: Set MO_TE once in do_load() / do_store() Philippe Mathieu-Daudé
2025-03-06 15:47 ` [PULL 28/54] target/microblaze: Introduce mo_endian() helper Philippe Mathieu-Daudé
2025-03-06 15:47 ` Philippe Mathieu-Daudé [this message]
2025-03-06 15:47 ` [PULL 30/54] target/i386/hvf: Variable type fixup in decoder Philippe Mathieu-Daudé
2025-03-06 15:47 ` [PULL 31/54] target/openrisc: Call cpu_openrisc_clock_init() in cpu_realize() Philippe Mathieu-Daudé
2025-03-06 15:47 ` [PULL 32/54] target/hexagon: Ensure not being build on system emulation Philippe Mathieu-Daudé
2025-03-06 15:47 ` [PULL 33/54] target/rx: Ensure not being build on user emulation Philippe Mathieu-Daudé
2025-03-06 15:47 ` [PULL 34/54] target/tricore: " Philippe Mathieu-Daudé
2025-03-06 15:47 ` [PULL 35/54] target/mips: Fix possible MSA int overflow Philippe Mathieu-Daudé
2025-03-06 15:47 ` [PULL 36/54] target: Set disassemble_info::endian value for little-endian targets Philippe Mathieu-Daudé
2025-03-06 15:47 ` [PULL 37/54] target: Set disassemble_info::endian value for big-endian targets Philippe Mathieu-Daudé
2025-03-06 15:47 ` [PULL 38/54] target/arm: Set disassemble_info::endian value in disas_set_info() Philippe Mathieu-Daudé
2025-03-06 15:47 ` [PULL 39/54] target/microblaze: Set disassemble_info::endian value in disas_set_info Philippe Mathieu-Daudé
2025-03-06 15:47 ` [PULL 40/54] target/mips: Set disassemble_info::endian value in disas_set_info() Philippe Mathieu-Daudé
2025-03-06 15:47 ` [PULL 41/54] target/ppc: " Philippe Mathieu-Daudé
2025-03-06 15:47 ` [PULL 42/54] target/riscv: " Philippe Mathieu-Daudé
2025-03-06 15:47 ` [PULL 43/54] target/sh4: " Philippe Mathieu-Daudé
2025-03-06 15:47 ` [PULL 44/54] target/xtensa: " Philippe Mathieu-Daudé
2025-03-06 15:47 ` [PULL 45/54] disas: Remove target_words_bigendian() call in initialize_debug_target() Philippe Mathieu-Daudé
2025-03-06 15:47 ` [PULL 46/54] target/i386: Constify X86CPUModel uses Philippe Mathieu-Daudé
2025-03-06 15:47 ` [PULL 47/54] target/sparc: Constify SPARCCPUClass::cpu_def Philippe Mathieu-Daudé
2025-03-06 15:47 ` [PULL 48/54] target/xtensa: Finalize config in xtensa_register_core() Philippe Mathieu-Daudé
2025-03-06 15:47 ` [PULL 49/54] target/riscv: Declare RISCVCPUClass::misa_mxl_max as RISCVMXL Philippe Mathieu-Daudé
2025-03-06 15:47 ` [PULL 50/54] target/riscv: Convert misa_mxl_max using GLib macros Philippe Mathieu-Daudé
2025-03-06 15:47 ` [PULL 51/54] target/alpha: Do not mix exception flags and FPCR bits Philippe Mathieu-Daudé
2025-03-06 15:47 ` [PULL 52/54] target/i386: Mark WHPX APIC region as little-endian Philippe Mathieu-Daudé
2025-03-06 15:47 ` [PULL 53/54] system: Open-code qemu_init_arch_modules() using target_name() Philippe Mathieu-Daudé
2025-03-06 15:47 ` [PULL 54/54] include: Poison TARGET_PHYS_ADDR_SPACE_BITS definition Philippe Mathieu-Daudé
2025-03-07  7:18 ` [PULL 00/54] Accelerators & CPU patches Stefan Hajnoczi

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