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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-43bdd94913fsm23999905e9.37.2025.03.06.08.39.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 06 Mar 2025 08:39:26 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: From ce9a42483c23c32cee233f648101a160b6604b45 Mon Sep 17 00:00:00 2001 Date: Thu, 6 Mar 2025 16:39:14 +0000 Message-ID: <20250306163925.2940297-1-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::32d; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Newer Arm CPUs need not implement AArch32 at all exception levels (and Armv9 forbids implementing AArch32 at any EL except EL0). All our current CPU models implement both AArch32 and AArch64 at every exception levels, so we currently get away with failing to enforce that the guest isn't trying to do an exception return to AArch32 when the target EL doesn't support AArch32. This patchset adds the missing checks: * SCR_EL3.RW has an effective value of 1 if EL2 is AArch64-only * HCR_EL2.RW is RAO/WI if EL1 is AArch64-only * return to AArch32 when no EL supports AArch32 is an illegal exception return To do this it needs to start off with some cleanup. This is because we need to add a cpu_isar_feature() check to arm_el_is_aa64(), but we don't want to include cpu-features.h in cpu.h. arm_el_is_aa64() is really an internal part of the CPU implementation, so we can move it to internals.h; this means also moving some other functions in cpu.h that are defined as inline functions and which call arm_el_is_aa64(). Removing some unused macros from linux-user allows us to avoid having linux-user include internals.h. (No doubt there are other functions that could be moved out of cpu.h, but I stuck to only the ones that I actually needed to move.) thanks -- PMM Peter Maydell (10): target/arm: Move A32_BANKED_REG_{GET,SET} macros to cpregs.h target/arm: Un-inline access_secure_reg() linux-user/aarch64: Remove unused get/put_user macros linux-user/arm: Remove unused get_put_user macros target/arm: Move arm_cpu_data_is_big_endian() etc to internals.h target/arm: Move arm_current_el() and arm_el_is_aa64() to internals.h target/arm: SCR_EL3.RW should be treated as 1 if EL2 doesn't support AArch32 target/arm: HCR_EL2.RW should be RAO/WI if EL1 doesn't support AArch32 target/arm: Add cpu local variable to exception_return helper target/arm: Forbid return to AArch32 when CPU is AArch64-only target/arm/cpregs.h | 28 +++++++ target/arm/cpu.h | 153 +--------------------------------- target/arm/internals.h | 133 +++++++++++++++++++++++++++++ hw/intc/arm_gicv3_cpuif.c | 1 + linux-user/aarch64/cpu_loop.c | 48 ----------- linux-user/arm/cpu_loop.c | 43 +--------- target/arm/arch_dump.c | 1 + target/arm/helper.c | 16 +++- target/arm/tcg/helper-a64.c | 12 ++- target/arm/tcg/hflags.c | 9 ++ 10 files changed, 202 insertions(+), 242 deletions(-) -- 2.43.0