From: Jamin Lin via <qemu-devel@nongnu.org>
To: "Cédric Le Goater" <clg@kaod.org>,
"Peter Maydell" <peter.maydell@linaro.org>,
"Steven Lee" <steven_lee@aspeedtech.com>,
"Troy Lee" <leetroy@gmail.com>,
"Andrew Jeffery" <andrew@codeconstruct.com.au>,
"Joel Stanley" <joel@jms.id.au>,
"open list:All patches CC here" <qemu-devel@nongnu.org>,
"open list:ASPEED BMCs" <qemu-arm@nongnu.org>
Cc: jamin_lin@aspeedtech.com, troy_lee@aspeedtech.com,
"Cédric Le Goater" <clg@redhat.com>
Subject: [PATCH v6 20/29] hw/arm/aspeed_ast27x0: Define an Array of AspeedINTCState with Two Instances
Date: Fri, 7 Mar 2025 11:59:29 +0800 [thread overview]
Message-ID: <20250307035945.3698802-21-jamin_lin@aspeedtech.com> (raw)
In-Reply-To: <20250307035945.3698802-1-jamin_lin@aspeedtech.com>
Updated Aspeed27x0SoCState to include an intc[2] array instead of a single
AspeedINTCState instance. Modified aspeed_soc_ast2700_get_irq and
aspeed_soc_ast2700_get_irq_index to correctly reference the corresponding
interrupt controller instance and OR gate index.
Currently, only GIC 192 to 201 are supported, and their source interrupts are
from INTCIO and connected to INTC at input pin 0 and output pins 0 to 9 for
GIC 192-201.
To support both AST2700 A1 and A0, INTC input pins 1 to 9 and output pins
10 to 18 remain to support GIC 128-136, which source interrupts from INTC.
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
Reviewed-by: Cédric Le Goater <clg@redhat.com>
---
include/hw/arm/aspeed_soc.h | 2 +-
hw/arm/aspeed_ast27x0.c | 58 +++++++++++++++++++++++++------------
2 files changed, 40 insertions(+), 20 deletions(-)
diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h
index 689f52dae8..1ac99269ae 100644
--- a/include/hw/arm/aspeed_soc.h
+++ b/include/hw/arm/aspeed_soc.h
@@ -128,7 +128,7 @@ struct Aspeed27x0SoCState {
AspeedSoCState parent;
ARMCPU cpu[ASPEED_CPUS_NUM];
- AspeedINTCState intc;
+ AspeedINTCState intc[2];
GICv3State gic;
MemoryRegion dram_empty;
};
diff --git a/hw/arm/aspeed_ast27x0.c b/hw/arm/aspeed_ast27x0.c
index 343fe87921..90545215e2 100644
--- a/hw/arm/aspeed_ast27x0.c
+++ b/hw/arm/aspeed_ast27x0.c
@@ -178,32 +178,48 @@ static const int ast2700_gic133_gic197_intcmap[] = {
/* GICINT 192 ~ 201 */
struct gic_intc_irq_info {
int irq;
+ int intc_idx;
+ int orgate_idx;
const int *ptr;
};
static const struct gic_intc_irq_info ast2700_gic_intcmap[] = {
- {128, ast2700_gic128_gic192_intcmap},
- {129, NULL},
- {130, ast2700_gic130_gic194_intcmap},
- {131, ast2700_gic131_gic195_intcmap},
- {132, ast2700_gic132_gic196_intcmap},
- {133, ast2700_gic133_gic197_intcmap},
- {134, NULL},
- {135, NULL},
- {136, NULL},
+ {192, 1, 0, ast2700_gic128_gic192_intcmap},
+ {193, 1, 1, NULL},
+ {194, 1, 2, ast2700_gic130_gic194_intcmap},
+ {195, 1, 3, ast2700_gic131_gic195_intcmap},
+ {196, 1, 4, ast2700_gic132_gic196_intcmap},
+ {197, 1, 5, ast2700_gic133_gic197_intcmap},
+ {198, 1, 6, NULL},
+ {199, 1, 7, NULL},
+ {200, 1, 8, NULL},
+ {201, 1, 9, NULL},
+ {128, 0, 1, ast2700_gic128_gic192_intcmap},
+ {129, 0, 2, NULL},
+ {130, 0, 3, ast2700_gic130_gic194_intcmap},
+ {131, 0, 4, ast2700_gic131_gic195_intcmap},
+ {132, 0, 5, ast2700_gic132_gic196_intcmap},
+ {133, 0, 6, ast2700_gic133_gic197_intcmap},
+ {134, 0, 7, NULL},
+ {135, 0, 8, NULL},
+ {136, 0, 9, NULL},
};
static qemu_irq aspeed_soc_ast2700_get_irq(AspeedSoCState *s, int dev)
{
Aspeed27x0SoCState *a = ASPEED27X0_SOC(s);
AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
+ int or_idx;
+ int idx;
int i;
for (i = 0; i < ARRAY_SIZE(ast2700_gic_intcmap); i++) {
if (sc->irqmap[dev] == ast2700_gic_intcmap[i].irq) {
assert(ast2700_gic_intcmap[i].ptr);
- return qdev_get_gpio_in(DEVICE(&a->intc.orgates[i]),
- ast2700_gic_intcmap[i].ptr[dev]);
+ or_idx = ast2700_gic_intcmap[i].orgate_idx;
+ idx = ast2700_gic_intcmap[i].intc_idx;
+ return qdev_get_gpio_in(DEVICE(&a->intc[idx].orgates[or_idx]),
+ ast2700_gic_intcmap[i].ptr[dev]);
}
}
@@ -215,12 +231,16 @@ static qemu_irq aspeed_soc_ast2700_get_irq_index(AspeedSoCState *s, int dev,
{
Aspeed27x0SoCState *a = ASPEED27X0_SOC(s);
AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
+ int or_idx;
+ int idx;
int i;
for (i = 0; i < ARRAY_SIZE(ast2700_gic_intcmap); i++) {
if (sc->irqmap[dev] == ast2700_gic_intcmap[i].irq) {
assert(ast2700_gic_intcmap[i].ptr);
- return qdev_get_gpio_in(DEVICE(&a->intc.orgates[i]),
+ or_idx = ast2700_gic_intcmap[i].orgate_idx;
+ idx = ast2700_gic_intcmap[i].intc_idx;
+ return qdev_get_gpio_in(DEVICE(&a->intc[idx].orgates[or_idx]),
ast2700_gic_intcmap[i].ptr[dev] + index);
}
}
@@ -390,7 +410,7 @@ static void aspeed_soc_ast2700_init(Object *obj)
object_initialize_child(obj, "sli", &s->sli, TYPE_ASPEED_2700_SLI);
object_initialize_child(obj, "sliio", &s->sliio, TYPE_ASPEED_2700_SLIIO);
- object_initialize_child(obj, "intc", &a->intc, TYPE_ASPEED_2700_INTC);
+ object_initialize_child(obj, "intc", &a->intc[0], TYPE_ASPEED_2700_INTC);
snprintf(typename, sizeof(typename), "aspeed.adc-%s", socname);
object_initialize_child(obj, "adc", &s->adc, typename);
@@ -502,7 +522,7 @@ static void aspeed_soc_ast2700_realize(DeviceState *dev, Error **errp)
Aspeed27x0SoCState *a = ASPEED27X0_SOC(dev);
AspeedSoCState *s = ASPEED_SOC(dev);
AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
- AspeedINTCClass *ic = ASPEED_INTC_GET_CLASS(&a->intc);
+ AspeedINTCClass *ic = ASPEED_INTC_GET_CLASS(&a->intc[0]);
g_autofree char *sram_name = NULL;
qemu_irq irq;
@@ -533,23 +553,23 @@ static void aspeed_soc_ast2700_realize(DeviceState *dev, Error **errp)
}
/* INTC */
- if (!sysbus_realize(SYS_BUS_DEVICE(&a->intc), errp)) {
+ if (!sysbus_realize(SYS_BUS_DEVICE(&a->intc[0]), errp)) {
return;
}
- aspeed_mmio_map(s, SYS_BUS_DEVICE(&a->intc), 0,
+ aspeed_mmio_map(s, SYS_BUS_DEVICE(&a->intc[0]), 0,
sc->memmap[ASPEED_DEV_INTC]);
/* irq sources -> orgates -> INTC */
for (i = 0; i < ic->num_inpins; i++) {
- qdev_connect_gpio_out(DEVICE(&a->intc.orgates[i]), 0,
- qdev_get_gpio_in(DEVICE(&a->intc), i));
+ qdev_connect_gpio_out(DEVICE(&a->intc[0].orgates[i]), 0,
+ qdev_get_gpio_in(DEVICE(&a->intc[0]), i));
}
/* INTC -> GIC192 - GIC201 */
/* INTC -> GIC128 - GIC136 */
for (i = 0; i < ic->num_outpins; i++) {
- sysbus_connect_irq(SYS_BUS_DEVICE(&a->intc), i,
+ sysbus_connect_irq(SYS_BUS_DEVICE(&a->intc[0]), i,
qdev_get_gpio_in(DEVICE(&a->gic),
ast2700_gic_intcmap[i].irq));
}
--
2.43.0
next prev parent reply other threads:[~2025-03-07 4:03 UTC|newest]
Thread overview: 39+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-03-07 3:59 [PATCH v6 00/29] Support AST2700 A1 Jamin Lin via
2025-03-07 3:59 ` [PATCH v6 01/29] hw/intc/aspeed: Support setting different memory size Jamin Lin via
2025-03-07 3:59 ` [PATCH v6 02/29] hw/intc/aspeed: Rename status_addr and addr to status_reg and reg for clarity Jamin Lin via
2025-03-07 3:59 ` [PATCH v6 03/29] hw/intc/aspeed: Introduce dynamic allocation for regs array Jamin Lin via
2025-03-07 7:23 ` Cédric Le Goater
2025-03-07 3:59 ` [PATCH v6 04/29] hw/intc/aspeed: Support setting different register size Jamin Lin via
2025-03-07 7:23 ` Cédric Le Goater
2025-03-07 3:59 ` [PATCH v6 05/29] hw/intc/aspeed: Reduce regs array size by adding a register sub-region Jamin Lin via
2025-03-07 7:22 ` Cédric Le Goater
2025-03-07 3:59 ` [PATCH v6 06/29] hw/intc/aspeed: Introduce helper functions for enable and status registers Jamin Lin via
2025-03-07 3:59 ` [PATCH v6 07/29] hw/intc/aspeed: Add object type name to trace events for better debugging Jamin Lin via
2025-03-07 3:59 ` [PATCH v6 08/29] hw/arm/aspeed: Rename IRQ table and machine name for AST2700 A0 Jamin Lin via
2025-03-07 3:59 ` [PATCH v6 09/29] hw/arm/aspeed_ast27x0: Sort the IRQ table by IRQ number Jamin Lin via
2025-03-07 3:59 ` [PATCH v6 10/29] hw/intc/aspeed: Support different memory region ops Jamin Lin via
2025-03-07 3:59 ` [PATCH v6 11/29] hw/intc/aspeed: Rename num_ints to num_inpins for clarity Jamin Lin via
2025-03-07 3:59 ` [PATCH v6 12/29] hw/intc/aspeed: Add support for multiple output pins in INTC Jamin Lin via
2025-03-07 3:59 ` [PATCH v6 13/29] hw/intc/aspeed: Refactor INTC to support separate input and output pin indices Jamin Lin via
2025-03-07 3:59 ` [PATCH v6 14/29] hw/intc/aspeed: Introduce AspeedINTCIRQ structure to save the irq index and register address Jamin Lin via
2025-03-07 3:59 ` [PATCH v6 15/29] hw/intc/aspeed: Introduce IRQ handler function to reduce code duplication Jamin Lin via
2025-03-07 3:59 ` [PATCH v6 16/29] hw/intc/aspeed: Add Support for Multi-Output IRQ Handling Jamin Lin via
2025-03-07 3:59 ` [PATCH v6 17/29] hw/intc/aspeed: Add Support for AST2700 INTCIO Controller Jamin Lin via
2025-03-07 3:59 ` [PATCH v6 18/29] hw/misc/aspeed_scu: Add Support for AST2700/AST2750 A1 Silicon Revisions Jamin Lin via
2025-03-07 3:59 ` [PATCH v6 19/29] hw/arm/aspeed_ast27x0.c Support AST2700 A1 GIC Interrupt Mapping Jamin Lin via
2025-03-07 3:59 ` Jamin Lin via [this message]
2025-03-07 3:59 ` [PATCH v6 21/29] hw/arm/aspeed_ast27x0: Support two levels of INTC controllers for AST2700 A1 Jamin Lin via
2025-03-07 3:59 ` [PATCH v6 22/29] hw/arm/aspeed_ast27x0: Add SoC Support " Jamin Lin via
2025-03-07 3:59 ` [PATCH v6 23/29] hw/arm/aspeed: Add Machine " Jamin Lin via
2025-03-07 3:59 ` [PATCH v6 24/29] hw/arm/aspeed_ast27x0: Sort the memmap table by mapping address Jamin Lin via
2025-03-07 3:59 ` [PATCH v6 25/29] tests/functional/aspeed: Introduce start_ast2700_test API Jamin Lin via
2025-03-07 3:59 ` [PATCH v6 26/29] tests/functional/aspeed: Update temperature hwmon path Jamin Lin via
2025-03-07 3:59 ` [PATCH v6 27/29] tests/functional/aspeed: Update test ASPEED SDK v09.05 Jamin Lin via
2025-03-07 3:59 ` [PATCH v6 28/29] tests/functional/aspeed: Add test case for AST2700 A1 Jamin Lin via
2025-03-07 3:59 ` [PATCH v6 29/29] docs/specs: Add aspeed-intc Jamin Lin via
2025-03-07 7:33 ` [PATCH v6 00/29] Support AST2700 A1 Cédric Le Goater
2025-03-07 7:36 ` Jamin Lin
2025-03-07 7:44 ` Cédric Le Goater
2025-03-07 7:56 ` Steven Lee
2025-03-07 8:08 ` Cédric Le Goater
2025-03-07 17:47 ` Nabih Estefan
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20250307035945.3698802-21-jamin_lin@aspeedtech.com \
--to=qemu-devel@nongnu.org \
--cc=andrew@codeconstruct.com.au \
--cc=clg@kaod.org \
--cc=clg@redhat.com \
--cc=jamin_lin@aspeedtech.com \
--cc=joel@jms.id.au \
--cc=leetroy@gmail.com \
--cc=peter.maydell@linaro.org \
--cc=qemu-arm@nongnu.org \
--cc=steven_lee@aspeedtech.com \
--cc=troy_lee@aspeedtech.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).