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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-43bd4292b06sm121601615e9.14.2025.03.08.11.03.24 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Sat, 08 Mar 2025 11:03:25 -0800 (PST) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: BALATON Zoltan , qemu-devel@nongnu.org Cc: Bernhard Beschow , Peter Maydell , qemu-ppc@nongnu.org, Andrey Smirnov , Jean-Christophe Dubois , Bin Meng , qemu-arm@nongnu.org, qemu-block@nongnu.org, Guenter Roeck , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v3 11/12] hw/sd/sdhci: Implement Freescale eSDHC as TYPE_FSL_ESDHC Date: Sat, 8 Mar 2025 20:02:29 +0100 Message-ID: <20250308190230.7508-12-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250308190230.7508-1-philmd@linaro.org> References: <20250308190230.7508-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::32e; envelope-from=philmd@linaro.org; helo=mail-wm1-x32e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Per the MPC8569E reference manual, its SDHC I/O range is 4KiB wide, mapped in big endian order, and it only accepts 32-bit aligned access. Set the default register reset values. Reported-by: BALATON Zoltan Signed-off-by: Philippe Mathieu-Daudé --- include/hw/sd/sdhci.h | 2 ++ hw/sd/sdhci.c | 37 ++++++++++++++++++++++++++++++++++++- 2 files changed, 38 insertions(+), 1 deletion(-) diff --git a/include/hw/sd/sdhci.h b/include/hw/sd/sdhci.h index e24392eb10d..0e9d3b10d1b 100644 --- a/include/hw/sd/sdhci.h +++ b/include/hw/sd/sdhci.h @@ -161,6 +161,8 @@ DECLARE_INSTANCE_CHECKER(SDHCIState, SYSBUS_SDHCI, DECLARE_CLASS_CHECKERS(SDHCIClass, SYSBUS_SDHCI, TYPE_SYSBUS_SDHCI) +#define TYPE_FSL_ESDHC "fsl-esdhc" + #define TYPE_IMX_USDHC "imx-usdhc" #define TYPE_S3C_SDHCI "s3c-sdhci" diff --git a/hw/sd/sdhci.c b/hw/sd/sdhci.c index cda608f8ec2..a78cff40fb1 100644 --- a/hw/sd/sdhci.c +++ b/hw/sd/sdhci.c @@ -1644,7 +1644,37 @@ static void sdhci_bus_class_init(ObjectClass *klass, void *data) sbc->set_readonly = sdhci_set_readonly; } -/* --- qdev i.MX eSDHC --- */ +/* --- Freescale eSDHC (MPC8569ERM Rev.2 from 06/2011) --- */ + +static const MemoryRegionOps fsl_esdhc_mmio_ops = { + .read = sdhci_read, + .write = sdhci_write, + .valid = { + .min_access_size = 4, + .unaligned = false + }, + .endianness = DEVICE_BIG_ENDIAN, +}; + +static void fsl_esdhc_class_init(ObjectClass *oc, void *data) +{ + SDHCIClass *sc = SYSBUS_SDHCI_CLASS(oc); + + sc->iomem_size = 0x1000; + sc->io_ops = &fsl_esdhc_mmio_ops; + sc->ro.capareg = 0x01e30000; + sc->reset.sdmasysad = 8; + sc->reset.blkcnt = 8; + sc->reset.prnsts = 0xff800000; + sc->reset.hostctl1 = 0x20; /* Endian mode (address-invariant) */ + sc->reset.clkcon = 0x8000; + sc->reset.norintstsen = 0x013f; + sc->reset.errintstsen = 0x117f; + + sdhci_common_class_init(oc, data); +} + +/* --- qdev i.MX uSDHC --- */ #define USDHC_MIX_CTRL 0x48 @@ -1974,6 +2004,11 @@ static const TypeInfo sdhci_types[] = { .class_size = sizeof(SDHCIClass), .class_init = sdhci_sysbus_class_init, }, + { + .name = TYPE_FSL_ESDHC, + .parent = TYPE_SYSBUS_SDHCI, + .class_init = fsl_esdhc_class_init, + }, { .name = TYPE_IMX_USDHC, .parent = TYPE_SYSBUS_SDHCI, -- 2.47.1