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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3912c0e2eecsm9836336f8f.79.2025.03.08.13.36.41 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Sat, 08 Mar 2025 13:36:42 -0800 (PST) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org, BALATON Zoltan Cc: =?UTF-8?q?Daniel=20P=2E=20Berrang=C3=A9?= , Eduardo Habkost , Peter Maydell , qemu-ppc@nongnu.org, Paolo Bonzini , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Andrey Smirnov , Bernhard Beschow , Jean-Christophe Dubois , Guenter Roeck , qemu-block@nongnu.org, Bin Meng , qemu-arm@nongnu.org Subject: [PATCH v4 00/14] hw/sd/sdhci: Set reset value of interrupt registers Date: Sat, 8 Mar 2025 22:36:26 +0100 Message-ID: <20250308213640.13138-1-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::335; envelope-from=philmd@linaro.org; helo=mail-wm1-x335.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Since v3: - Fix "hw/qdev-properties-system.h" (first patch) - Convert to EndianMode (patch #10) Rainy saturday, time for some hobbyist contributions :) In this series we try to address the issue Zoltan reported and try to fix in [*], but using a more generic approach. The SDHCI code ends up better consolidated and ready to scale for more vendor implementations. I expect (with few QOM knowledge) this to be trivial to review. - Remove SDHCIState::vendor field - Convert state fields to class ones - Simplify endianness handling - Add default reset values as class fields [*] https://lore.kernel.org/qemu-devel/20250210160329.DDA7F4E600E@zero.eik.bme.hu/ Philippe Mathieu-Daudé (14): hw/qdev-properties-system: Include missing 'qapi/qapi-types-common.h' hw/sd/sdhci: Remove need for SDHCIState::vendor field hw/sd/sdhci: Introduce SDHCIClass stub hw/sd/sdhci: Make quirks a class property hw/sd/sdhci: Make I/O region size a class property hw/sd/sdhci: Enforce little endianness on PCI devices hw/sd/sdhci: Allow SDHCI classes to register their own MemoryRegionOps hw/sd/sdhci: Simplify MemoryRegionOps endianness check hw/sd/sdhci: Unify default MemoryRegionOps hw/sd/sdhci: Convert SDHCIState::endianness to EndianMode hw/sd/sdhci: Add SDHCIClass::ro::capareg field hw/sd/sdhci: Allow SDHCI classes to have different register reset values hw/sd/sdhci: Implement Freescale eSDHC as TYPE_FSL_ESDHC hw/ppc/e500: Replace generic SDHCI by Freescale eSDHC hw/sd/sdhci-internal.h | 28 ++--- include/hw/qdev-properties-system.h | 1 + include/hw/sd/sdhci.h | 46 +++++++- hw/arm/fsl-imx25.c | 2 - hw/arm/fsl-imx6.c | 2 - hw/arm/fsl-imx6ul.c | 2 - hw/arm/fsl-imx7.c | 2 - hw/arm/fsl-imx8mp.c | 2 - hw/ppc/e500.c | 12 +- hw/sd/sdhci-pci.c | 1 + hw/sd/sdhci.c | 172 ++++++++++++++++++---------- 11 files changed, 170 insertions(+), 100 deletions(-) -- 2.47.1