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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-43bd42c6203sm124940935e9.24.2025.03.08.13.37.39 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Sat, 08 Mar 2025 13:37:40 -0800 (PST) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org, BALATON Zoltan Cc: =?UTF-8?q?Daniel=20P=2E=20Berrang=C3=A9?= , Eduardo Habkost , Peter Maydell , qemu-ppc@nongnu.org, Paolo Bonzini , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Andrey Smirnov , Bernhard Beschow , Jean-Christophe Dubois , Guenter Roeck , qemu-block@nongnu.org, Bin Meng , qemu-arm@nongnu.org Subject: [PATCH v4 11/14] hw/sd/sdhci: Add SDHCIClass::ro::capareg field Date: Sat, 8 Mar 2025 22:36:37 +0100 Message-ID: <20250308213640.13138-12-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250308213640.13138-1-philmd@linaro.org> References: <20250308213640.13138-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::32d; envelope-from=philmd@linaro.org; helo=mail-wm1-x32d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Capability register is read-only. Since we allow instances to clear/set extra bits, log when read-only bits normally set by hardware are cleared at board level. Signed-off-by: Philippe Mathieu-Daudé --- include/hw/sd/sdhci.h | 5 +++++ hw/sd/sdhci.c | 6 ++++++ 2 files changed, 11 insertions(+) diff --git a/include/hw/sd/sdhci.h b/include/hw/sd/sdhci.h index a91cda16cbe..15ef3a07b54 100644 --- a/include/hw/sd/sdhci.h +++ b/include/hw/sd/sdhci.h @@ -116,6 +116,11 @@ typedef struct SDHCIClass { const MemoryRegionOps *io_ops; uint32_t quirks; uint64_t iomem_size; + + /* Read-only registers */ + struct { + uint64_t capareg; + } ro; } SDHCIClass; /* diff --git a/hw/sd/sdhci.c b/hw/sd/sdhci.c index f2bb612c665..9708b52f850 100644 --- a/hw/sd/sdhci.c +++ b/hw/sd/sdhci.c @@ -73,6 +73,7 @@ static bool sdhci_check_capab_freq_range(SDHCIState *s, const char *desc, static void sdhci_check_capareg(SDHCIState *s, Error **errp) { + SDHCIClass *sc = SYSBUS_SDHCI_GET_CLASS(s); uint64_t msk = s->capareg; uint32_t val; bool y; @@ -208,6 +209,11 @@ static void sdhci_check_capareg(SDHCIState *s, Error **errp) qemu_log_mask(LOG_UNIMP, "SDHCI: unknown CAPAB mask: 0x%016" PRIx64 "\n", msk); } + msk = sc->ro.capareg & ~s->capareg; + if (msk) { + qemu_log_mask(LOG_UNIMP, + "SDHCI: ignored CAPAB mask: 0x%016" PRIx64 "\n", msk); + } } static uint8_t sdhci_slotint(SDHCIState *s) -- 2.47.1