From: "Cédric Le Goater" <clg@redhat.com>
To: qemu-arm@nongnu.org, qemu-devel@nongnu.org
Cc: "Jamin Lin" <jamin_lin@aspeedtech.com>,
"Andrew Jeffery" <andrew@codeconstruct.com.au>,
"Cédric Le Goater" <clg@redhat.com>
Subject: [PULL 10/46] hw/arm/aspeed_ast27x0: Add HACE support for AST2700
Date: Sun, 9 Mar 2025 14:50:54 +0100 [thread overview]
Message-ID: <20250309135130.545764-11-clg@redhat.com> (raw)
In-Reply-To: <20250309135130.545764-1-clg@redhat.com>
From: Jamin Lin <jamin_lin@aspeedtech.com>
The HACE controller between AST2600 and AST2700 are almost identical.
The HACE controller registers base address starts at 0x1207_0000 and
its alarm interrupt is connected to GICINT4.
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
Reviewed-by: Andrew Jeffery <andrew@codeconstruct.com.au>
Link: https://lore.kernel.org/qemu-devel/20250225075622.305515-4-jamin_lin@aspeedtech.com
Signed-off-by: Cédric Le Goater <clg@redhat.com>
---
hw/arm/aspeed_ast27x0.c | 15 +++++++++++++++
1 file changed, 15 insertions(+)
diff --git a/hw/arm/aspeed_ast27x0.c b/hw/arm/aspeed_ast27x0.c
index 6506bdfdff68..56e43d45ad22 100644
--- a/hw/arm/aspeed_ast27x0.c
+++ b/hw/arm/aspeed_ast27x0.c
@@ -67,6 +67,7 @@ static const hwaddr aspeed_soc_ast2700_memmap[] = {
[ASPEED_DEV_RTC] = 0x12C0F000,
[ASPEED_DEV_SDHCI] = 0x14080000,
[ASPEED_DEV_TIMER1] = 0x12C10000,
+ [ASPEED_DEV_HACE] = 0x12070000,
};
#define AST2700_MAX_IRQ 256
@@ -401,6 +402,9 @@ static void aspeed_soc_ast2700_init(Object *obj)
snprintf(typename, sizeof(typename), "aspeed.timer-%s", socname);
object_initialize_child(obj, "timerctrl", &s->timerctrl, typename);
+
+ snprintf(typename, sizeof(typename), "aspeed.hace-%s", socname);
+ object_initialize_child(obj, "hace", &s->hace, typename);
}
/*
@@ -737,6 +741,17 @@ static void aspeed_soc_ast2700_realize(DeviceState *dev, Error **errp)
sysbus_connect_irq(SYS_BUS_DEVICE(&s->timerctrl), i, irq);
}
+ /* HACE */
+ object_property_set_link(OBJECT(&s->hace), "dram", OBJECT(s->dram_mr),
+ &error_abort);
+ if (!sysbus_realize(SYS_BUS_DEVICE(&s->hace), errp)) {
+ return;
+ }
+ aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->hace), 0,
+ sc->memmap[ASPEED_DEV_HACE]);
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->hace), 0,
+ aspeed_soc_get_irq(s, ASPEED_DEV_HACE));
+
create_unimplemented_device("ast2700.dpmcu", 0x11000000, 0x40000);
create_unimplemented_device("ast2700.iomem0", 0x12000000, 0x01000000);
create_unimplemented_device("ast2700.iomem1", 0x14000000, 0x01000000);
--
2.48.1
next prev parent reply other threads:[~2025-03-09 13:53 UTC|newest]
Thread overview: 54+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-03-09 13:50 [PULL 00/46] aspeed queue Cédric Le Goater
2025-03-09 13:50 ` [PULL 01/46] tests/functional: Introduce a new test routine for OpenBMC images Cédric Le Goater
2025-03-09 13:50 ` [PULL 02/46] tests/functional: Update OpenBMC image of palmetto machine Cédric Le Goater
2025-03-09 13:50 ` [PULL 03/46] tests/functional: Update OpenBMC image of romulus machine Cédric Le Goater
2025-03-09 13:50 ` [PULL 04/46] tests/functional: Introduce a witherspoon machine test Cédric Le Goater
2025-03-09 13:50 ` [PULL 05/46] tests/functional: Introduce a bletchley " Cédric Le Goater
2025-03-09 13:50 ` [PULL 06/46] aspeed/soc: Support Non-maskable Interrupt for AST2700 Cédric Le Goater
2025-03-09 13:50 ` [PULL 07/46] aspeed: Remove duplicate typename in AspeedSoCClass Cédric Le Goater
2025-03-09 13:50 ` [PULL 08/46] hw/misc/aspeed_hace: Fix coding style Cédric Le Goater
2025-03-09 13:50 ` [PULL 09/46] hw/misc/aspeed_hace: Add AST2700 support Cédric Le Goater
2025-03-09 13:50 ` Cédric Le Goater [this message]
2025-03-09 13:50 ` [PULL 11/46] hw/misc/aspeed_hace: Fix boot issue in the Crypto Manager Self Test Cédric Le Goater
2025-03-09 13:50 ` [PULL 12/46] hw/misc/aspeed_scu: Skipping dram_init in u-boot Cédric Le Goater
2025-03-09 13:50 ` [PULL 13/46] hw/misc/aspeed_scu: Fix the revision ID cannot be set in the SOC layer for AST2700 Cédric Le Goater
2025-03-09 13:50 ` [PULL 14/46] hw/arm/aspeed Update HW Strap Default Values " Cédric Le Goater
2025-03-09 13:50 ` [PULL 15/46] hw/misc/aspeed_scu: Fix the hw-strap1 cannot be set in the SOC layer " Cédric Le Goater
2025-03-09 13:51 ` [PULL 16/46] hw/arm/aspeed_ast27x0.c Separate HW Strap Registers for SCU and SCUIO Cédric Le Goater
2025-03-09 13:51 ` [PULL 17/46] hw/arm/aspeed_ast27x0.c Fix boot issue for AST2700 Cédric Le Goater
2025-03-09 13:51 ` [PULL 18/46] hw/intc/aspeed: Support setting different memory size Cédric Le Goater
2025-03-09 13:51 ` [PULL 19/46] hw/intc/aspeed: Rename status_addr and addr to status_reg and reg for clarity Cédric Le Goater
2025-03-09 13:51 ` [PULL 20/46] hw/intc/aspeed: Introduce dynamic allocation for regs array Cédric Le Goater
2025-03-09 13:51 ` [PULL 21/46] hw/intc/aspeed: Support setting different register size Cédric Le Goater
2025-03-09 13:51 ` [PULL 22/46] hw/intc/aspeed: Reduce regs array size by adding a register sub-region Cédric Le Goater
2025-03-09 13:51 ` [PULL 23/46] hw/intc/aspeed: Introduce helper functions for enable and status registers Cédric Le Goater
2025-03-09 13:51 ` [PULL 24/46] hw/intc/aspeed: Add object type name to trace events for better debugging Cédric Le Goater
2025-03-09 13:51 ` [PULL 25/46] hw/arm/aspeed: Rename IRQ table and machine name for AST2700 A0 Cédric Le Goater
2025-03-09 13:51 ` [PULL 26/46] hw/arm/aspeed_ast27x0: Sort the IRQ table by IRQ number Cédric Le Goater
2025-03-09 13:51 ` [PULL 27/46] hw/intc/aspeed: Support different memory region ops Cédric Le Goater
2025-03-09 13:51 ` [PULL 28/46] hw/intc/aspeed: Rename num_ints to num_inpins for clarity Cédric Le Goater
2025-03-09 13:51 ` [PULL 29/46] hw/intc/aspeed: Add support for multiple output pins in INTC Cédric Le Goater
2025-03-09 13:51 ` [PULL 30/46] hw/intc/aspeed: Refactor INTC to support separate input and output pin indices Cédric Le Goater
2025-03-09 13:51 ` [PULL 31/46] hw/intc/aspeed: Introduce AspeedINTCIRQ structure to save the irq index and register address Cédric Le Goater
2025-03-09 13:51 ` [PULL 32/46] hw/intc/aspeed: Introduce IRQ handler function to reduce code duplication Cédric Le Goater
2025-03-09 13:51 ` [PULL 33/46] hw/intc/aspeed: Add Support for Multi-Output IRQ Handling Cédric Le Goater
2025-03-09 13:51 ` [PULL 34/46] hw/intc/aspeed: Add Support for AST2700 INTCIO Controller Cédric Le Goater
2025-05-16 11:50 ` Philippe Mathieu-Daudé
2025-05-19 1:43 ` Jamin Lin
2025-03-09 13:51 ` [PULL 35/46] hw/misc/aspeed_scu: Add Support for AST2700/AST2750 A1 Silicon Revisions Cédric Le Goater
2025-03-09 13:51 ` [PULL 36/46] hw/arm/aspeed_ast27x0.c Support AST2700 A1 GIC Interrupt Mapping Cédric Le Goater
2025-03-09 13:51 ` [PULL 37/46] hw/arm/aspeed_ast27x0: Define an Array of AspeedINTCState with Two Instances Cédric Le Goater
2025-03-09 13:51 ` [PULL 38/46] hw/arm/aspeed_ast27x0: Support two levels of INTC controllers for AST2700 A1 Cédric Le Goater
2025-03-09 13:51 ` [PULL 39/46] hw/arm/aspeed_ast27x0: Add SoC Support " Cédric Le Goater
2025-03-09 13:51 ` [PULL 40/46] hw/arm/aspeed: Add Machine " Cédric Le Goater
2025-03-09 13:51 ` [PULL 41/46] hw/arm/aspeed_ast27x0: Sort the memmap table by mapping address Cédric Le Goater
2025-03-09 13:51 ` [PULL 42/46] tests/functional/aspeed: Introduce start_ast2700_test API Cédric Le Goater
2025-03-09 13:51 ` [PULL 43/46] tests/functional/aspeed: Update temperature hwmon path Cédric Le Goater
2025-03-09 13:51 ` [PULL 44/46] tests/functional/aspeed: Update test ASPEED SDK v09.05 Cédric Le Goater
2025-03-09 13:51 ` [PULL 45/46] tests/functional/aspeed: Add test case for AST2700 A1 Cédric Le Goater
2025-05-15 12:39 ` Cédric Le Goater
2025-05-16 2:59 ` Jamin Lin
2025-05-16 9:20 ` Cédric Le Goater
2025-05-19 1:52 ` Jamin Lin
2025-05-19 8:34 ` Cédric Le Goater
2025-03-09 13:51 ` [PULL 46/46] docs/specs: Add aspeed-intc Cédric Le Goater
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