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From: "Philippe Mathieu-Daudé" <philmd@linaro.org>
To: qemu-devel@nongnu.org
Subject: [PULL 29/38] target/riscv: Move has_work() from CPUClass to SysemuCPUOps
Date: Sun,  9 Mar 2025 18:51:58 +0100	[thread overview]
Message-ID: <20250309175207.43828-30-philmd@linaro.org> (raw)
In-Reply-To: <20250309175207.43828-1-philmd@linaro.org>

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20250125170125.32855-17-philmd@linaro.org>
---
 target/riscv/internals.h | 4 +++-
 target/riscv/cpu.c       | 8 +++-----
 2 files changed, 6 insertions(+), 6 deletions(-)

diff --git a/target/riscv/internals.h b/target/riscv/internals.h
index 67291933f84..213aff31d85 100644
--- a/target/riscv/internals.h
+++ b/target/riscv/internals.h
@@ -142,8 +142,10 @@ static inline float16 check_nanbox_h(CPURISCVState *env, uint64_t f)
     }
 }
 
-/* Our implementation of CPUClass::has_work */
+#ifndef CONFIG_USER_ONLY
+/* Our implementation of SysemuCPUOps::has_work */
 bool riscv_cpu_has_work(CPUState *cs);
+#endif
 
 /* Zjpm addr masking routine */
 static inline target_ulong adjust_addr_body(CPURISCVState *env,
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 1c000c30f8d..09ded6829a2 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -1006,9 +1006,9 @@ static vaddr riscv_cpu_get_pc(CPUState *cs)
     return env->pc;
 }
 
+#ifndef CONFIG_USER_ONLY
 bool riscv_cpu_has_work(CPUState *cs)
 {
-#ifndef CONFIG_USER_ONLY
     RISCVCPU *cpu = RISCV_CPU(cs);
     CPURISCVState *env = &cpu->env;
     /*
@@ -1018,10 +1018,8 @@ bool riscv_cpu_has_work(CPUState *cs)
     return riscv_cpu_all_pending(env) != 0 ||
         riscv_cpu_sirq_pending(env) != RISCV_EXCP_NONE ||
         riscv_cpu_vsirq_pending(env) != RISCV_EXCP_NONE;
-#else
-    return true;
-#endif
 }
+#endif /* !CONFIG_USER_ONLY */
 
 static int riscv_cpu_mmu_index(CPUState *cs, bool ifetch)
 {
@@ -3029,6 +3027,7 @@ static int64_t riscv_get_arch_id(CPUState *cs)
 #include "hw/core/sysemu-cpu-ops.h"
 
 static const struct SysemuCPUOps riscv_sysemu_ops = {
+    .has_work = riscv_cpu_has_work,
     .get_phys_page_debug = riscv_cpu_get_phys_page_debug,
     .write_elf64_note = riscv_cpu_write_elf64_note,
     .write_elf32_note = riscv_cpu_write_elf32_note,
@@ -3050,7 +3049,6 @@ static void riscv_cpu_common_class_init(ObjectClass *c, void *data)
                                        &mcc->parent_phases);
 
     cc->class_by_name = riscv_cpu_class_by_name;
-    cc->has_work = riscv_cpu_has_work;
     cc->mmu_index = riscv_cpu_mmu_index;
     cc->dump_state = riscv_cpu_dump_state;
     cc->set_pc = riscv_cpu_set_pc;
-- 
2.47.1



  parent reply	other threads:[~2025-03-09 17:58 UTC|newest]

Thread overview: 39+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-03-09 17:51 [PULL 00/38] Accelerators & CPU patches for 2025-03-09 Philippe Mathieu-Daudé
2025-03-09 17:51 ` [PULL 01/38] linux-user: Only include 'exec/tb-flush.h' header when necessary Philippe Mathieu-Daudé
2025-03-09 17:51 ` [PULL 02/38] bsd-user: Always use mmap_find_vma_aligned() in target_mmap() Philippe Mathieu-Daudé
2025-03-09 17:51 ` [PULL 03/38] bsd-user: Propagate alignment argument to mmap_find_vma() Philippe Mathieu-Daudé
2025-03-09 17:51 ` [PULL 04/38] user: Extract common MMAP API to 'user/mmap.h' Philippe Mathieu-Daudé
2025-03-09 17:51 ` [PULL 05/38] cpus: Register VMState per user / system emulation Philippe Mathieu-Daudé
2025-03-09 17:51 ` [PULL 06/38] cpus: Build cpu_exec_[un]realizefn() methods once Philippe Mathieu-Daudé
2025-03-09 17:51 ` [PULL 07/38] cpus: Prefer cached CpuClass over CPU_GET_CLASS() macro Philippe Mathieu-Daudé
2025-03-09 17:51 ` [PULL 08/38] accel: " Philippe Mathieu-Daudé
2025-03-09 17:51 ` [PULL 09/38] user: " Philippe Mathieu-Daudé
2025-03-09 17:51 ` [PULL 10/38] disas: " Philippe Mathieu-Daudé
2025-03-09 17:51 ` [PULL 11/38] gdbstub: " Philippe Mathieu-Daudé
2025-03-09 17:51 ` [PULL 12/38] hw/acpi: " Philippe Mathieu-Daudé
2025-03-09 17:51 ` [PULL 13/38] target/arm: " Philippe Mathieu-Daudé
2025-03-09 17:51 ` [PULL 14/38] cpus: Restrict cpu_has_work() to system emulation Philippe Mathieu-Daudé
2025-03-09 17:51 ` [PULL 15/38] cpus: Un-inline cpu_has_work() Philippe Mathieu-Daudé
2025-03-09 17:51 ` [PULL 16/38] cpus: Introduce SysemuCPUOps::has_work() handler Philippe Mathieu-Daudé
2025-03-09 17:51 ` [PULL 17/38] target/alpha: Move has_work() from CPUClass to SysemuCPUOps Philippe Mathieu-Daudé
2025-03-09 17:51 ` [PULL 18/38] target/arm: " Philippe Mathieu-Daudé
2025-03-09 17:51 ` [PULL 19/38] target/avr: " Philippe Mathieu-Daudé
2025-03-09 17:51 ` [PULL 20/38] target/hexagon: Remove CPUClass:has_work() handler Philippe Mathieu-Daudé
2025-03-09 17:51 ` [PULL 21/38] target/hppa: Move has_work() from CPUClass to SysemuCPUOps Philippe Mathieu-Daudé
2025-03-09 17:51 ` [PULL 22/38] target/i386: " Philippe Mathieu-Daudé
2025-03-09 17:51 ` [PULL 23/38] target/loongarch: " Philippe Mathieu-Daudé
2025-03-09 17:51 ` [PULL 24/38] target/m68k: " Philippe Mathieu-Daudé
2025-03-09 17:51 ` [PULL 25/38] target/microblaze: " Philippe Mathieu-Daudé
2025-03-09 17:51 ` [PULL 26/38] target/mips: " Philippe Mathieu-Daudé
2025-03-09 17:51 ` [PULL 27/38] target/openrisc: " Philippe Mathieu-Daudé
2025-03-09 17:51 ` [PULL 28/38] target/ppc: " Philippe Mathieu-Daudé
2025-03-09 17:51 ` Philippe Mathieu-Daudé [this message]
2025-03-09 17:51 ` [PULL 30/38] target/rx: " Philippe Mathieu-Daudé
2025-03-09 17:52 ` [PULL 31/38] target/s390x: Restrict I/O handler installers to system emulation Philippe Mathieu-Daudé
2025-03-09 17:52 ` [PULL 32/38] target/s390x: Move has_work() from CPUClass to SysemuCPUOps Philippe Mathieu-Daudé
2025-03-09 17:52 ` [PULL 33/38] target/sh4: " Philippe Mathieu-Daudé
2025-03-09 17:52 ` [PULL 34/38] target/sparc: " Philippe Mathieu-Daudé
2025-03-09 17:52 ` [PULL 35/38] target/tricore: " Philippe Mathieu-Daudé
2025-03-09 17:52 ` [PULL 36/38] target/xtensa: " Philippe Mathieu-Daudé
2025-03-09 17:52 ` [PULL 37/38] cpus: Remove CPUClass::has_work() handler Philippe Mathieu-Daudé
2025-03-09 17:52 ` [PULL 38/38] MAINTAINERS: Consolidate core exec/vCPU handling section Philippe Mathieu-Daudé

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