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From: "Philippe Mathieu-Daudé" <philmd@linaro.org>
To: qemu-devel@nongnu.org
Subject: [PULL 08/38] accel: Prefer cached CpuClass over CPU_GET_CLASS() macro
Date: Sun,  9 Mar 2025 18:51:37 +0100	[thread overview]
Message-ID: <20250309175207.43828-9-philmd@linaro.org> (raw)
In-Reply-To: <20250309175207.43828-1-philmd@linaro.org>

CpuState caches its CPUClass since commit 6fbdff87062
("cpu: cache CPUClass in CPUState for hot code paths"),
use it.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20250122093028.52416-6-philmd@linaro.org>
---
 accel/accel-target.c      | 12 +++++-------
 accel/tcg/tcg-accel-ops.c |  3 +--
 accel/tcg/translate-all.c |  2 +-
 accel/tcg/watchpoint.c    |  9 ++++-----
 4 files changed, 11 insertions(+), 15 deletions(-)

diff --git a/accel/accel-target.c b/accel/accel-target.c
index 83587274626..33a539b4cbb 100644
--- a/accel/accel-target.c
+++ b/accel/accel-target.c
@@ -113,22 +113,20 @@ void accel_init_interfaces(AccelClass *ac)
 
 void accel_cpu_instance_init(CPUState *cpu)
 {
-    CPUClass *cc = CPU_GET_CLASS(cpu);
-
-    if (cc->accel_cpu && cc->accel_cpu->cpu_instance_init) {
-        cc->accel_cpu->cpu_instance_init(cpu);
+    if (cpu->cc->accel_cpu && cpu->cc->accel_cpu->cpu_instance_init) {
+        cpu->cc->accel_cpu->cpu_instance_init(cpu);
     }
 }
 
 bool accel_cpu_common_realize(CPUState *cpu, Error **errp)
 {
-    CPUClass *cc = CPU_GET_CLASS(cpu);
     AccelState *accel = current_accel();
     AccelClass *acc = ACCEL_GET_CLASS(accel);
 
     /* target specific realization */
-    if (cc->accel_cpu && cc->accel_cpu->cpu_target_realize
-        && !cc->accel_cpu->cpu_target_realize(cpu, errp)) {
+    if (cpu->cc->accel_cpu
+        && cpu->cc->accel_cpu->cpu_target_realize
+        && !cpu->cc->accel_cpu->cpu_target_realize(cpu, errp)) {
         return false;
     }
 
diff --git a/accel/tcg/tcg-accel-ops.c b/accel/tcg/tcg-accel-ops.c
index 53e580d128b..d9b662efe3b 100644
--- a/accel/tcg/tcg-accel-ops.c
+++ b/accel/tcg/tcg-accel-ops.c
@@ -121,10 +121,9 @@ static inline int xlat_gdb_type(CPUState *cpu, int gdbtype)
         [GDB_WATCHPOINT_ACCESS] = BP_GDB | BP_MEM_ACCESS,
     };
 
-    CPUClass *cc = CPU_GET_CLASS(cpu);
     int cputype = xlat[gdbtype];
 
-    if (cc->gdb_stop_before_watchpoint) {
+    if (cpu->cc->gdb_stop_before_watchpoint) {
         cputype |= BP_STOP_BEFORE_ACCESS;
     }
     return cputype;
diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c
index 0914d6e98b2..82bc16bd535 100644
--- a/accel/tcg/translate-all.c
+++ b/accel/tcg/translate-all.c
@@ -630,7 +630,7 @@ void cpu_io_recompile(CPUState *cpu, uintptr_t retaddr)
      * to account for the re-execution of the branch.
      */
     n = 1;
-    cc = CPU_GET_CLASS(cpu);
+    cc = cpu->cc;
     if (cc->tcg_ops->io_recompile_replay_branch &&
         cc->tcg_ops->io_recompile_replay_branch(cpu, tb)) {
         cpu->neg.icount_decr.u16.low++;
diff --git a/accel/tcg/watchpoint.c b/accel/tcg/watchpoint.c
index ba8c9859cf4..65b21884cec 100644
--- a/accel/tcg/watchpoint.c
+++ b/accel/tcg/watchpoint.c
@@ -68,7 +68,6 @@ int cpu_watchpoint_address_matches(CPUState *cpu, vaddr addr, vaddr len)
 void cpu_check_watchpoint(CPUState *cpu, vaddr addr, vaddr len,
                           MemTxAttrs attrs, int flags, uintptr_t ra)
 {
-    CPUClass *cc = CPU_GET_CLASS(cpu);
     CPUWatchpoint *wp;
 
     assert(tcg_enabled());
@@ -84,9 +83,9 @@ void cpu_check_watchpoint(CPUState *cpu, vaddr addr, vaddr len,
         return;
     }
 
-    if (cc->tcg_ops->adjust_watchpoint_address) {
+    if (cpu->cc->tcg_ops->adjust_watchpoint_address) {
         /* this is currently used only by ARM BE32 */
-        addr = cc->tcg_ops->adjust_watchpoint_address(cpu, addr, len);
+        addr = cpu->cc->tcg_ops->adjust_watchpoint_address(cpu, addr, len);
     }
 
     assert((flags & ~BP_MEM_ACCESS) == 0);
@@ -118,8 +117,8 @@ void cpu_check_watchpoint(CPUState *cpu, vaddr addr, vaddr len,
             wp->hitattrs = attrs;
 
             if (wp->flags & BP_CPU
-                && cc->tcg_ops->debug_check_watchpoint
-                && !cc->tcg_ops->debug_check_watchpoint(cpu, wp)) {
+                && cpu->cc->tcg_ops->debug_check_watchpoint
+                && !cpu->cc->tcg_ops->debug_check_watchpoint(cpu, wp)) {
                 wp->flags &= ~BP_WATCHPOINT_HIT;
                 continue;
             }
-- 
2.47.1



  parent reply	other threads:[~2025-03-09 17:54 UTC|newest]

Thread overview: 39+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-03-09 17:51 [PULL 00/38] Accelerators & CPU patches for 2025-03-09 Philippe Mathieu-Daudé
2025-03-09 17:51 ` [PULL 01/38] linux-user: Only include 'exec/tb-flush.h' header when necessary Philippe Mathieu-Daudé
2025-03-09 17:51 ` [PULL 02/38] bsd-user: Always use mmap_find_vma_aligned() in target_mmap() Philippe Mathieu-Daudé
2025-03-09 17:51 ` [PULL 03/38] bsd-user: Propagate alignment argument to mmap_find_vma() Philippe Mathieu-Daudé
2025-03-09 17:51 ` [PULL 04/38] user: Extract common MMAP API to 'user/mmap.h' Philippe Mathieu-Daudé
2025-03-09 17:51 ` [PULL 05/38] cpus: Register VMState per user / system emulation Philippe Mathieu-Daudé
2025-03-09 17:51 ` [PULL 06/38] cpus: Build cpu_exec_[un]realizefn() methods once Philippe Mathieu-Daudé
2025-03-09 17:51 ` [PULL 07/38] cpus: Prefer cached CpuClass over CPU_GET_CLASS() macro Philippe Mathieu-Daudé
2025-03-09 17:51 ` Philippe Mathieu-Daudé [this message]
2025-03-09 17:51 ` [PULL 09/38] user: " Philippe Mathieu-Daudé
2025-03-09 17:51 ` [PULL 10/38] disas: " Philippe Mathieu-Daudé
2025-03-09 17:51 ` [PULL 11/38] gdbstub: " Philippe Mathieu-Daudé
2025-03-09 17:51 ` [PULL 12/38] hw/acpi: " Philippe Mathieu-Daudé
2025-03-09 17:51 ` [PULL 13/38] target/arm: " Philippe Mathieu-Daudé
2025-03-09 17:51 ` [PULL 14/38] cpus: Restrict cpu_has_work() to system emulation Philippe Mathieu-Daudé
2025-03-09 17:51 ` [PULL 15/38] cpus: Un-inline cpu_has_work() Philippe Mathieu-Daudé
2025-03-09 17:51 ` [PULL 16/38] cpus: Introduce SysemuCPUOps::has_work() handler Philippe Mathieu-Daudé
2025-03-09 17:51 ` [PULL 17/38] target/alpha: Move has_work() from CPUClass to SysemuCPUOps Philippe Mathieu-Daudé
2025-03-09 17:51 ` [PULL 18/38] target/arm: " Philippe Mathieu-Daudé
2025-03-09 17:51 ` [PULL 19/38] target/avr: " Philippe Mathieu-Daudé
2025-03-09 17:51 ` [PULL 20/38] target/hexagon: Remove CPUClass:has_work() handler Philippe Mathieu-Daudé
2025-03-09 17:51 ` [PULL 21/38] target/hppa: Move has_work() from CPUClass to SysemuCPUOps Philippe Mathieu-Daudé
2025-03-09 17:51 ` [PULL 22/38] target/i386: " Philippe Mathieu-Daudé
2025-03-09 17:51 ` [PULL 23/38] target/loongarch: " Philippe Mathieu-Daudé
2025-03-09 17:51 ` [PULL 24/38] target/m68k: " Philippe Mathieu-Daudé
2025-03-09 17:51 ` [PULL 25/38] target/microblaze: " Philippe Mathieu-Daudé
2025-03-09 17:51 ` [PULL 26/38] target/mips: " Philippe Mathieu-Daudé
2025-03-09 17:51 ` [PULL 27/38] target/openrisc: " Philippe Mathieu-Daudé
2025-03-09 17:51 ` [PULL 28/38] target/ppc: " Philippe Mathieu-Daudé
2025-03-09 17:51 ` [PULL 29/38] target/riscv: " Philippe Mathieu-Daudé
2025-03-09 17:51 ` [PULL 30/38] target/rx: " Philippe Mathieu-Daudé
2025-03-09 17:52 ` [PULL 31/38] target/s390x: Restrict I/O handler installers to system emulation Philippe Mathieu-Daudé
2025-03-09 17:52 ` [PULL 32/38] target/s390x: Move has_work() from CPUClass to SysemuCPUOps Philippe Mathieu-Daudé
2025-03-09 17:52 ` [PULL 33/38] target/sh4: " Philippe Mathieu-Daudé
2025-03-09 17:52 ` [PULL 34/38] target/sparc: " Philippe Mathieu-Daudé
2025-03-09 17:52 ` [PULL 35/38] target/tricore: " Philippe Mathieu-Daudé
2025-03-09 17:52 ` [PULL 36/38] target/xtensa: " Philippe Mathieu-Daudé
2025-03-09 17:52 ` [PULL 37/38] cpus: Remove CPUClass::has_work() handler Philippe Mathieu-Daudé
2025-03-09 17:52 ` [PULL 38/38] MAINTAINERS: Consolidate core exec/vCPU handling section Philippe Mathieu-Daudé

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