From: "Philippe Mathieu-Daudé" <philmd@linaro.org>
To: BALATON Zoltan <balaton@eik.bme.hu>, qemu-devel@nongnu.org
Cc: "Steven Lee" <steven_lee@aspeedtech.com>,
"Joel Stanley" <joel@jms.id.au>,
"Bernhard Beschow" <shentey@gmail.com>,
"Peter Maydell" <peter.maydell@linaro.org>,
qemu-arm@nongnu.org, "Andrey Smirnov" <andrew.smirnov@gmail.com>,
"Paolo Bonzini" <pbonzini@redhat.com>,
"Bin Meng" <bmeng.cn@gmail.com>,
"Cédric Le Goater" <clg@kaod.org>,
"Eduardo Habkost" <eduardo@habkost.net>,
qemu-ppc@nongnu.org, "Daniel P. Berrangé" <berrange@redhat.com>,
"Guenter Roeck" <linux@roeck-us.net>,
"Andrew Jeffery" <andrew@codeconstruct.com.au>,
"Troy Lee" <leetroy@gmail.com>,
"Jean-Christophe Dubois" <jcd@tribudubois.net>,
"Philippe Mathieu-Daudé" <philmd@linaro.org>,
qemu-block@nongnu.org, "Jamin Lin" <jamin_lin@aspeedtech.com>
Subject: [PATCH v5 09/14] hw/sd/sdhci: Allow SDHCI classes to register their own MemoryRegionOps
Date: Mon, 10 Mar 2025 01:06:15 +0100 [thread overview]
Message-ID: <20250310000620.70120-10-philmd@linaro.org> (raw)
In-Reply-To: <20250310000620.70120-1-philmd@linaro.org>
Add MemoryRegionOps as a class property. For now it is only
used by TYPE_IMX_USDHC.
Otherwise the default remains in little endian.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
include/hw/sd/sdhci.h | 1 +
hw/sd/sdhci.c | 22 ++++++++--------------
2 files changed, 9 insertions(+), 14 deletions(-)
diff --git a/include/hw/sd/sdhci.h b/include/hw/sd/sdhci.h
index dfa0c214036..108bc1993c6 100644
--- a/include/hw/sd/sdhci.h
+++ b/include/hw/sd/sdhci.h
@@ -117,6 +117,7 @@ struct SDHCIClass {
SysBusDeviceClass sbd_parent_class;
};
+ const MemoryRegionOps *io_ops;
uint32_t quirks;
uint64_t iomem_size;
};
diff --git a/hw/sd/sdhci.c b/hw/sd/sdhci.c
index 3467385490d..6868bf68285 100644
--- a/hw/sd/sdhci.c
+++ b/hw/sd/sdhci.c
@@ -1428,8 +1428,6 @@ void sdhci_initfn(SDHCIState *s)
s->transfer_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL,
sdhci_data_transfer, s);
s->quirks = s->sc->quirks;
-
- s->io_ops = &sdhci_mmio_le_ops;
}
void sdhci_uninitfn(SDHCIState *s)
@@ -1447,6 +1445,7 @@ void sdhci_common_realize(SDHCIState *s, Error **errp)
SDHCIClass *sc = s->sc;
const char *class_name = object_get_typename(OBJECT(s));
+ s->io_ops = sc->io_ops ?: &sdhci_mmio_le_ops;
switch (s->endianness) {
case DEVICE_LITTLE_ENDIAN:
/* s->io_ops is little endian by default */
@@ -1890,17 +1889,11 @@ static const MemoryRegionOps usdhc_mmio_ops = {
.endianness = DEVICE_LITTLE_ENDIAN,
};
-static void imx_usdhc_init(Object *obj)
-{
- SDHCIState *s = SYSBUS_SDHCI(obj);
-
- s->io_ops = &usdhc_mmio_ops;
-}
-
static void imx_usdhc_class_init(ObjectClass *oc, void *data)
{
SDHCIClass *sc = SYSBUS_SDHCI_CLASS(oc);
+ sc->io_ops = &usdhc_mmio_ops;
sc->quirks = BIT(SDHCI_QUIRK_NO_BUSY_IRQ);
sdhci_common_class_init(oc, data);
@@ -1957,11 +1950,13 @@ static const MemoryRegionOps sdhci_s3c_mmio_ops = {
.endianness = DEVICE_LITTLE_ENDIAN,
};
-static void sdhci_s3c_init(Object *obj)
+static void sdhci_s3c_class_init(ObjectClass *oc, void *data)
{
- SDHCIState *s = SYSBUS_SDHCI(obj);
+ SDHCIClass *sc = SYSBUS_SDHCI_CLASS(oc);
- s->io_ops = &sdhci_s3c_mmio_ops;
+ sc->io_ops = &sdhci_s3c_mmio_ops;
+
+ sdhci_common_class_init(oc, data);
}
static const TypeInfo sdhci_types[] = {
@@ -1983,13 +1978,12 @@ static const TypeInfo sdhci_types[] = {
{
.name = TYPE_IMX_USDHC,
.parent = TYPE_SYSBUS_SDHCI,
- .instance_init = imx_usdhc_init,
.class_init = imx_usdhc_class_init,
},
{
.name = TYPE_S3C_SDHCI,
.parent = TYPE_SYSBUS_SDHCI,
- .instance_init = sdhci_s3c_init,
+ .class_init = sdhci_s3c_class_init,
},
};
--
2.47.1
next prev parent reply other threads:[~2025-03-10 0:09 UTC|newest]
Thread overview: 30+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-03-10 0:06 [PATCH v5 00/14] hw/sd/sdhci: Set reset value of interrupt registers Philippe Mathieu-Daudé
2025-03-10 0:06 ` [PATCH v5 01/14] hw/qdev-properties-system: Include missing 'qapi/qapi-types-common.h' Philippe Mathieu-Daudé
2025-03-11 10:56 ` Philippe Mathieu-Daudé
2025-03-10 0:06 ` [PATCH v5 02/14] hw/sd/sdhci: Remove need for SDHCIState::vendor field Philippe Mathieu-Daudé
2025-03-10 0:06 ` [PATCH v5 03/14] hw/sd/sdhci: Redefine SDHCI_QUIRK_NO_BUSY_IRQ bitmask as bit Philippe Mathieu-Daudé
2025-03-10 13:31 ` BALATON Zoltan
2025-03-10 0:06 ` [PATCH v5 04/14] hw/sd/sdhci: Include 'wp-inverted' property in quirk bitmask Philippe Mathieu-Daudé
2025-03-10 13:36 ` BALATON Zoltan
2025-03-10 0:06 ` [PATCH v5 05/14] hw/sd/sdhci: Include 'pending-insert-quirk' " Philippe Mathieu-Daudé
2025-03-10 13:39 ` BALATON Zoltan
2025-03-10 0:06 ` [PATCH v5 06/14] hw/sd/sdhci: Introduce SDHCIClass stub Philippe Mathieu-Daudé
2025-03-10 0:06 ` [PATCH v5 07/14] hw/sd/sdhci: Make quirks a class property Philippe Mathieu-Daudé
2025-03-10 0:06 ` [PATCH v5 08/14] hw/sd/sdhci: Make I/O region size " Philippe Mathieu-Daudé
2025-03-10 0:06 ` Philippe Mathieu-Daudé [this message]
2025-03-10 13:50 ` [PATCH v5 09/14] hw/sd/sdhci: Allow SDHCI classes to register their own MemoryRegionOps BALATON Zoltan
2025-03-10 0:06 ` [PATCH v5 10/14] hw/sd/sdhci: Allow SDHCI classes to register their own read-only regs Philippe Mathieu-Daudé
2025-03-10 0:06 ` [PATCH v5 11/14] hw/sd/sdhci: Allow SDHCI classes to have different register reset values Philippe Mathieu-Daudé
2025-03-10 0:06 ` [PATCH v5 12/14] hw/sd/sdhci: Implement Freescale eSDHC as TYPE_FSL_ESDHC Philippe Mathieu-Daudé
2025-03-10 0:06 ` [PATCH v5 13/14] hw/ppc/e500: Replace generic SDHCI by Freescale eSDHC Philippe Mathieu-Daudé
2025-03-10 0:06 ` [PATCH v5 14/14] hw/sd/sdhci: Remove unnecessary 'endianness' property Philippe Mathieu-Daudé
2025-03-10 14:09 ` BALATON Zoltan
2025-03-10 15:27 ` Philippe Mathieu-Daudé
2025-03-10 15:56 ` Guenter Roeck
2025-03-10 17:31 ` Philippe Mathieu-Daudé
2025-03-10 17:38 ` Bernhard Beschow
2025-03-10 18:24 ` Cédric Le Goater
2025-03-10 18:34 ` Philippe Mathieu-Daudé
2025-03-10 22:30 ` Guenter Roeck
2025-03-11 7:31 ` Bernhard Beschow
2025-03-11 7:59 ` Philippe Mathieu-Daudé
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