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From: "Philippe Mathieu-Daudé" <philmd@linaro.org>
To: BALATON Zoltan <balaton@eik.bme.hu>, qemu-devel@nongnu.org
Cc: "Steven Lee" <steven_lee@aspeedtech.com>,
	"Joel Stanley" <joel@jms.id.au>,
	"Bernhard Beschow" <shentey@gmail.com>,
	"Peter Maydell" <peter.maydell@linaro.org>,
	qemu-arm@nongnu.org, "Andrey Smirnov" <andrew.smirnov@gmail.com>,
	"Paolo Bonzini" <pbonzini@redhat.com>,
	"Bin Meng" <bmeng.cn@gmail.com>,
	"Cédric Le Goater" <clg@kaod.org>,
	"Eduardo Habkost" <eduardo@habkost.net>,
	qemu-ppc@nongnu.org, "Daniel P. Berrangé" <berrange@redhat.com>,
	"Guenter Roeck" <linux@roeck-us.net>,
	"Andrew Jeffery" <andrew@codeconstruct.com.au>,
	"Troy Lee" <leetroy@gmail.com>,
	"Jean-Christophe Dubois" <jcd@tribudubois.net>,
	"Philippe Mathieu-Daudé" <philmd@linaro.org>,
	qemu-block@nongnu.org, "Jamin Lin" <jamin_lin@aspeedtech.com>
Subject: [PATCH v5 10/14] hw/sd/sdhci: Allow SDHCI classes to register their own read-only regs
Date: Mon, 10 Mar 2025 01:06:16 +0100	[thread overview]
Message-ID: <20250310000620.70120-11-philmd@linaro.org> (raw)
In-Reply-To: <20250310000620.70120-1-philmd@linaro.org>

Some registers are read-only.

Since we allow instances to clear/set extra bits of capareg,
log when read-only bits normally set by hardware are cleared
at board level.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
 include/hw/sd/sdhci.h |  7 +++++++
 hw/sd/sdhci.c         | 10 +++++++++-
 2 files changed, 16 insertions(+), 1 deletion(-)

diff --git a/include/hw/sd/sdhci.h b/include/hw/sd/sdhci.h
index 108bc1993c6..eb21b64f932 100644
--- a/include/hw/sd/sdhci.h
+++ b/include/hw/sd/sdhci.h
@@ -120,6 +120,13 @@ struct SDHCIClass {
     const MemoryRegionOps *io_ops;
     uint32_t quirks;
     uint64_t iomem_size;
+
+    /* Read-only registers */
+    struct {
+        uint64_t capareg;
+        uint64_t maxcurr;
+        uint16_t version;
+    } ro;
 };
 
 /*
diff --git a/hw/sd/sdhci.c b/hw/sd/sdhci.c
index 6868bf68285..eb6a0e0f939 100644
--- a/hw/sd/sdhci.c
+++ b/hw/sd/sdhci.c
@@ -73,6 +73,7 @@ static bool sdhci_check_capab_freq_range(SDHCIState *s, const char *desc,
 
 static void sdhci_check_capareg(SDHCIState *s, Error **errp)
 {
+    SDHCIClass *sc = s->sc;
     uint64_t msk = s->capareg;
     uint32_t val;
     bool y;
@@ -208,6 +209,11 @@ static void sdhci_check_capareg(SDHCIState *s, Error **errp)
         qemu_log_mask(LOG_UNIMP,
                       "SDHCI: unknown CAPAB mask: 0x%016" PRIx64 "\n", msk);
     }
+    msk = sc->ro.capareg & ~s->capareg;
+    if (msk) {
+        qemu_log_mask(LOG_UNIMP,
+                      "SDHCI: ignored CAPAB mask: 0x%016" PRIx64 "\n", msk);
+    }
 }
 
 static uint8_t sdhci_slotint(SDHCIState *s)
@@ -1407,7 +1413,9 @@ static void sdhci_init_readonly_registers(SDHCIState *s, Error **errp)
         error_setg(errp, "Only Spec v2/v3 are supported");
         return;
     }
-    s->version = (SDHC_HCVER_VENDOR << 8) | (s->sd_spec_version - 1);
+    s->version = s->sc->ro.version
+                 ?: (SDHC_HCVER_VENDOR << 8) | (s->sd_spec_version - 1);
+    s->maxcurr = s->sc->ro.maxcurr;
 
     sdhci_check_capareg(s, errp);
     if (*errp) {
-- 
2.47.1



  parent reply	other threads:[~2025-03-10  0:11 UTC|newest]

Thread overview: 30+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-03-10  0:06 [PATCH v5 00/14] hw/sd/sdhci: Set reset value of interrupt registers Philippe Mathieu-Daudé
2025-03-10  0:06 ` [PATCH v5 01/14] hw/qdev-properties-system: Include missing 'qapi/qapi-types-common.h' Philippe Mathieu-Daudé
2025-03-11 10:56   ` Philippe Mathieu-Daudé
2025-03-10  0:06 ` [PATCH v5 02/14] hw/sd/sdhci: Remove need for SDHCIState::vendor field Philippe Mathieu-Daudé
2025-03-10  0:06 ` [PATCH v5 03/14] hw/sd/sdhci: Redefine SDHCI_QUIRK_NO_BUSY_IRQ bitmask as bit Philippe Mathieu-Daudé
2025-03-10 13:31   ` BALATON Zoltan
2025-03-10  0:06 ` [PATCH v5 04/14] hw/sd/sdhci: Include 'wp-inverted' property in quirk bitmask Philippe Mathieu-Daudé
2025-03-10 13:36   ` BALATON Zoltan
2025-03-10  0:06 ` [PATCH v5 05/14] hw/sd/sdhci: Include 'pending-insert-quirk' " Philippe Mathieu-Daudé
2025-03-10 13:39   ` BALATON Zoltan
2025-03-10  0:06 ` [PATCH v5 06/14] hw/sd/sdhci: Introduce SDHCIClass stub Philippe Mathieu-Daudé
2025-03-10  0:06 ` [PATCH v5 07/14] hw/sd/sdhci: Make quirks a class property Philippe Mathieu-Daudé
2025-03-10  0:06 ` [PATCH v5 08/14] hw/sd/sdhci: Make I/O region size " Philippe Mathieu-Daudé
2025-03-10  0:06 ` [PATCH v5 09/14] hw/sd/sdhci: Allow SDHCI classes to register their own MemoryRegionOps Philippe Mathieu-Daudé
2025-03-10 13:50   ` BALATON Zoltan
2025-03-10  0:06 ` Philippe Mathieu-Daudé [this message]
2025-03-10  0:06 ` [PATCH v5 11/14] hw/sd/sdhci: Allow SDHCI classes to have different register reset values Philippe Mathieu-Daudé
2025-03-10  0:06 ` [PATCH v5 12/14] hw/sd/sdhci: Implement Freescale eSDHC as TYPE_FSL_ESDHC Philippe Mathieu-Daudé
2025-03-10  0:06 ` [PATCH v5 13/14] hw/ppc/e500: Replace generic SDHCI by Freescale eSDHC Philippe Mathieu-Daudé
2025-03-10  0:06 ` [PATCH v5 14/14] hw/sd/sdhci: Remove unnecessary 'endianness' property Philippe Mathieu-Daudé
2025-03-10 14:09   ` BALATON Zoltan
2025-03-10 15:27     ` Philippe Mathieu-Daudé
2025-03-10 15:56       ` Guenter Roeck
2025-03-10 17:31         ` Philippe Mathieu-Daudé
2025-03-10 17:38           ` Bernhard Beschow
2025-03-10 18:24             ` Cédric Le Goater
2025-03-10 18:34               ` Philippe Mathieu-Daudé
2025-03-10 22:30           ` Guenter Roeck
2025-03-11  7:31   ` Bernhard Beschow
2025-03-11  7:59     ` Philippe Mathieu-Daudé

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