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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3912bfb7aefsm13011423f8f.20.2025.03.09.17.07.14 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Sun, 09 Mar 2025 17:07:15 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: BALATON Zoltan , qemu-devel@nongnu.org Cc: Steven Lee , Joel Stanley , Bernhard Beschow , Peter Maydell , qemu-arm@nongnu.org, Andrey Smirnov , Paolo Bonzini , Bin Meng , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Eduardo Habkost , qemu-ppc@nongnu.org, =?UTF-8?q?Daniel=20P=2E=20Berrang=C3=A9?= , Guenter Roeck , Andrew Jeffery , Troy Lee , Jean-Christophe Dubois , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , qemu-block@nongnu.org, Jamin Lin Subject: [PATCH v5 10/14] hw/sd/sdhci: Allow SDHCI classes to register their own read-only regs Date: Mon, 10 Mar 2025 01:06:16 +0100 Message-ID: <20250310000620.70120-11-philmd@linaro.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250310000620.70120-1-philmd@linaro.org> References: <20250310000620.70120-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::42f; envelope-from=philmd@linaro.org; helo=mail-wr1-x42f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Some registers are read-only. Since we allow instances to clear/set extra bits of capareg, log when read-only bits normally set by hardware are cleared at board level. Signed-off-by: Philippe Mathieu-Daudé --- include/hw/sd/sdhci.h | 7 +++++++ hw/sd/sdhci.c | 10 +++++++++- 2 files changed, 16 insertions(+), 1 deletion(-) diff --git a/include/hw/sd/sdhci.h b/include/hw/sd/sdhci.h index 108bc1993c6..eb21b64f932 100644 --- a/include/hw/sd/sdhci.h +++ b/include/hw/sd/sdhci.h @@ -120,6 +120,13 @@ struct SDHCIClass { const MemoryRegionOps *io_ops; uint32_t quirks; uint64_t iomem_size; + + /* Read-only registers */ + struct { + uint64_t capareg; + uint64_t maxcurr; + uint16_t version; + } ro; }; /* diff --git a/hw/sd/sdhci.c b/hw/sd/sdhci.c index 6868bf68285..eb6a0e0f939 100644 --- a/hw/sd/sdhci.c +++ b/hw/sd/sdhci.c @@ -73,6 +73,7 @@ static bool sdhci_check_capab_freq_range(SDHCIState *s, const char *desc, static void sdhci_check_capareg(SDHCIState *s, Error **errp) { + SDHCIClass *sc = s->sc; uint64_t msk = s->capareg; uint32_t val; bool y; @@ -208,6 +209,11 @@ static void sdhci_check_capareg(SDHCIState *s, Error **errp) qemu_log_mask(LOG_UNIMP, "SDHCI: unknown CAPAB mask: 0x%016" PRIx64 "\n", msk); } + msk = sc->ro.capareg & ~s->capareg; + if (msk) { + qemu_log_mask(LOG_UNIMP, + "SDHCI: ignored CAPAB mask: 0x%016" PRIx64 "\n", msk); + } } static uint8_t sdhci_slotint(SDHCIState *s) @@ -1407,7 +1413,9 @@ static void sdhci_init_readonly_registers(SDHCIState *s, Error **errp) error_setg(errp, "Only Spec v2/v3 are supported"); return; } - s->version = (SDHC_HCVER_VENDOR << 8) | (s->sd_spec_version - 1); + s->version = s->sc->ro.version + ?: (SDHC_HCVER_VENDOR << 8) | (s->sd_spec_version - 1); + s->maxcurr = s->sc->ro.maxcurr; sdhci_check_capareg(s, errp); if (*errp) { -- 2.47.1