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From: "Philippe Mathieu-Daudé" <philmd@linaro.org>
To: qemu-devel@nongnu.org
Cc: "Peter Maydell" <peter.maydell@linaro.org>,
	"Marc-André Lureau" <marcandre.lureau@redhat.com>,
	"Alex Bennée" <alex.bennee@linaro.org>,
	"Mark Cave-Ayland" <mark.cave-ayland@ilande.co.uk>,
	qemu-arm@nongnu.org, "Paolo Bonzini" <pbonzini@redhat.com>,
	"Philippe Mathieu-Daudé" <philmd@linaro.org>
Subject: [PATCH v7 4/7] hw/char/pl011: Trace FIFO enablement
Date: Mon, 10 Mar 2025 02:28:22 +0100	[thread overview]
Message-ID: <20250310012825.79614-5-philmd@linaro.org> (raw)
In-Reply-To: <20250310012825.79614-1-philmd@linaro.org>

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/char/pl011.c      | 3 ++-
 hw/char/trace-events | 1 +
 2 files changed, 3 insertions(+), 1 deletion(-)

diff --git a/hw/char/pl011.c b/hw/char/pl011.c
index 18ea03a52f4..34a5cb3af5d 100644
--- a/hw/char/pl011.c
+++ b/hw/char/pl011.c
@@ -480,8 +480,9 @@ static void pl011_write(void *opaque, hwaddr offset,
         pl011_trace_baudrate_change(s);
         break;
     case 11: /* UARTLCR_H */
-        /* Reset the FIFO state on FIFO enable or disable */
         if ((s->lcr ^ value) & LCR_FEN) {
+            /* Reset the FIFO state on FIFO enable or disable */
+            trace_pl011_fifo_enable(value & LCR_FEN);
             pl011_reset_rx_fifo(s);
             pl011_reset_tx_fifo(s);
         }
diff --git a/hw/char/trace-events b/hw/char/trace-events
index 1bab98fb5f3..c857f4c4b38 100644
--- a/hw/char/trace-events
+++ b/hw/char/trace-events
@@ -63,6 +63,7 @@ pl011_read(uint32_t addr, uint32_t value, const char *regname) "addr 0x%03x valu
 pl011_read_fifo(unsigned rx_fifo_used, size_t rx_fifo_depth) "RX FIFO read, used %u/%zu"
 pl011_write(uint32_t addr, uint32_t value, const char *regname) "addr 0x%03x value 0x%08x reg %s"
 pl011_can_receive(uint32_t lcr, unsigned rx_fifo_used, size_t rx_fifo_depth, unsigned rx_fifo_available) "LCR 0x%02x, RX FIFO used %u/%zu, can_receive %u chars"
+pl011_fifo_enable(bool enable) "enable:%u"
 pl011_fifo_rx_put(uint32_t c, unsigned read_count, size_t rx_fifo_depth) "RX FIFO push char [0x%02x] %d/%zu depth used"
 pl011_fifo_rx_full(void) "RX FIFO now full, RXFF set"
 pl011_fifo_tx_put(uint8_t byte) "TX FIFO push char [0x%02x]"
-- 
2.47.1



  parent reply	other threads:[~2025-03-10  1:30 UTC|newest]

Thread overview: 12+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-03-10  1:28 [PATCH v7 0/7] hw/char/pl011: Implement TX (async) FIFO to avoid blocking the main loop Philippe Mathieu-Daudé
2025-03-10  1:28 ` [PATCH v7 1/7] hw/char/pl011: Add transmit FIFO to PL011State Philippe Mathieu-Daudé
2025-03-10  1:28 ` [PATCH v7 2/7] hw/char/pl011: Introduce pl011_xmit() Philippe Mathieu-Daudé
2025-03-10  1:28 ` [PATCH v7 3/7] hw/char/pl011: Factor pl011_xmit_cb() out as GSource Philippe Mathieu-Daudé
2025-03-10  1:28 ` Philippe Mathieu-Daudé [this message]
2025-03-10  1:28 ` [PATCH v7 5/7] hw/char/pl011: Consider TX FIFO overrun error Philippe Mathieu-Daudé
2025-03-10  1:28 ` [PATCH v7 6/7] hw/char/pl011: Drain TX FIFO when no backend connected Philippe Mathieu-Daudé
2025-03-10  1:28 ` [PATCH v7 7/7] hw/char/pl011: Implement TX FIFO Philippe Mathieu-Daudé
2025-03-10 14:42 ` [PATCH v7 0/7] hw/char/pl011: Implement TX (async) FIFO to avoid blocking the main loop Peter Maydell
2025-03-10 17:28   ` Peter Maydell
2025-03-11 10:33     ` Philippe Mathieu-Daudé
2025-03-11 18:36       ` Peter Maydell

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