From: "Philippe Mathieu-Daudé" <philmd@linaro.org>
To: qemu-devel@nongnu.org
Cc: "Peter Maydell" <peter.maydell@linaro.org>,
"Marc-André Lureau" <marcandre.lureau@redhat.com>,
"Alex Bennée" <alex.bennee@linaro.org>,
"Mark Cave-Ayland" <mark.cave-ayland@ilande.co.uk>,
qemu-arm@nongnu.org, "Paolo Bonzini" <pbonzini@redhat.com>,
"Philippe Mathieu-Daudé" <philmd@linaro.org>
Subject: [PATCH v7 5/7] hw/char/pl011: Consider TX FIFO overrun error
Date: Mon, 10 Mar 2025 02:28:23 +0100 [thread overview]
Message-ID: <20250310012825.79614-6-philmd@linaro.org> (raw)
In-Reply-To: <20250310012825.79614-1-philmd@linaro.org>
When transmission is disabled, characters are still queued
to the FIFO which eventually overruns. Report that error
condition in the status register.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
---
hw/char/pl011.c | 22 ++++++++++++++++++++++
hw/char/trace-events | 2 ++
2 files changed, 24 insertions(+)
diff --git a/hw/char/pl011.c b/hw/char/pl011.c
index 34a5cb3af5d..f67ce951ac9 100644
--- a/hw/char/pl011.c
+++ b/hw/char/pl011.c
@@ -61,6 +61,9 @@ DeviceState *pl011_create(hwaddr addr, qemu_irq irq, Chardev *chr)
/* Data Register, UARTDR */
#define DR_BE (1 << 10)
+/* Receive Status Register/Error Clear Register, UARTRSR/UARTECR */
+#define RSR_OE (1 << 3)
+
/* Interrupt status bits in UARTRIS, UARTMIS, UARTIMSC */
#define INT_OE (1 << 10)
#define INT_BE (1 << 9)
@@ -157,6 +160,18 @@ static inline unsigned pl011_get_fifo_depth(PL011State *s)
return pl011_is_fifo_enabled(s) ? PL011_FIFO_DEPTH : 1;
}
+static bool pl011_is_tx_fifo_full(PL011State *s)
+{
+ bool fifo_enabled = pl011_is_fifo_enabled(s);
+ bool tx_fifo_full = fifo_enabled
+ ? fifo8_is_full(&s->xmit_fifo)
+ : !fifo8_is_empty(&s->xmit_fifo);
+
+ trace_pl011_fifo_tx_is_full(fifo_enabled ? "FIFO" : "CHAR", tx_fifo_full);
+
+ return tx_fifo_full;
+}
+
static inline void pl011_reset_rx_fifo(PL011State *s)
{
s->read_count = 0;
@@ -275,6 +290,13 @@ static void pl011_write_txdata(PL011State *s, uint8_t data)
"PL011 data written to disabled TX UART\n");
}
+ if (pl011_is_tx_fifo_full(s)) {
+ /* The FIFO is already full. Content remains valid. */
+ trace_pl011_fifo_tx_overrun();
+ s->rsr |= RSR_OE;
+ return;
+ }
+
trace_pl011_fifo_tx_put(data);
pl011_loopback_tx(s, data);
fifo8_push(&s->xmit_fifo, data);
diff --git a/hw/char/trace-events b/hw/char/trace-events
index c857f4c4b38..d52f511a1e2 100644
--- a/hw/char/trace-events
+++ b/hw/char/trace-events
@@ -66,9 +66,11 @@ pl011_can_receive(uint32_t lcr, unsigned rx_fifo_used, size_t rx_fifo_depth, uns
pl011_fifo_enable(bool enable) "enable:%u"
pl011_fifo_rx_put(uint32_t c, unsigned read_count, size_t rx_fifo_depth) "RX FIFO push char [0x%02x] %d/%zu depth used"
pl011_fifo_rx_full(void) "RX FIFO now full, RXFF set"
+pl011_fifo_tx_is_full(const char *desc, bool full) "mode:%s full:%u"
pl011_fifo_tx_put(uint8_t byte) "TX FIFO push char [0x%02x]"
pl011_fifo_tx_xmit_used(unsigned sent) "TX FIFO used %u chars"
pl011_fifo_tx_xmit_consumed(unsigned sent) "TX FIFO consumed %u chars"
+pl011_fifo_tx_overrun(void) "TX FIFO overrun"
pl011_baudrate_change(unsigned int baudrate, uint64_t clock, uint32_t ibrd, uint32_t fbrd) "new baudrate %u (clk: %" PRIu64 "hz, ibrd: %" PRIu32 ", fbrd: %" PRIu32 ")"
pl011_receive(int size) "recv %d chars"
--
2.47.1
next prev parent reply other threads:[~2025-03-10 1:30 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-03-10 1:28 [PATCH v7 0/7] hw/char/pl011: Implement TX (async) FIFO to avoid blocking the main loop Philippe Mathieu-Daudé
2025-03-10 1:28 ` [PATCH v7 1/7] hw/char/pl011: Add transmit FIFO to PL011State Philippe Mathieu-Daudé
2025-03-10 1:28 ` [PATCH v7 2/7] hw/char/pl011: Introduce pl011_xmit() Philippe Mathieu-Daudé
2025-03-10 1:28 ` [PATCH v7 3/7] hw/char/pl011: Factor pl011_xmit_cb() out as GSource Philippe Mathieu-Daudé
2025-03-10 1:28 ` [PATCH v7 4/7] hw/char/pl011: Trace FIFO enablement Philippe Mathieu-Daudé
2025-03-10 1:28 ` Philippe Mathieu-Daudé [this message]
2025-03-10 1:28 ` [PATCH v7 6/7] hw/char/pl011: Drain TX FIFO when no backend connected Philippe Mathieu-Daudé
2025-03-10 1:28 ` [PATCH v7 7/7] hw/char/pl011: Implement TX FIFO Philippe Mathieu-Daudé
2025-03-10 14:42 ` [PATCH v7 0/7] hw/char/pl011: Implement TX (async) FIFO to avoid blocking the main loop Peter Maydell
2025-03-10 17:28 ` Peter Maydell
2025-03-11 10:33 ` Philippe Mathieu-Daudé
2025-03-11 18:36 ` Peter Maydell
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