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From: Nicholas Piggin <npiggin@gmail.com>
To: qemu-devel@nongnu.org
Cc: Nicholas Piggin <npiggin@gmail.com>,
	qemu-ppc@nongnu.org, Michael Kowal <kowal@linux.ibm.com>
Subject: [PULL 24/72] ppc/xive: Rename ipb_to_pipr() to xive_ipb_to_pipr()
Date: Tue, 11 Mar 2025 22:57:18 +1000	[thread overview]
Message-ID: <20250311125815.903177-25-npiggin@gmail.com> (raw)
In-Reply-To: <20250311125815.903177-1-npiggin@gmail.com>

From: Michael Kowal <kowal@linux.ibm.com>

Rename to follow the convention of the other function names.

Signed-off-by: Michael Kowal <kowal@linux.ibm.com>
Reviewed-by: Nicholas Piggin <npiggin@gmail.com>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
---
 hw/intc/xive.c        | 22 ++++++----------------
 include/hw/ppc/xive.h | 16 ++++++++++++----
 2 files changed, 18 insertions(+), 20 deletions(-)

diff --git a/hw/intc/xive.c b/hw/intc/xive.c
index 139cfdf9bf..f603d9f1a5 100644
--- a/hw/intc/xive.c
+++ b/hw/intc/xive.c
@@ -3,8 +3,7 @@
  *
  * Copyright (c) 2017-2018, IBM Corporation.
  *
- * This code is licensed under the GPL version 2 or later. See the
- * COPYING file in the top-level directory.
+ * SPDX-License-Identifier: GPL-2.0-or-later
  */
 
 #include "qemu/osdep.h"
@@ -27,15 +26,6 @@
  * XIVE Thread Interrupt Management context
  */
 
-/*
- * Convert an Interrupt Pending Buffer (IPB) register to a Pending
- * Interrupt Priority Register (PIPR), which contains the priority of
- * the most favored pending notification.
- */
-static uint8_t ipb_to_pipr(uint8_t ibp)
-{
-    return ibp ? clz32((uint32_t)ibp << 24) : 0xff;
-}
 
 static uint8_t exception_mask(uint8_t ring)
 {
@@ -159,7 +149,7 @@ static void xive_tctx_set_cppr(XiveTCTX *tctx, uint8_t ring, uint8_t cppr)
      * Recompute the PIPR based on local pending interrupts.  The PHYS
      * ring must take the minimum of both the PHYS and POOL PIPR values.
      */
-    pipr_min = ipb_to_pipr(regs[TM_IPB]);
+    pipr_min = xive_ipb_to_pipr(regs[TM_IPB]);
     ring_min = ring;
 
     /* PHYS updates also depend on POOL values */
@@ -169,7 +159,7 @@ static void xive_tctx_set_cppr(XiveTCTX *tctx, uint8_t ring, uint8_t cppr)
         /* POOL values only matter if POOL ctx is valid */
         if (pool_regs[TM_WORD2] & 0x80) {
 
-            uint8_t pool_pipr = ipb_to_pipr(pool_regs[TM_IPB]);
+            uint8_t pool_pipr = xive_ipb_to_pipr(pool_regs[TM_IPB]);
 
             /*
              * Determine highest priority interrupt and
@@ -193,7 +183,7 @@ void xive_tctx_ipb_update(XiveTCTX *tctx, uint8_t ring, uint8_t ipb)
     uint8_t *regs = &tctx->regs[ring];
 
     regs[TM_IPB] |= ipb;
-    regs[TM_PIPR] = ipb_to_pipr(regs[TM_IPB]);
+    regs[TM_PIPR] = xive_ipb_to_pipr(regs[TM_IPB]);
     xive_tctx_notify(tctx, ring);
 }
 
@@ -841,9 +831,9 @@ void xive_tctx_reset(XiveTCTX *tctx)
      * CPPR is first set.
      */
     tctx->regs[TM_QW1_OS + TM_PIPR] =
-        ipb_to_pipr(tctx->regs[TM_QW1_OS + TM_IPB]);
+        xive_ipb_to_pipr(tctx->regs[TM_QW1_OS + TM_IPB]);
     tctx->regs[TM_QW3_HV_PHYS + TM_PIPR] =
-        ipb_to_pipr(tctx->regs[TM_QW3_HV_PHYS + TM_IPB]);
+        xive_ipb_to_pipr(tctx->regs[TM_QW3_HV_PHYS + TM_IPB]);
 }
 
 static void xive_tctx_realize(DeviceState *dev, Error **errp)
diff --git a/include/hw/ppc/xive.h b/include/hw/ppc/xive.h
index ea5d03a346..75276b9ba6 100644
--- a/include/hw/ppc/xive.h
+++ b/include/hw/ppc/xive.h
@@ -130,11 +130,9 @@
  *   TCTX   Thread interrupt Context
  *
  *
- * Copyright (c) 2017-2018, IBM Corporation.
- *
- * This code is licensed under the GPL version 2 or later. See the
- * COPYING file in the top-level directory.
+ * Copyright (c) 2017-2024, IBM Corporation.
  *
+ * SPDX-License-Identifier: GPL-2.0-or-later
  */
 
 #ifndef PPC_XIVE_H
@@ -510,6 +508,16 @@ static inline uint8_t xive_priority_to_ipb(uint8_t priority)
         0 : 1 << (XIVE_PRIORITY_MAX - priority);
 }
 
+/*
+ * Convert an Interrupt Pending Buffer (IPB) register to a Pending
+ * Interrupt Priority Register (PIPR), which contains the priority of
+ * the most favored pending notification.
+ */
+static inline uint8_t xive_ipb_to_pipr(uint8_t ibp)
+{
+    return ibp ? clz32((uint32_t)ibp << 24) : 0xff;
+}
+
 /*
  * XIVE Thread Interrupt Management Aera (TIMA)
  *
-- 
2.47.1



  parent reply	other threads:[~2025-03-11 13:12 UTC|newest]

Thread overview: 83+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-03-11 12:56 [PULL 00/72] ppc-for-10.0-1 queue Nicholas Piggin
2025-03-11 12:56 ` [PULL 01/72] ppc/ppc405: Remove tests Nicholas Piggin
2025-03-11 12:56 ` [PULL 02/72] ppc/ppc405: Remove boards Nicholas Piggin
2025-03-11 12:56 ` [PULL 03/72] hw/ppc: Deprecate 405 CPUs Nicholas Piggin
2025-03-11 12:56 ` [PULL 04/72] ppc/pnv: Update skiboot to 7.1-106 Nicholas Piggin
2025-03-11 12:56 ` [PULL 05/72] pseries: Update SLOF firmware image Nicholas Piggin
2025-03-11 12:57 ` [PULL 06/72] ppc/pnv/phb4: Add pervasive chiplet support to PHB4/5 Nicholas Piggin
2025-03-11 12:57 ` [PULL 07/72] ppc/pnv/homer: Fix OCC registers Nicholas Piggin
2025-03-11 12:57 ` [PULL 08/72] ppc/pnv/homer: Make dummy reads return 0 Nicholas Piggin
2025-03-11 12:57 ` [PULL 09/72] ppc/pnv/occ: Fix common area sensor offsets Nicholas Piggin
2025-03-13  7:57   ` Michael Tokarev
2025-03-11 12:57 ` [PULL 10/72] ppc/pnv/homer: class-based base and size Nicholas Piggin
2025-03-11 12:57 ` [PULL 11/72] ppc/pnv/occ: Better document OCCMISC bits Nicholas Piggin
2025-03-11 12:57 ` [PULL 12/72] ppc/pnv: Make HOMER memory a RAM region Nicholas Piggin
2025-03-11 12:57 ` [PULL 13/72] ppc/pnv/occ: Update pstate frequency tables Nicholas Piggin
2025-03-11 12:57 ` [PULL 14/72] ppc/pnv/occ: Add POWER10 OCC-OPAL data format Nicholas Piggin
2025-03-11 12:57 ` [PULL 15/72] ppc/pnv/occ: Implement a basic dynamic OCC model Nicholas Piggin
2025-03-11 12:57 ` [PULL 16/72] target/ppc: Add Power9/10 power management SPRs Nicholas Piggin
2025-03-11 12:57 ` [PULL 17/72] ppc/pnv: Support LPC host controller irqs other than serirqs Nicholas Piggin
2025-03-11 12:57 ` [PULL 18/72] ppc/pnv: raise no-response errors if an LPC transaction fails Nicholas Piggin
2025-03-11 12:57 ` [PULL 19/72] ppc/pnv: Implement LPC FW address space IDSEL Nicholas Piggin
2025-03-11 12:57 ` [PULL 20/72] ppc/pnv: Move PNOR to offset 0 in the ISA FW space Nicholas Piggin
2025-03-11 12:57 ` [PULL 21/72] ppc/pnv: Add a PNOR address and size sanity checks Nicholas Piggin
2025-03-11 12:57 ` [PULL 22/72] ppc/pnv: Add a default formatted PNOR image Nicholas Piggin
2025-03-11 12:57 ` [PULL 23/72] ppc/xive2: Update NVP save/restore for group attributes Nicholas Piggin
2025-03-11 12:57 ` Nicholas Piggin [this message]
2025-03-11 12:57 ` [PULL 25/72] ppc/xive2: Add grouping level to notification Nicholas Piggin
2025-03-11 12:57 ` [PULL 26/72] ppc/xive2: Support group-matching when looking for target Nicholas Piggin
2025-03-11 12:57 ` [PULL 27/72] ppc/xive2: Add undelivered group interrupt to backlog Nicholas Piggin
2025-03-11 12:57 ` [PULL 28/72] ppc/xive2: Process group backlog when pushing an OS context Nicholas Piggin
2025-03-11 12:57 ` [PULL 29/72] ppc/xive2: Process group backlog when updating the CPPR Nicholas Piggin
2025-03-11 12:57 ` [PULL 30/72] qtest/xive: Add group-interrupt test Nicholas Piggin
2025-03-11 12:57 ` [PULL 31/72] ppc/xive2: Add support for MMIO operations on the NVPG/NVC BAR Nicholas Piggin
2025-03-11 12:57 ` [PULL 32/72] ppc/xive2: Support crowd-matching when looking for target Nicholas Piggin
2025-03-11 12:57 ` [PULL 33/72] pnv/xive2: Rename nvp_ to nvx_ if they can refer to NVP or NVGC Nicholas Piggin
2025-03-11 12:57 ` [PULL 34/72] ppc/xive2: Check crowd backlog when scanning group backlog Nicholas Piggin
2025-03-11 12:57 ` [PULL 35/72] qtest/xive: Change printf to g_test_message Nicholas Piggin
2025-03-11 12:57 ` [PULL 36/72] qtest/xive: Add test of pool interrupts Nicholas Piggin
2025-03-11 12:57 ` [PULL 37/72] hw/ssi/pnv_spi: Replace PnvXferBuffer with Fifo8 structure Nicholas Piggin
2025-03-11 12:57 ` [PULL 38/72] hw/ssi/pnv_spi: Use local var seq_index instead of get_seq_index() Nicholas Piggin
2025-03-11 12:57 ` [PULL 39/72] hw/ssi/pnv_spi: Make bus names distinct for each controllers of a socket Nicholas Piggin
2025-03-11 12:57 ` [PULL 40/72] hw/ssi/pnv_spi: Put a limit to RDR match failures Nicholas Piggin
2025-03-11 12:57 ` [PULL 41/72] hw/ppc/spapr: Restrict CONFER hypercall to TCG Nicholas Piggin
2025-03-11 12:57 ` [PULL 42/72] ppc/pnv: Add new PowerPC Special Purpose Registers (RWMR) Nicholas Piggin
2025-03-11 12:57 ` [PULL 43/72] target/ppc: Make ppc_ldl_code() declaration public Nicholas Piggin
2025-03-11 12:57 ` [PULL 44/72] target/ppc: Move TCG specific exception handlers to tcg-excp_helper.c Nicholas Piggin
2025-03-11 12:57 ` [PULL 45/72] target/ppc: Move ppc_ldl_code() " Nicholas Piggin
2025-03-11 12:57 ` [PULL 46/72] target/ppc: Ensure powerpc_mcheck_checkstop() is only called under TCG Nicholas Piggin
2025-03-11 12:57 ` [PULL 47/72] target/ppc: Restrict powerpc_checkstop() to TCG Nicholas Piggin
2025-03-11 12:57 ` [PULL 48/72] target/ppc: Remove raise_exception_ra() Nicholas Piggin
2025-03-11 12:57 ` [PULL 49/72] target/ppc: Restrict exception helpers to TCG Nicholas Piggin
2025-03-11 12:57 ` [PULL 50/72] target/ppc: Restrict various common " Nicholas Piggin
2025-03-11 12:57 ` [PULL 51/72] target/ppc: Fix style in excp_helper.c Nicholas Piggin
2025-03-11 12:57 ` [PULL 52/72] target/ppc: Make powerpc_excp() prototype public Nicholas Piggin
2025-03-11 12:57 ` [PULL 53/72] target/ppc: Restrict ATTN / SCV / PMINSN helpers to TCG Nicholas Piggin
2025-03-11 12:57 ` [PULL 54/72] hw/ppc/spapr: Convert HPTE() macro as hpte_get_ptr() method Nicholas Piggin
2025-03-11 12:57 ` [PULL 55/72] hw/ppc/spapr: Convert HPTE_VALID() macro as hpte_is_valid() method Nicholas Piggin
2025-03-11 12:57 ` [PULL 56/72] hw/ppc/spapr: Convert HPTE_DIRTY() macro as hpte_is_dirty() method Nicholas Piggin
2025-03-11 12:57 ` [PULL 57/72] hw/ppc/spapr: Convert CLEAN_HPTE() macro as hpte_set_clean() method Nicholas Piggin
2025-03-11 12:57 ` [PULL 58/72] hw/ppc/spapr: Convert DIRTY_HPTE() macro as hpte_set_dirty() method Nicholas Piggin
2025-03-11 12:57 ` [PULL 59/72] hw/ppc/epapr: Do not swap ePAPR magic value Nicholas Piggin
2025-03-11 12:57 ` [PULL 60/72] ppc: Enable 2nd DAWR support on Power10 PowerNV machine Nicholas Piggin
2025-03-11 12:57 ` [PULL 61/72] ppc: spapr: Enable 2nd DAWR on Power10 pSeries machine Nicholas Piggin
2025-03-11 12:57 ` [PULL 62/72] spapr: nested: Add support for reporting Hostwide state counter Nicholas Piggin
2025-03-11 12:57 ` [PULL 63/72] target/ppc: fix timebase register reset state Nicholas Piggin
2025-03-11 12:57 ` [PULL 64/72] target/ppc: Wire up BookE ATB registers for e500 family Nicholas Piggin
2025-03-11 12:57 ` [PULL 65/72] target/ppc: Avoid warning message for zero process table entries Nicholas Piggin
2025-03-11 12:58 ` [PULL 66/72] spapr: Generate random HASHPKEYR for spapr machines Nicholas Piggin
2025-03-11 12:58 ` [PULL 67/72] ppc/amigaone: Simplify replacement dummy_fw Nicholas Piggin
2025-03-11 12:58 ` [PULL 68/72] ppc/amigaone: Implement NVRAM emulation Nicholas Piggin
2025-03-11 12:58 ` [PULL 69/72] ppc/amigaone: Add default environment Nicholas Piggin
2025-03-11 12:58 ` [PULL 70/72] ppc/amigaone: Add kernel and initrd support Nicholas Piggin
2025-06-16 10:07   ` Philippe Mathieu-Daudé
2025-06-16 10:38     ` BALATON Zoltan
2025-03-11 12:58 ` [PULL 71/72] ppc/amigaone: Add #defines for memory map constants Nicholas Piggin
2025-03-11 12:58 ` [PULL 72/72] docs/system/ppc/amigang.rst: Update for NVRAM emulation Nicholas Piggin
2025-03-13  2:34 ` [PULL 00/72] ppc-for-10.0-1 queue Stefan Hajnoczi
2025-03-13  6:13   ` Thomas Huth
2025-03-13 10:49     ` Philippe Mathieu-Daudé
2025-03-14  2:34       ` Nicholas Piggin
2025-03-14  6:19         ` Thomas Huth
2025-03-14  2:41       ` Nicholas Piggin
2025-03-13  7:05 ` Stefan Hajnoczi

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