From: Nicholas Piggin <npiggin@gmail.com>
To: qemu-devel@nongnu.org
Cc: "Nicholas Piggin" <npiggin@gmail.com>,
qemu-ppc@nongnu.org, "Philippe Mathieu-Daudé" <philmd@linaro.org>,
"Harsh Prateek Bora" <harshpb@linux.ibm.com>
Subject: [PULL 50/72] target/ppc: Restrict various common helpers to TCG
Date: Tue, 11 Mar 2025 22:57:44 +1000 [thread overview]
Message-ID: <20250311125815.903177-51-npiggin@gmail.com> (raw)
In-Reply-To: <20250311125815.903177-1-npiggin@gmail.com>
From: Philippe Mathieu-Daudé <philmd@linaro.org>
Move helpers common to system/user emulation to tcg-excp_helper.c.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Harsh Prateek Bora <harshpb@linux.ibm.com>
Message-ID: <20250127102620.39159-12-philmd@linaro.org>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
---
target/ppc/excp_helper.c | 141 ----------------------------------
target/ppc/tcg-excp_helper.c | 143 +++++++++++++++++++++++++++++++++++
2 files changed, 143 insertions(+), 141 deletions(-)
diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c
index 6a12402b23..511e27f726 100644
--- a/target/ppc/excp_helper.c
+++ b/target/ppc/excp_helper.c
@@ -2711,148 +2711,7 @@ void helper_rfmci(CPUPPCState *env)
/* FIXME: choose CSRR1 or MCSRR1 based on cpu type */
do_rfi(env, env->spr[SPR_BOOKE_MCSRR0], env->spr[SPR_BOOKE_MCSRR1]);
}
-#endif /* !CONFIG_USER_ONLY */
-
-void helper_TW(CPUPPCState *env, target_ulong arg1, target_ulong arg2,
- uint32_t flags)
-{
- if (!likely(!(((int32_t)arg1 < (int32_t)arg2 && (flags & 0x10)) ||
- ((int32_t)arg1 > (int32_t)arg2 && (flags & 0x08)) ||
- ((int32_t)arg1 == (int32_t)arg2 && (flags & 0x04)) ||
- ((uint32_t)arg1 < (uint32_t)arg2 && (flags & 0x02)) ||
- ((uint32_t)arg1 > (uint32_t)arg2 && (flags & 0x01))))) {
- raise_exception_err_ra(env, POWERPC_EXCP_PROGRAM,
- POWERPC_EXCP_TRAP, GETPC());
- }
-}
-
-#ifdef TARGET_PPC64
-void helper_TD(CPUPPCState *env, target_ulong arg1, target_ulong arg2,
- uint32_t flags)
-{
- if (!likely(!(((int64_t)arg1 < (int64_t)arg2 && (flags & 0x10)) ||
- ((int64_t)arg1 > (int64_t)arg2 && (flags & 0x08)) ||
- ((int64_t)arg1 == (int64_t)arg2 && (flags & 0x04)) ||
- ((uint64_t)arg1 < (uint64_t)arg2 && (flags & 0x02)) ||
- ((uint64_t)arg1 > (uint64_t)arg2 && (flags & 0x01))))) {
- raise_exception_err_ra(env, POWERPC_EXCP_PROGRAM,
- POWERPC_EXCP_TRAP, GETPC());
- }
-}
-#endif /* TARGET_PPC64 */
-
-static uint32_t helper_SIMON_LIKE_32_64(uint32_t x, uint64_t key, uint32_t lane)
-{
- const uint16_t c = 0xfffc;
- const uint64_t z0 = 0xfa2561cdf44ac398ULL;
- uint16_t z = 0, temp;
- uint16_t k[32], eff_k[32], xleft[33], xright[33], fxleft[32];
-
- for (int i = 3; i >= 0; i--) {
- k[i] = key & 0xffff;
- key >>= 16;
- }
- xleft[0] = x & 0xffff;
- xright[0] = (x >> 16) & 0xffff;
-
- for (int i = 0; i < 28; i++) {
- z = (z0 >> (63 - i)) & 1;
- temp = ror16(k[i + 3], 3) ^ k[i + 1];
- k[i + 4] = c ^ z ^ k[i] ^ temp ^ ror16(temp, 1);
- }
-
- for (int i = 0; i < 8; i++) {
- eff_k[4 * i + 0] = k[4 * i + ((0 + lane) % 4)];
- eff_k[4 * i + 1] = k[4 * i + ((1 + lane) % 4)];
- eff_k[4 * i + 2] = k[4 * i + ((2 + lane) % 4)];
- eff_k[4 * i + 3] = k[4 * i + ((3 + lane) % 4)];
- }
-
- for (int i = 0; i < 32; i++) {
- fxleft[i] = (rol16(xleft[i], 1) &
- rol16(xleft[i], 8)) ^ rol16(xleft[i], 2);
- xleft[i + 1] = xright[i] ^ fxleft[i] ^ eff_k[i];
- xright[i + 1] = xleft[i];
- }
-
- return (((uint32_t)xright[32]) << 16) | xleft[32];
-}
-static uint64_t hash_digest(uint64_t ra, uint64_t rb, uint64_t key)
-{
- uint64_t stage0_h = 0ULL, stage0_l = 0ULL;
- uint64_t stage1_h, stage1_l;
-
- for (int i = 0; i < 4; i++) {
- stage0_h |= ror64(rb & 0xff, 8 * (2 * i + 1));
- stage0_h |= ((ra >> 32) & 0xff) << (8 * 2 * i);
- stage0_l |= ror64((rb >> 32) & 0xff, 8 * (2 * i + 1));
- stage0_l |= (ra & 0xff) << (8 * 2 * i);
- rb >>= 8;
- ra >>= 8;
- }
-
- stage1_h = (uint64_t)helper_SIMON_LIKE_32_64(stage0_h >> 32, key, 0) << 32;
- stage1_h |= helper_SIMON_LIKE_32_64(stage0_h, key, 1);
- stage1_l = (uint64_t)helper_SIMON_LIKE_32_64(stage0_l >> 32, key, 2) << 32;
- stage1_l |= helper_SIMON_LIKE_32_64(stage0_l, key, 3);
-
- return stage1_h ^ stage1_l;
-}
-
-static void do_hash(CPUPPCState *env, target_ulong ea, target_ulong ra,
- target_ulong rb, uint64_t key, bool store)
-{
- uint64_t calculated_hash = hash_digest(ra, rb, key), loaded_hash;
-
- if (store) {
- cpu_stq_data_ra(env, ea, calculated_hash, GETPC());
- } else {
- loaded_hash = cpu_ldq_data_ra(env, ea, GETPC());
- if (loaded_hash != calculated_hash) {
- raise_exception_err_ra(env, POWERPC_EXCP_PROGRAM,
- POWERPC_EXCP_TRAP, GETPC());
- }
- }
-}
-
-#include "qemu/guest-random.h"
-
-#ifdef TARGET_PPC64
-#define HELPER_HASH(op, key, store, dexcr_aspect) \
-void helper_##op(CPUPPCState *env, target_ulong ea, target_ulong ra, \
- target_ulong rb) \
-{ \
- if (env->msr & R_MSR_PR_MASK) { \
- if (!(env->spr[SPR_DEXCR] & R_DEXCR_PRO_##dexcr_aspect##_MASK || \
- env->spr[SPR_HDEXCR] & R_HDEXCR_ENF_##dexcr_aspect##_MASK)) \
- return; \
- } else if (!(env->msr & R_MSR_HV_MASK)) { \
- if (!(env->spr[SPR_DEXCR] & R_DEXCR_PNH_##dexcr_aspect##_MASK || \
- env->spr[SPR_HDEXCR] & R_HDEXCR_ENF_##dexcr_aspect##_MASK)) \
- return; \
- } else if (!(env->msr & R_MSR_S_MASK)) { \
- if (!(env->spr[SPR_HDEXCR] & R_HDEXCR_HNU_##dexcr_aspect##_MASK)) \
- return; \
- } \
- \
- do_hash(env, ea, ra, rb, key, store); \
-}
-#else
-#define HELPER_HASH(op, key, store, dexcr_aspect) \
-void helper_##op(CPUPPCState *env, target_ulong ea, target_ulong ra, \
- target_ulong rb) \
-{ \
- do_hash(env, ea, ra, rb, key, store); \
-}
-#endif /* TARGET_PPC64 */
-
-HELPER_HASH(HASHST, env->spr[SPR_HASHKEYR], true, NPHIE)
-HELPER_HASH(HASHCHK, env->spr[SPR_HASHKEYR], false, NPHIE)
-HELPER_HASH(HASHSTP, env->spr[SPR_HASHPKEYR], true, PHIE)
-HELPER_HASH(HASHCHKP, env->spr[SPR_HASHPKEYR], false, PHIE)
-
-#ifndef CONFIG_USER_ONLY
/* Embedded.Processor Control */
static int dbell2irq(target_ulong rb)
{
diff --git a/target/ppc/tcg-excp_helper.c b/target/ppc/tcg-excp_helper.c
index 268a161459..2459d2d095 100644
--- a/target/ppc/tcg-excp_helper.c
+++ b/target/ppc/tcg-excp_helper.c
@@ -66,6 +66,149 @@ void raise_exception(CPUPPCState *env, uint32_t exception)
raise_exception_err_ra(env, exception, 0, 0);
}
+#endif /* !CONFIG_USER_ONLY */
+
+void helper_TW(CPUPPCState *env, target_ulong arg1, target_ulong arg2,
+ uint32_t flags)
+{
+ if (!likely(!(((int32_t)arg1 < (int32_t)arg2 && (flags & 0x10)) ||
+ ((int32_t)arg1 > (int32_t)arg2 && (flags & 0x08)) ||
+ ((int32_t)arg1 == (int32_t)arg2 && (flags & 0x04)) ||
+ ((uint32_t)arg1 < (uint32_t)arg2 && (flags & 0x02)) ||
+ ((uint32_t)arg1 > (uint32_t)arg2 && (flags & 0x01))))) {
+ raise_exception_err_ra(env, POWERPC_EXCP_PROGRAM,
+ POWERPC_EXCP_TRAP, GETPC());
+ }
+}
+
+#ifdef TARGET_PPC64
+void helper_TD(CPUPPCState *env, target_ulong arg1, target_ulong arg2,
+ uint32_t flags)
+{
+ if (!likely(!(((int64_t)arg1 < (int64_t)arg2 && (flags & 0x10)) ||
+ ((int64_t)arg1 > (int64_t)arg2 && (flags & 0x08)) ||
+ ((int64_t)arg1 == (int64_t)arg2 && (flags & 0x04)) ||
+ ((uint64_t)arg1 < (uint64_t)arg2 && (flags & 0x02)) ||
+ ((uint64_t)arg1 > (uint64_t)arg2 && (flags & 0x01))))) {
+ raise_exception_err_ra(env, POWERPC_EXCP_PROGRAM,
+ POWERPC_EXCP_TRAP, GETPC());
+ }
+}
+#endif /* TARGET_PPC64 */
+
+static uint32_t helper_SIMON_LIKE_32_64(uint32_t x, uint64_t key, uint32_t lane)
+{
+ const uint16_t c = 0xfffc;
+ const uint64_t z0 = 0xfa2561cdf44ac398ULL;
+ uint16_t z = 0, temp;
+ uint16_t k[32], eff_k[32], xleft[33], xright[33], fxleft[32];
+
+ for (int i = 3; i >= 0; i--) {
+ k[i] = key & 0xffff;
+ key >>= 16;
+ }
+ xleft[0] = x & 0xffff;
+ xright[0] = (x >> 16) & 0xffff;
+
+ for (int i = 0; i < 28; i++) {
+ z = (z0 >> (63 - i)) & 1;
+ temp = ror16(k[i + 3], 3) ^ k[i + 1];
+ k[i + 4] = c ^ z ^ k[i] ^ temp ^ ror16(temp, 1);
+ }
+
+ for (int i = 0; i < 8; i++) {
+ eff_k[4 * i + 0] = k[4 * i + ((0 + lane) % 4)];
+ eff_k[4 * i + 1] = k[4 * i + ((1 + lane) % 4)];
+ eff_k[4 * i + 2] = k[4 * i + ((2 + lane) % 4)];
+ eff_k[4 * i + 3] = k[4 * i + ((3 + lane) % 4)];
+ }
+
+ for (int i = 0; i < 32; i++) {
+ fxleft[i] = (rol16(xleft[i], 1) &
+ rol16(xleft[i], 8)) ^ rol16(xleft[i], 2);
+ xleft[i + 1] = xright[i] ^ fxleft[i] ^ eff_k[i];
+ xright[i + 1] = xleft[i];
+ }
+
+ return (((uint32_t)xright[32]) << 16) | xleft[32];
+}
+
+static uint64_t hash_digest(uint64_t ra, uint64_t rb, uint64_t key)
+{
+ uint64_t stage0_h = 0ULL, stage0_l = 0ULL;
+ uint64_t stage1_h, stage1_l;
+
+ for (int i = 0; i < 4; i++) {
+ stage0_h |= ror64(rb & 0xff, 8 * (2 * i + 1));
+ stage0_h |= ((ra >> 32) & 0xff) << (8 * 2 * i);
+ stage0_l |= ror64((rb >> 32) & 0xff, 8 * (2 * i + 1));
+ stage0_l |= (ra & 0xff) << (8 * 2 * i);
+ rb >>= 8;
+ ra >>= 8;
+ }
+
+ stage1_h = (uint64_t)helper_SIMON_LIKE_32_64(stage0_h >> 32, key, 0) << 32;
+ stage1_h |= helper_SIMON_LIKE_32_64(stage0_h, key, 1);
+ stage1_l = (uint64_t)helper_SIMON_LIKE_32_64(stage0_l >> 32, key, 2) << 32;
+ stage1_l |= helper_SIMON_LIKE_32_64(stage0_l, key, 3);
+
+ return stage1_h ^ stage1_l;
+}
+
+static void do_hash(CPUPPCState *env, target_ulong ea, target_ulong ra,
+ target_ulong rb, uint64_t key, bool store)
+{
+ uint64_t calculated_hash = hash_digest(ra, rb, key), loaded_hash;
+
+ if (store) {
+ cpu_stq_data_ra(env, ea, calculated_hash, GETPC());
+ } else {
+ loaded_hash = cpu_ldq_data_ra(env, ea, GETPC());
+ if (loaded_hash != calculated_hash) {
+ raise_exception_err_ra(env, POWERPC_EXCP_PROGRAM,
+ POWERPC_EXCP_TRAP, GETPC());
+ }
+ }
+}
+
+#include "qemu/guest-random.h"
+
+#ifdef TARGET_PPC64
+#define HELPER_HASH(op, key, store, dexcr_aspect) \
+void helper_##op(CPUPPCState *env, target_ulong ea, target_ulong ra, \
+ target_ulong rb) \
+{ \
+ if (env->msr & R_MSR_PR_MASK) { \
+ if (!(env->spr[SPR_DEXCR] & R_DEXCR_PRO_##dexcr_aspect##_MASK || \
+ env->spr[SPR_HDEXCR] & R_HDEXCR_ENF_##dexcr_aspect##_MASK)) \
+ return; \
+ } else if (!(env->msr & R_MSR_HV_MASK)) { \
+ if (!(env->spr[SPR_DEXCR] & R_DEXCR_PNH_##dexcr_aspect##_MASK || \
+ env->spr[SPR_HDEXCR] & R_HDEXCR_ENF_##dexcr_aspect##_MASK)) \
+ return; \
+ } else if (!(env->msr & R_MSR_S_MASK)) { \
+ if (!(env->spr[SPR_HDEXCR] & R_HDEXCR_HNU_##dexcr_aspect##_MASK)) \
+ return; \
+ } \
+ \
+ do_hash(env, ea, ra, rb, key, store); \
+}
+#else
+#define HELPER_HASH(op, key, store, dexcr_aspect) \
+void helper_##op(CPUPPCState *env, target_ulong ea, target_ulong ra, \
+ target_ulong rb) \
+{ \
+ do_hash(env, ea, ra, rb, key, store); \
+}
+#endif /* TARGET_PPC64 */
+
+HELPER_HASH(HASHST, env->spr[SPR_HASHKEYR], true, NPHIE)
+HELPER_HASH(HASHCHK, env->spr[SPR_HASHKEYR], false, NPHIE)
+HELPER_HASH(HASHSTP, env->spr[SPR_HASHPKEYR], true, PHIE)
+HELPER_HASH(HASHCHKP, env->spr[SPR_HASHPKEYR], false, PHIE)
+
+#ifndef CONFIG_USER_ONLY
+
void ppc_cpu_do_unaligned_access(CPUState *cs, vaddr vaddr,
MMUAccessType access_type,
int mmu_idx, uintptr_t retaddr)
--
2.47.1
next prev parent reply other threads:[~2025-03-11 13:15 UTC|newest]
Thread overview: 83+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-03-11 12:56 [PULL 00/72] ppc-for-10.0-1 queue Nicholas Piggin
2025-03-11 12:56 ` [PULL 01/72] ppc/ppc405: Remove tests Nicholas Piggin
2025-03-11 12:56 ` [PULL 02/72] ppc/ppc405: Remove boards Nicholas Piggin
2025-03-11 12:56 ` [PULL 03/72] hw/ppc: Deprecate 405 CPUs Nicholas Piggin
2025-03-11 12:56 ` [PULL 04/72] ppc/pnv: Update skiboot to 7.1-106 Nicholas Piggin
2025-03-11 12:56 ` [PULL 05/72] pseries: Update SLOF firmware image Nicholas Piggin
2025-03-11 12:57 ` [PULL 06/72] ppc/pnv/phb4: Add pervasive chiplet support to PHB4/5 Nicholas Piggin
2025-03-11 12:57 ` [PULL 07/72] ppc/pnv/homer: Fix OCC registers Nicholas Piggin
2025-03-11 12:57 ` [PULL 08/72] ppc/pnv/homer: Make dummy reads return 0 Nicholas Piggin
2025-03-11 12:57 ` [PULL 09/72] ppc/pnv/occ: Fix common area sensor offsets Nicholas Piggin
2025-03-13 7:57 ` Michael Tokarev
2025-03-11 12:57 ` [PULL 10/72] ppc/pnv/homer: class-based base and size Nicholas Piggin
2025-03-11 12:57 ` [PULL 11/72] ppc/pnv/occ: Better document OCCMISC bits Nicholas Piggin
2025-03-11 12:57 ` [PULL 12/72] ppc/pnv: Make HOMER memory a RAM region Nicholas Piggin
2025-03-11 12:57 ` [PULL 13/72] ppc/pnv/occ: Update pstate frequency tables Nicholas Piggin
2025-03-11 12:57 ` [PULL 14/72] ppc/pnv/occ: Add POWER10 OCC-OPAL data format Nicholas Piggin
2025-03-11 12:57 ` [PULL 15/72] ppc/pnv/occ: Implement a basic dynamic OCC model Nicholas Piggin
2025-03-11 12:57 ` [PULL 16/72] target/ppc: Add Power9/10 power management SPRs Nicholas Piggin
2025-03-11 12:57 ` [PULL 17/72] ppc/pnv: Support LPC host controller irqs other than serirqs Nicholas Piggin
2025-03-11 12:57 ` [PULL 18/72] ppc/pnv: raise no-response errors if an LPC transaction fails Nicholas Piggin
2025-03-11 12:57 ` [PULL 19/72] ppc/pnv: Implement LPC FW address space IDSEL Nicholas Piggin
2025-03-11 12:57 ` [PULL 20/72] ppc/pnv: Move PNOR to offset 0 in the ISA FW space Nicholas Piggin
2025-03-11 12:57 ` [PULL 21/72] ppc/pnv: Add a PNOR address and size sanity checks Nicholas Piggin
2025-03-11 12:57 ` [PULL 22/72] ppc/pnv: Add a default formatted PNOR image Nicholas Piggin
2025-03-11 12:57 ` [PULL 23/72] ppc/xive2: Update NVP save/restore for group attributes Nicholas Piggin
2025-03-11 12:57 ` [PULL 24/72] ppc/xive: Rename ipb_to_pipr() to xive_ipb_to_pipr() Nicholas Piggin
2025-03-11 12:57 ` [PULL 25/72] ppc/xive2: Add grouping level to notification Nicholas Piggin
2025-03-11 12:57 ` [PULL 26/72] ppc/xive2: Support group-matching when looking for target Nicholas Piggin
2025-03-11 12:57 ` [PULL 27/72] ppc/xive2: Add undelivered group interrupt to backlog Nicholas Piggin
2025-03-11 12:57 ` [PULL 28/72] ppc/xive2: Process group backlog when pushing an OS context Nicholas Piggin
2025-03-11 12:57 ` [PULL 29/72] ppc/xive2: Process group backlog when updating the CPPR Nicholas Piggin
2025-03-11 12:57 ` [PULL 30/72] qtest/xive: Add group-interrupt test Nicholas Piggin
2025-03-11 12:57 ` [PULL 31/72] ppc/xive2: Add support for MMIO operations on the NVPG/NVC BAR Nicholas Piggin
2025-03-11 12:57 ` [PULL 32/72] ppc/xive2: Support crowd-matching when looking for target Nicholas Piggin
2025-03-11 12:57 ` [PULL 33/72] pnv/xive2: Rename nvp_ to nvx_ if they can refer to NVP or NVGC Nicholas Piggin
2025-03-11 12:57 ` [PULL 34/72] ppc/xive2: Check crowd backlog when scanning group backlog Nicholas Piggin
2025-03-11 12:57 ` [PULL 35/72] qtest/xive: Change printf to g_test_message Nicholas Piggin
2025-03-11 12:57 ` [PULL 36/72] qtest/xive: Add test of pool interrupts Nicholas Piggin
2025-03-11 12:57 ` [PULL 37/72] hw/ssi/pnv_spi: Replace PnvXferBuffer with Fifo8 structure Nicholas Piggin
2025-03-11 12:57 ` [PULL 38/72] hw/ssi/pnv_spi: Use local var seq_index instead of get_seq_index() Nicholas Piggin
2025-03-11 12:57 ` [PULL 39/72] hw/ssi/pnv_spi: Make bus names distinct for each controllers of a socket Nicholas Piggin
2025-03-11 12:57 ` [PULL 40/72] hw/ssi/pnv_spi: Put a limit to RDR match failures Nicholas Piggin
2025-03-11 12:57 ` [PULL 41/72] hw/ppc/spapr: Restrict CONFER hypercall to TCG Nicholas Piggin
2025-03-11 12:57 ` [PULL 42/72] ppc/pnv: Add new PowerPC Special Purpose Registers (RWMR) Nicholas Piggin
2025-03-11 12:57 ` [PULL 43/72] target/ppc: Make ppc_ldl_code() declaration public Nicholas Piggin
2025-03-11 12:57 ` [PULL 44/72] target/ppc: Move TCG specific exception handlers to tcg-excp_helper.c Nicholas Piggin
2025-03-11 12:57 ` [PULL 45/72] target/ppc: Move ppc_ldl_code() " Nicholas Piggin
2025-03-11 12:57 ` [PULL 46/72] target/ppc: Ensure powerpc_mcheck_checkstop() is only called under TCG Nicholas Piggin
2025-03-11 12:57 ` [PULL 47/72] target/ppc: Restrict powerpc_checkstop() to TCG Nicholas Piggin
2025-03-11 12:57 ` [PULL 48/72] target/ppc: Remove raise_exception_ra() Nicholas Piggin
2025-03-11 12:57 ` [PULL 49/72] target/ppc: Restrict exception helpers to TCG Nicholas Piggin
2025-03-11 12:57 ` Nicholas Piggin [this message]
2025-03-11 12:57 ` [PULL 51/72] target/ppc: Fix style in excp_helper.c Nicholas Piggin
2025-03-11 12:57 ` [PULL 52/72] target/ppc: Make powerpc_excp() prototype public Nicholas Piggin
2025-03-11 12:57 ` [PULL 53/72] target/ppc: Restrict ATTN / SCV / PMINSN helpers to TCG Nicholas Piggin
2025-03-11 12:57 ` [PULL 54/72] hw/ppc/spapr: Convert HPTE() macro as hpte_get_ptr() method Nicholas Piggin
2025-03-11 12:57 ` [PULL 55/72] hw/ppc/spapr: Convert HPTE_VALID() macro as hpte_is_valid() method Nicholas Piggin
2025-03-11 12:57 ` [PULL 56/72] hw/ppc/spapr: Convert HPTE_DIRTY() macro as hpte_is_dirty() method Nicholas Piggin
2025-03-11 12:57 ` [PULL 57/72] hw/ppc/spapr: Convert CLEAN_HPTE() macro as hpte_set_clean() method Nicholas Piggin
2025-03-11 12:57 ` [PULL 58/72] hw/ppc/spapr: Convert DIRTY_HPTE() macro as hpte_set_dirty() method Nicholas Piggin
2025-03-11 12:57 ` [PULL 59/72] hw/ppc/epapr: Do not swap ePAPR magic value Nicholas Piggin
2025-03-11 12:57 ` [PULL 60/72] ppc: Enable 2nd DAWR support on Power10 PowerNV machine Nicholas Piggin
2025-03-11 12:57 ` [PULL 61/72] ppc: spapr: Enable 2nd DAWR on Power10 pSeries machine Nicholas Piggin
2025-03-11 12:57 ` [PULL 62/72] spapr: nested: Add support for reporting Hostwide state counter Nicholas Piggin
2025-03-11 12:57 ` [PULL 63/72] target/ppc: fix timebase register reset state Nicholas Piggin
2025-03-11 12:57 ` [PULL 64/72] target/ppc: Wire up BookE ATB registers for e500 family Nicholas Piggin
2025-03-11 12:57 ` [PULL 65/72] target/ppc: Avoid warning message for zero process table entries Nicholas Piggin
2025-03-11 12:58 ` [PULL 66/72] spapr: Generate random HASHPKEYR for spapr machines Nicholas Piggin
2025-03-11 12:58 ` [PULL 67/72] ppc/amigaone: Simplify replacement dummy_fw Nicholas Piggin
2025-03-11 12:58 ` [PULL 68/72] ppc/amigaone: Implement NVRAM emulation Nicholas Piggin
2025-03-11 12:58 ` [PULL 69/72] ppc/amigaone: Add default environment Nicholas Piggin
2025-03-11 12:58 ` [PULL 70/72] ppc/amigaone: Add kernel and initrd support Nicholas Piggin
2025-06-16 10:07 ` Philippe Mathieu-Daudé
2025-06-16 10:38 ` BALATON Zoltan
2025-03-11 12:58 ` [PULL 71/72] ppc/amigaone: Add #defines for memory map constants Nicholas Piggin
2025-03-11 12:58 ` [PULL 72/72] docs/system/ppc/amigang.rst: Update for NVRAM emulation Nicholas Piggin
2025-03-13 2:34 ` [PULL 00/72] ppc-for-10.0-1 queue Stefan Hajnoczi
2025-03-13 6:13 ` Thomas Huth
2025-03-13 10:49 ` Philippe Mathieu-Daudé
2025-03-14 2:34 ` Nicholas Piggin
2025-03-14 6:19 ` Thomas Huth
2025-03-14 2:41 ` Nicholas Piggin
2025-03-13 7:05 ` Stefan Hajnoczi
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