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From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [PULL 01/17] target/arm: Move A32_BANKED_REG_{GET, SET} macros to cpregs.h
Date: Fri, 14 Mar 2025 13:16:21 +0000	[thread overview]
Message-ID: <20250314131637.371866-2-peter.maydell@linaro.org> (raw)
In-Reply-To: <20250314131637.371866-1-peter.maydell@linaro.org>

The A32_BANKED_REG_{GET,SET} macros are only used inside target/arm;
move their definitions to cpregs.h. There's no need to have them
defined in all the code that includes cpu.h.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
 target/arm/cpregs.h | 28 ++++++++++++++++++++++++++++
 target/arm/cpu.h    | 27 ---------------------------
 2 files changed, 28 insertions(+), 27 deletions(-)

diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h
index 52377c6eb50..2183de8eda6 100644
--- a/target/arm/cpregs.h
+++ b/target/arm/cpregs.h
@@ -1157,4 +1157,32 @@ static inline bool arm_cpreg_traps_in_nv(const ARMCPRegInfo *ri)
     return ri->opc1 == 4 || ri->opc1 == 5;
 }
 
+/* Macros for accessing a specified CP register bank */
+#define A32_BANKED_REG_GET(_env, _regname, _secure)                     \
+    ((_secure) ? (_env)->cp15._regname##_s : (_env)->cp15._regname##_ns)
+
+#define A32_BANKED_REG_SET(_env, _regname, _secure, _val)       \
+    do {                                                        \
+        if (_secure) {                                          \
+            (_env)->cp15._regname##_s = (_val);                 \
+        } else {                                                \
+            (_env)->cp15._regname##_ns = (_val);                \
+        }                                                       \
+    } while (0)
+
+/*
+ * Macros for automatically accessing a specific CP register bank depending on
+ * the current secure state of the system.  These macros are not intended for
+ * supporting instruction translation reads/writes as these are dependent
+ * solely on the SCR.NS bit and not the mode.
+ */
+#define A32_BANKED_CURRENT_REG_GET(_env, _regname)                          \
+    A32_BANKED_REG_GET((_env), _regname,                                    \
+                       (arm_is_secure(_env) && !arm_el_is_aa64((_env), 3)))
+
+#define A32_BANKED_CURRENT_REG_SET(_env, _regname, _val)                    \
+    A32_BANKED_REG_SET((_env), _regname,                                    \
+                       (arm_is_secure(_env) && !arm_el_is_aa64((_env), 3)), \
+                       (_val))
+
 #endif /* TARGET_ARM_CPREGS_H */
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index 8f52380c88c..15d3a79b0af 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -2684,33 +2684,6 @@ static inline bool access_secure_reg(CPUARMState *env)
     return ret;
 }
 
-/* Macros for accessing a specified CP register bank */
-#define A32_BANKED_REG_GET(_env, _regname, _secure)    \
-    ((_secure) ? (_env)->cp15._regname##_s : (_env)->cp15._regname##_ns)
-
-#define A32_BANKED_REG_SET(_env, _regname, _secure, _val)   \
-    do {                                                \
-        if (_secure) {                                   \
-            (_env)->cp15._regname##_s = (_val);            \
-        } else {                                        \
-            (_env)->cp15._regname##_ns = (_val);           \
-        }                                               \
-    } while (0)
-
-/* Macros for automatically accessing a specific CP register bank depending on
- * the current secure state of the system.  These macros are not intended for
- * supporting instruction translation reads/writes as these are dependent
- * solely on the SCR.NS bit and not the mode.
- */
-#define A32_BANKED_CURRENT_REG_GET(_env, _regname)        \
-    A32_BANKED_REG_GET((_env), _regname,                \
-                       (arm_is_secure(_env) && !arm_el_is_aa64((_env), 3)))
-
-#define A32_BANKED_CURRENT_REG_SET(_env, _regname, _val)                       \
-    A32_BANKED_REG_SET((_env), _regname,                                    \
-                       (arm_is_secure(_env) && !arm_el_is_aa64((_env), 3)), \
-                       (_val))
-
 uint32_t arm_phys_excp_target_el(CPUState *cs, uint32_t excp_idx,
                                  uint32_t cur_el, bool secure);
 
-- 
2.43.0



  reply	other threads:[~2025-03-14 13:17 UTC|newest]

Thread overview: 19+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-03-14 13:16 [PULL 00/17] target-arm queue Peter Maydell
2025-03-14 13:16 ` Peter Maydell [this message]
2025-03-14 13:16 ` [PULL 02/17] target/arm: Un-inline access_secure_reg() Peter Maydell
2025-03-14 13:16 ` [PULL 03/17] linux-user/aarch64: Remove unused get/put_user macros Peter Maydell
2025-03-14 13:16 ` [PULL 04/17] linux-user/arm: Remove unused get_put_user macros Peter Maydell
2025-03-14 13:16 ` [PULL 05/17] target/arm: Move arm_cpu_data_is_big_endian() etc to internals.h Peter Maydell
2025-03-14 13:16 ` [PULL 06/17] target/arm: Move arm_current_el() and arm_el_is_aa64() " Peter Maydell
2025-03-14 13:16 ` [PULL 07/17] target/arm: SCR_EL3.RW should be treated as 1 if EL2 doesn't support AArch32 Peter Maydell
2025-03-14 13:16 ` [PULL 08/17] target/arm: HCR_EL2.RW should be RAO/WI if EL1 " Peter Maydell
2025-03-14 13:16 ` [PULL 09/17] target/arm: Add cpu local variable to exception_return helper Peter Maydell
2025-03-14 13:16 ` [PULL 10/17] target/arm: Forbid return to AArch32 when CPU is AArch64-only Peter Maydell
2025-03-14 13:16 ` [PULL 11/17] MAINTAINERS: Fix status for Arm boards I "maintain" Peter Maydell
2025-03-14 13:16 ` [PULL 12/17] tests/functional: Bump up arm_replay timeout Peter Maydell
2025-03-14 13:16 ` [PULL 13/17] Revert "hw/char/pl011: Warn when using disabled receiver" Peter Maydell
2025-03-14 13:16 ` [PULL 14/17] util/cacheflush: Make first DSB unconditional on aarch64 Peter Maydell
2025-03-14 13:16 ` [PULL 15/17] target/arm: Make DisasContext.{fp, sve}_access_checked tristate Peter Maydell
2025-03-14 13:16 ` [PULL 16/17] target/arm: Simplify pstate_sm check in sve_access_check Peter Maydell
2025-03-14 13:16 ` [PULL 17/17] meson.build: Set RUST_BACKTRACE for all tests Peter Maydell
2025-03-16 10:10 ` [PULL 00/17] target-arm queue Stefan Hajnoczi

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