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Tsirkin" To: Jason Chien Cc: qemu-devel@nongnu.org, qemu-riscv@nongnu.org, Peter Maydell , Andrey Smirnov , Marcel Apfelbaum , Palmer Dabbelt , Alistair Francis , Weiwei Li , Daniel Henrique Barboza , Liu Zhiwei , "open list:MCIMX7D SABRE / i..." Subject: Re: [PATCH 0/4] Integrate IOMMUs with PCI hosts that have ATUs Message-ID: <20250319134141-mutt-send-email-mst@kernel.org> References: <20250307203952.13871-1-jason.chien@sifive.com> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: Received-SPF: pass client-ip=170.10.133.124; envelope-from=mst@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -23 X-Spam_score: -2.4 X-Spam_bar: -- X-Spam_report: (-2.4 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.337, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=0.001, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On Thu, Mar 20, 2025 at 01:19:18AM +0800, Jason Chien wrote: > Ping > > Jason Chien 於 2025年3月8日週六上午4:40寫道： > > The struct PCIIOMMUOps is designed for use by an IOMMU, but many PCI hosts > also utilize it to implement their ATUs, preventing coexistence with > IOMMUs. > Overwriting a PCI host’s PCIIOMMUOps disrupts its translation rules. > > This patch series introduces a mechanism to route inbound transactions from > PCI hosts to the IOMMU, enabling proper integration. > > The final patch depends on another patch series: > https://lists.nongnu.org/archive/html/qemu-riscv/2025-03/msg00003.html > > Jason Chien (4): >   include/hw/pci: Introduce a callback to set the downstream mr of PCI >     hosts >   hw/pci: Introduce an API to set PCI host downstream mr for IOMMU >     integration >   hw/pci-host/designware: Implement PCIIOMMUOps.set_downstream_mr() >   hw/riscv/riscv-iommu: Connect the IOMMU with PCI hosts that have ATUs > >  hw/pci-host/designware.c         | 18 +++++++++++++++--- >  hw/pci/pci.c                     |  8 ++++++++ >  hw/riscv/riscv-iommu.c           | 15 ++++++++++----- >  include/hw/pci-host/designware.h |  2 ++ >  include/hw/pci/pci.h             | 21 +++++++++++++++++++++ >  5 files changed, 56 insertions(+), 8 deletions(-) Hello! I tagged this for 10.1, as qemu entered code freeze. > -- > 2.43.2 > >