[PATCH-for-10.1 00/12] tcg: Make tcg_gen_insn_start() target-agnostic

[PATCH-for-10.1 00/12] tcg: Make tcg_gen_insn_start() target-agnostic

[Philippe Mathieu-Daudé]

Instead of TARGET_INSN_START_EXTRA_WORDS, use
TCGContext::insn_start_words().
Define TARGET_INSN_START_WORDS_MAX and reduce
TARGET_INSN_START_EXTRA_WORDS scope.
Unify tcg_gen_insn_start() prototypes.

(preparatory for heterogeneous emulation)

Philippe Mathieu-Daudé (12):
  tcg: Declare TARGET_INSN_START_EXTRA_WORDS in 'cpu-param.h'
  tcg: Always define TARGET_INSN_START_EXTRA_WORDS
  tcg: Have tcg_gen_insn_start() take uint64_t arguments
  tcg: Declare local 'insn_start_words' variable in tcg_gen_insn_start()
  tcg: Use TCGContext::insn_start_words in tcg_gen_insn_start()
  tcg: Use TCGContext::insn_start_words in translate-all.c methods
  tcg: Check TARGET_INSN_START_EXTRA_WORDS range at runtime
  tcg: Declare arrays using TARGET_INSN_START_WORDS_MAX
  tcg: Restrict TARGET_INSN_START_WORDS definition to translate-all.c
  tcg: Unify tcg_gen_insn_start() to handle 1 or 2 arguments
  tcg: Unify tcg_gen_insn_start() to handle 0 or 2 arguments
  tcg: Uninline tcg_gen_insn_start()

 include/tcg/insn-start-words.h   | 17 -----------------
 include/tcg/tcg-op.h             | 26 --------------------------
 include/tcg/tcg.h                |  4 ++++
 target/alpha/cpu-param.h         |  2 ++
 target/arm/cpu-param.h           | 14 ++++++++++++++
 target/arm/cpu.h                 | 14 --------------
 target/avr/cpu-param.h           |  2 ++
 target/hexagon/cpu-param.h       |  2 ++
 target/hppa/cpu-param.h          |  2 ++
 target/hppa/cpu.h                |  2 --
 target/i386/cpu-param.h          |  2 ++
 target/i386/cpu.h                |  2 --
 target/loongarch/cpu-param.h     |  2 ++
 target/m68k/cpu-param.h          |  2 ++
 target/m68k/cpu.h                |  2 --
 target/microblaze/cpu-param.h    |  2 ++
 target/microblaze/cpu.h          |  2 --
 target/mips/cpu-param.h          |  2 ++
 target/mips/cpu.h                |  2 --
 target/openrisc/cpu-param.h      |  2 ++
 target/openrisc/cpu.h            |  2 --
 target/ppc/cpu-param.h           |  2 ++
 target/riscv/cpu-param.h         |  8 ++++++++
 target/riscv/cpu.h               |  6 ------
 target/rx/cpu-param.h            |  2 ++
 target/s390x/cpu-param.h         |  2 ++
 target/s390x/cpu.h               |  2 --
 target/sh4/cpu-param.h           |  2 ++
 target/sh4/cpu.h                 |  2 --
 target/sparc/cpu-param.h         |  2 ++
 target/sparc/cpu.h               |  1 -
 target/tricore/cpu-param.h       |  2 ++
 target/xtensa/cpu-param.h        |  2 ++
 accel/tcg/translate-all.c        | 26 ++++++++++++++++----------
 target/alpha/translate.c         |  4 ++--
 target/avr/translate.c           |  2 +-
 target/i386/helper.c             |  4 ++--
 target/i386/tcg/translate.c      |  2 +-
 target/loongarch/tcg/translate.c |  2 +-
 target/m68k/translate.c          |  2 +-
 target/microblaze/translate.c    |  2 +-
 target/openrisc/sys_helper.c     |  4 ++--
 target/openrisc/translate.c      |  2 +-
 target/ppc/translate.c           |  2 +-
 target/rx/translate.c            |  2 +-
 target/sh4/translate.c           |  2 +-
 target/sparc/translate.c         |  2 +-
 target/tricore/translate.c       |  2 +-
 target/xtensa/translate.c        |  2 +-
 tcg/tcg.c                        | 15 +++++++++++++++
 50 files changed, 109 insertions(+), 108 deletions(-)
 delete mode 100644 include/tcg/insn-start-words.h

-- 
2.47.1

[PATCH-for-10.1 01/12] tcg: Declare TARGET_INSN_START_EXTRA_WORDS in 'cpu-param.h'

[Philippe Mathieu-Daudé]

To avoid including the huge "cpu.h" for a simple definition,
move TARGET_INSN_START_EXTRA_WORDS to "cpu-param.h".

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
 target/arm/cpu-param.h        | 14 ++++++++++++++
 target/arm/cpu.h              | 14 --------------
 target/hppa/cpu-param.h       |  2 ++
 target/hppa/cpu.h             |  2 --
 target/i386/cpu-param.h       |  2 ++
 target/i386/cpu.h             |  2 --
 target/m68k/cpu-param.h       |  2 ++
 target/m68k/cpu.h             |  2 --
 target/microblaze/cpu-param.h |  2 ++
 target/microblaze/cpu.h       |  2 --
 target/mips/cpu-param.h       |  2 ++
 target/mips/cpu.h             |  2 --
 target/openrisc/cpu-param.h   |  2 ++
 target/openrisc/cpu.h         |  2 --
 target/riscv/cpu-param.h      |  8 ++++++++
 target/riscv/cpu.h            |  6 ------
 target/s390x/cpu-param.h      |  2 ++
 target/s390x/cpu.h            |  2 --
 target/sh4/cpu-param.h        |  2 ++
 target/sh4/cpu.h              |  2 --
 target/sparc/cpu-param.h      |  2 ++
 target/sparc/cpu.h            |  1 -
 22 files changed, 40 insertions(+), 37 deletions(-)

diff --git a/target/arm/cpu-param.h b/target/arm/cpu-param.h
index 896b35bd6d5..ed1f0b16e51 100644
--- a/target/arm/cpu-param.h
+++ b/target/arm/cpu-param.h
@@ -38,6 +38,20 @@
 # define TARGET_PAGE_BITS_MIN  10
 #endif /* !CONFIG_USER_ONLY */
 
+/* ARM-specific extra insn start words:
+ * 1: Conditional execution bits
+ * 2: Partial exception syndrome for data aborts
+ */
+#define TARGET_INSN_START_EXTRA_WORDS 2
+
+/* The 2nd extra word holding syndrome info for data aborts does not use
+ * the upper 6 bits nor the lower 13 bits. We mask and shift it down to
+ * help the sleb128 encoder do a better job.
+ * When restoring the CPU state, we shift it back up.
+ */
+#define ARM_INSN_START_WORD2_MASK ((1 << 26) - 1)
+#define ARM_INSN_START_WORD2_SHIFT 13
+
 /* ARM processors have a weak memory model */
 #define TCG_GUEST_DEFAULT_MO      (0)
 
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index a8177c6c2e8..537359ff30b 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -100,20 +100,6 @@
 #define offsetofhigh32(S, M) (offsetof(S, M) + sizeof(uint32_t))
 #endif
 
-/* ARM-specific extra insn start words:
- * 1: Conditional execution bits
- * 2: Partial exception syndrome for data aborts
- */
-#define TARGET_INSN_START_EXTRA_WORDS 2
-
-/* The 2nd extra word holding syndrome info for data aborts does not use
- * the upper 6 bits nor the lower 13 bits. We mask and shift it down to
- * help the sleb128 encoder do a better job.
- * When restoring the CPU state, we shift it back up.
- */
-#define ARM_INSN_START_WORD2_MASK ((1 << 26) - 1)
-#define ARM_INSN_START_WORD2_SHIFT 13
-
 /* We currently assume float and double are IEEE single and double
    precision respectively.
    Doing runtime conversions is tricky because VFP registers may contain
diff --git a/target/hppa/cpu-param.h b/target/hppa/cpu-param.h
index 7ed6b5741e7..68ed84e84af 100644
--- a/target/hppa/cpu-param.h
+++ b/target/hppa/cpu-param.h
@@ -19,6 +19,8 @@
 
 #define TARGET_PAGE_BITS 12
 
+#define TARGET_INSN_START_EXTRA_WORDS 2
+
 /* PA-RISC 1.x processors have a strong memory model.  */
 /*
  * ??? While we do not yet implement PA-RISC 2.0, those processors have
diff --git a/target/hppa/cpu.h b/target/hppa/cpu.h
index 7be4a1d3800..f289843c299 100644
--- a/target/hppa/cpu.h
+++ b/target/hppa/cpu.h
@@ -45,8 +45,6 @@
 #define PRIV_KERNEL       0
 #define PRIV_USER         3
 
-#define TARGET_INSN_START_EXTRA_WORDS 2
-
 /* No need to flush MMU_ABS*_IDX  */
 #define HPPA_MMU_FLUSH_MASK                             \
         (1 << MMU_KERNEL_IDX | 1 << MMU_KERNEL_P_IDX |  \
diff --git a/target/i386/cpu-param.h b/target/i386/cpu-param.h
index b0e884c5d70..0c8efce8619 100644
--- a/target/i386/cpu-param.h
+++ b/target/i386/cpu-param.h
@@ -22,6 +22,8 @@
 #endif
 #define TARGET_PAGE_BITS 12
 
+#define TARGET_INSN_START_EXTRA_WORDS 1
+
 /* The x86 has a strong memory model with some store-after-load re-ordering */
 #define TCG_GUEST_DEFAULT_MO      (TCG_MO_ALL & ~TCG_MO_ST_LD)
 
diff --git a/target/i386/cpu.h b/target/i386/cpu.h
index 76f24446a55..f2cae1b066e 100644
--- a/target/i386/cpu.h
+++ b/target/i386/cpu.h
@@ -1610,8 +1610,6 @@ typedef struct {
 #define MAX_FIXED_COUNTERS 3
 #define MAX_GP_COUNTERS    (MSR_IA32_PERF_STATUS - MSR_P6_EVNTSEL0)
 
-#define TARGET_INSN_START_EXTRA_WORDS 1
-
 #define NB_OPMASK_REGS 8
 
 /* CPU can't have 0xFFFFFFFF APIC ID, use that value to distinguish
diff --git a/target/m68k/cpu-param.h b/target/m68k/cpu-param.h
index 7afbf6d302d..256a2b5f8b2 100644
--- a/target/m68k/cpu-param.h
+++ b/target/m68k/cpu-param.h
@@ -17,4 +17,6 @@
 #define TARGET_PHYS_ADDR_SPACE_BITS 32
 #define TARGET_VIRT_ADDR_SPACE_BITS 32
 
+#define TARGET_INSN_START_EXTRA_WORDS 1
+
 #endif
diff --git a/target/m68k/cpu.h b/target/m68k/cpu.h
index ddb0f29f4a3..b6cc38f700e 100644
--- a/target/m68k/cpu.h
+++ b/target/m68k/cpu.h
@@ -76,8 +76,6 @@
 #define M68K_MAX_TTR 2
 #define TTR(type, index) ttr[((type & ACCESS_CODE) == ACCESS_CODE) * 2 + index]
 
-#define TARGET_INSN_START_EXTRA_WORDS 1
-
 typedef CPU_LDoubleU FPReg;
 
 typedef struct CPUArchState {
diff --git a/target/microblaze/cpu-param.h b/target/microblaze/cpu-param.h
index c866ec6c149..5d55e0e3c4a 100644
--- a/target/microblaze/cpu-param.h
+++ b/target/microblaze/cpu-param.h
@@ -27,6 +27,8 @@
 /* FIXME: MB uses variable pages down to 1K but linux only uses 4k.  */
 #define TARGET_PAGE_BITS 12
 
+#define TARGET_INSN_START_EXTRA_WORDS 1
+
 /* MicroBlaze is always in-order. */
 #define TCG_GUEST_DEFAULT_MO  TCG_MO_ALL
 
diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h
index e44ddd53078..552e9646e95 100644
--- a/target/microblaze/cpu.h
+++ b/target/microblaze/cpu.h
@@ -231,8 +231,6 @@ typedef struct CPUArchState CPUMBState;
 #define STREAM_CONTROL   (1 << 3)
 #define STREAM_NONBLOCK  (1 << 4)
 
-#define TARGET_INSN_START_EXTRA_WORDS 1
-
 /* use-non-secure property masks */
 #define USE_NON_SECURE_M_AXI_DP_MASK 0x1
 #define USE_NON_SECURE_M_AXI_IP_MASK 0x2
diff --git a/target/mips/cpu-param.h b/target/mips/cpu-param.h
index 11b3ac0ac63..b953f993b25 100644
--- a/target/mips/cpu-param.h
+++ b/target/mips/cpu-param.h
@@ -25,6 +25,8 @@
 #define TARGET_PAGE_BITS_MIN 12
 #endif
 
+#define TARGET_INSN_START_EXTRA_WORDS 2
+
 #define TCG_GUEST_DEFAULT_MO (0)
 
 #endif
diff --git a/target/mips/cpu.h b/target/mips/cpu.h
index f6877ece8b4..6545f0b4cd4 100644
--- a/target/mips/cpu.h
+++ b/target/mips/cpu.h
@@ -98,8 +98,6 @@ struct CPUMIPSFPUContext {
 #define FP_UNIMPLEMENTED  32
 };
 
-#define TARGET_INSN_START_EXTRA_WORDS 2
-
 typedef struct CPUMIPSMVPContext CPUMIPSMVPContext;
 struct CPUMIPSMVPContext {
     int32_t CP0_MVPControl;
diff --git a/target/openrisc/cpu-param.h b/target/openrisc/cpu-param.h
index 37627f2c394..7ea0ecb55a6 100644
--- a/target/openrisc/cpu-param.h
+++ b/target/openrisc/cpu-param.h
@@ -12,6 +12,8 @@
 #define TARGET_PHYS_ADDR_SPACE_BITS 32
 #define TARGET_VIRT_ADDR_SPACE_BITS 32
 
+#define TARGET_INSN_START_EXTRA_WORDS 1
+
 #define TCG_GUEST_DEFAULT_MO (0)
 
 #endif
diff --git a/target/openrisc/cpu.h b/target/openrisc/cpu.h
index b97d2ffdd26..ae6d6a77910 100644
--- a/target/openrisc/cpu.h
+++ b/target/openrisc/cpu.h
@@ -38,8 +38,6 @@ struct OpenRISCCPUClass {
     ResettablePhases parent_phases;
 };
 
-#define TARGET_INSN_START_EXTRA_WORDS 1
-
 enum {
     MMU_NOMMU_IDX = 0,
     MMU_SUPERVISOR_IDX = 1,
diff --git a/target/riscv/cpu-param.h b/target/riscv/cpu-param.h
index fba30e966a8..ff4ba81965a 100644
--- a/target/riscv/cpu-param.h
+++ b/target/riscv/cpu-param.h
@@ -16,6 +16,14 @@
 # define TARGET_VIRT_ADDR_SPACE_BITS 32 /* sv32 */
 #endif
 #define TARGET_PAGE_BITS 12 /* 4 KiB Pages */
+
+/*
+ * RISC-V-specific extra insn start words:
+ * 1: Original instruction opcode
+ * 2: more information about instruction
+ */
+#define TARGET_INSN_START_EXTRA_WORDS 2
+
 /*
  * The current MMU Modes are:
  *  - U mode 0b000
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 7de19b41836..b432e31fb6d 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -43,12 +43,6 @@ typedef struct CPUArchState CPURISCVState;
 # define TYPE_RISCV_CPU_BASE            TYPE_RISCV_CPU_BASE64
 #endif
 
-/*
- * RISC-V-specific extra insn start words:
- * 1: Original instruction opcode
- * 2: more information about instruction
- */
-#define TARGET_INSN_START_EXTRA_WORDS 2
 /*
  * b0: Whether a instruction always raise a store AMO or not.
  */
diff --git a/target/s390x/cpu-param.h b/target/s390x/cpu-param.h
index 5c331ec424c..a8a4377f4ff 100644
--- a/target/s390x/cpu-param.h
+++ b/target/s390x/cpu-param.h
@@ -12,6 +12,8 @@
 #define TARGET_PHYS_ADDR_SPACE_BITS 64
 #define TARGET_VIRT_ADDR_SPACE_BITS 64
 
+#define TARGET_INSN_START_EXTRA_WORDS 2
+
 /*
  * The z/Architecture has a strong memory model with some
  * store-after-load re-ordering.
diff --git a/target/s390x/cpu.h b/target/s390x/cpu.h
index 5b7992deda6..057c33e0225 100644
--- a/target/s390x/cpu.h
+++ b/target/s390x/cpu.h
@@ -35,8 +35,6 @@
 
 #define TARGET_HAS_PRECISE_SMC
 
-#define TARGET_INSN_START_EXTRA_WORDS 2
-
 #define MMU_USER_IDX 0
 
 #define S390_MAX_CPUS 248
diff --git a/target/sh4/cpu-param.h b/target/sh4/cpu-param.h
index 2b6e11dd0ac..f328715ee86 100644
--- a/target/sh4/cpu-param.h
+++ b/target/sh4/cpu-param.h
@@ -16,4 +16,6 @@
 # define TARGET_VIRT_ADDR_SPACE_BITS 32
 #endif
 
+#define TARGET_INSN_START_EXTRA_WORDS 1
+
 #endif
diff --git a/target/sh4/cpu.h b/target/sh4/cpu.h
index d536d5d7154..3ece180ff63 100644
--- a/target/sh4/cpu.h
+++ b/target/sh4/cpu.h
@@ -125,8 +125,6 @@ typedef struct tlb_t {
 #define UTLB_SIZE 64
 #define ITLB_SIZE 4
 
-#define TARGET_INSN_START_EXTRA_WORDS 1
-
 enum sh_features {
     SH_FEATURE_SH4A = 1,
     SH_FEATURE_BCR3_AND_BCR4 = 2,
diff --git a/target/sparc/cpu-param.h b/target/sparc/cpu-param.h
index 6952ee2b826..62d47b804bb 100644
--- a/target/sparc/cpu-param.h
+++ b/target/sparc/cpu-param.h
@@ -21,6 +21,8 @@
 # define TARGET_VIRT_ADDR_SPACE_BITS 32
 #endif
 
+#define TARGET_INSN_START_EXTRA_WORDS 1
+
 /*
  * From Oracle SPARC Architecture 2015:
  *
diff --git a/target/sparc/cpu.h b/target/sparc/cpu.h
index 462bcb6c0e6..d5e8378e6c0 100644
--- a/target/sparc/cpu.h
+++ b/target/sparc/cpu.h
@@ -221,7 +221,6 @@ typedef struct trap_state {
     uint32_t tt;
 } trap_state;
 #endif
-#define TARGET_INSN_START_EXTRA_WORDS 1
 
 typedef struct sparc_def_t {
     const char *name;
-- 
2.47.1

[PATCH-for-10.1 02/12] tcg: Always define TARGET_INSN_START_EXTRA_WORDS

[Philippe Mathieu-Daudé]

Do not define TARGET_INSN_START_EXTRA_WORDS under the
hood, have each target explicitly define it.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
 include/tcg/insn-start-words.h | 4 ----
 include/tcg/tcg-op.h           | 2 +-
 target/alpha/cpu-param.h       | 2 ++
 target/avr/cpu-param.h         | 2 ++
 target/hexagon/cpu-param.h     | 2 ++
 target/loongarch/cpu-param.h   | 2 ++
 target/ppc/cpu-param.h         | 2 ++
 target/rx/cpu-param.h          | 2 ++
 target/tricore/cpu-param.h     | 2 ++
 target/xtensa/cpu-param.h      | 2 ++
 10 files changed, 17 insertions(+), 5 deletions(-)

diff --git a/include/tcg/insn-start-words.h b/include/tcg/insn-start-words.h
index 50c18bd326d..394c191da8d 100644
--- a/include/tcg/insn-start-words.h
+++ b/include/tcg/insn-start-words.h
@@ -8,10 +8,6 @@
 
 #include "cpu.h"
 
-#ifndef TARGET_INSN_START_EXTRA_WORDS
-# define TARGET_INSN_START_WORDS 1
-#else
 # define TARGET_INSN_START_WORDS (1 + TARGET_INSN_START_EXTRA_WORDS)
-#endif
 
 #endif /* TARGET_INSN_START_WORDS */
diff --git a/include/tcg/tcg-op.h b/include/tcg/tcg-op.h
index a02850583bd..5dfddf995d6 100644
--- a/include/tcg/tcg-op.h
+++ b/include/tcg/tcg-op.h
@@ -22,7 +22,7 @@
 # error
 #endif
 
-#ifndef TARGET_INSN_START_EXTRA_WORDS
+#if TARGET_INSN_START_EXTRA_WORDS == 0
 static inline void tcg_gen_insn_start(target_ulong pc)
 {
     TCGOp *op = tcg_emit_op(INDEX_op_insn_start, 64 / TCG_TARGET_REG_BITS);
diff --git a/target/alpha/cpu-param.h b/target/alpha/cpu-param.h
index ff06e41497a..c89d3ad52b6 100644
--- a/target/alpha/cpu-param.h
+++ b/target/alpha/cpu-param.h
@@ -25,6 +25,8 @@
 # define TARGET_VIRT_ADDR_SPACE_BITS  (30 + TARGET_PAGE_BITS)
 #endif
 
+#define TARGET_INSN_START_EXTRA_WORDS 0
+
 /* Alpha processors have a weak memory model */
 #define TCG_GUEST_DEFAULT_MO      (0)
 
diff --git a/target/avr/cpu-param.h b/target/avr/cpu-param.h
index 81f3f49ee1f..0417f8dcccb 100644
--- a/target/avr/cpu-param.h
+++ b/target/avr/cpu-param.h
@@ -31,6 +31,8 @@
 #define TARGET_PHYS_ADDR_SPACE_BITS 24
 #define TARGET_VIRT_ADDR_SPACE_BITS 24
 
+#define TARGET_INSN_START_EXTRA_WORDS 0
+
 #define TCG_GUEST_DEFAULT_MO 0
 
 #endif
diff --git a/target/hexagon/cpu-param.h b/target/hexagon/cpu-param.h
index 45ee7b46409..635d509e743 100644
--- a/target/hexagon/cpu-param.h
+++ b/target/hexagon/cpu-param.h
@@ -23,4 +23,6 @@
 #define TARGET_PHYS_ADDR_SPACE_BITS 36
 #define TARGET_VIRT_ADDR_SPACE_BITS 32
 
+#define TARGET_INSN_START_EXTRA_WORDS 0
+
 #endif
diff --git a/target/loongarch/cpu-param.h b/target/loongarch/cpu-param.h
index 52437946e56..dbe414bb35a 100644
--- a/target/loongarch/cpu-param.h
+++ b/target/loongarch/cpu-param.h
@@ -13,6 +13,8 @@
 
 #define TARGET_PAGE_BITS 12
 
+#define TARGET_INSN_START_EXTRA_WORDS 0
+
 #define TCG_GUEST_DEFAULT_MO (0)
 
 #endif
diff --git a/target/ppc/cpu-param.h b/target/ppc/cpu-param.h
index 6c4525fdf3c..9cb26cefd5d 100644
--- a/target/ppc/cpu-param.h
+++ b/target/ppc/cpu-param.h
@@ -38,6 +38,8 @@
 # define TARGET_PAGE_BITS 12
 #endif
 
+#define TARGET_INSN_START_EXTRA_WORDS 0
+
 #define TCG_GUEST_DEFAULT_MO 0
 
 #endif
diff --git a/target/rx/cpu-param.h b/target/rx/cpu-param.h
index ef1970a09e9..84934f3bcaf 100644
--- a/target/rx/cpu-param.h
+++ b/target/rx/cpu-param.h
@@ -24,4 +24,6 @@
 #define TARGET_PHYS_ADDR_SPACE_BITS 32
 #define TARGET_VIRT_ADDR_SPACE_BITS 32
 
+#define TARGET_INSN_START_EXTRA_WORDS 0
+
 #endif
diff --git a/target/tricore/cpu-param.h b/target/tricore/cpu-param.h
index 790242ef3d2..eb33a67c419 100644
--- a/target/tricore/cpu-param.h
+++ b/target/tricore/cpu-param.h
@@ -12,4 +12,6 @@
 #define TARGET_PHYS_ADDR_SPACE_BITS 32
 #define TARGET_VIRT_ADDR_SPACE_BITS 32
 
+#define TARGET_INSN_START_EXTRA_WORDS 0
+
 #endif
diff --git a/target/xtensa/cpu-param.h b/target/xtensa/cpu-param.h
index 5e4848ad059..e7cb747aaae 100644
--- a/target/xtensa/cpu-param.h
+++ b/target/xtensa/cpu-param.h
@@ -16,6 +16,8 @@
 #define TARGET_VIRT_ADDR_SPACE_BITS 32
 #endif
 
+#define TARGET_INSN_START_EXTRA_WORDS 0
+
 /* Xtensa processors have a weak memory model */
 #define TCG_GUEST_DEFAULT_MO      (0)
 
-- 
2.47.1

[PATCH-for-10.1 03/12] tcg: Have tcg_gen_insn_start() take uint64_t arguments

[Philippe Mathieu-Daudé]

Since restore_state_to_opc()'s rework in commits d29256896..04f105758
and TCGContext::gen_insn_data[] widened in commit c9ad8d27caa ("tcg:
Widen gen_insn_data to uint64_t"), tcg_set_insn_start_param()'s 3rd
argument is uint64_t, not target_ulong. Use the same type signature
for tcg_gen_insn_start().

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
 include/tcg/tcg-op.h      | 7 +++----
 accel/tcg/translate-all.c | 2 +-
 2 files changed, 4 insertions(+), 5 deletions(-)

diff --git a/include/tcg/tcg-op.h b/include/tcg/tcg-op.h
index 5dfddf995d6..8938f386599 100644
--- a/include/tcg/tcg-op.h
+++ b/include/tcg/tcg-op.h
@@ -23,21 +23,20 @@
 #endif
 
 #if TARGET_INSN_START_EXTRA_WORDS == 0
-static inline void tcg_gen_insn_start(target_ulong pc)
+static inline void tcg_gen_insn_start(uint64_t pc)
 {
     TCGOp *op = tcg_emit_op(INDEX_op_insn_start, 64 / TCG_TARGET_REG_BITS);
     tcg_set_insn_start_param(op, 0, pc);
 }
 #elif TARGET_INSN_START_EXTRA_WORDS == 1
-static inline void tcg_gen_insn_start(target_ulong pc, target_ulong a1)
+static inline void tcg_gen_insn_start(uint64_t pc, uint64_t a1)
 {
     TCGOp *op = tcg_emit_op(INDEX_op_insn_start, 2 * 64 / TCG_TARGET_REG_BITS);
     tcg_set_insn_start_param(op, 0, pc);
     tcg_set_insn_start_param(op, 1, a1);
 }
 #elif TARGET_INSN_START_EXTRA_WORDS == 2
-static inline void tcg_gen_insn_start(target_ulong pc, target_ulong a1,
-                                      target_ulong a2)
+static inline void tcg_gen_insn_start(uint64_t pc, uint64_t a1, uint64_t a2)
 {
     TCGOp *op = tcg_emit_op(INDEX_op_insn_start, 3 * 64 / TCG_TARGET_REG_BITS);
     tcg_set_insn_start_param(op, 0, pc);
diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c
index 82bc16bd535..a857aefd756 100644
--- a/accel/tcg/translate-all.c
+++ b/accel/tcg/translate-all.c
@@ -117,7 +117,7 @@ static int64_t decode_sleb128(const uint8_t **pp)
 /* Encode the data collected about the instructions while compiling TB.
    Place the data at BLOCK, and return the number of bytes consumed.
 
-   The logical table consists of TARGET_INSN_START_WORDS target_ulong's,
+   The logical table consists of TARGET_INSN_START_WORDS uint64_t's,
    which come from the target's insn_start data, followed by a uintptr_t
    which comes from the host pc of the end of the code implementing the insn.
 
-- 
2.47.1

[PATCH-for-10.1 04/12] tcg: Declare local 'insn_start_words' variable in tcg_gen_insn_start()

[Philippe Mathieu-Daudé]

In order to keep following commits simple, introduce the
'insn_start_words' local variable in tcg_gen_insn_start().

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
 include/tcg/tcg-op.h | 15 ++++++++++++---
 1 file changed, 12 insertions(+), 3 deletions(-)

diff --git a/include/tcg/tcg-op.h b/include/tcg/tcg-op.h
index 8938f386599..e0038e70a8d 100644
--- a/include/tcg/tcg-op.h
+++ b/include/tcg/tcg-op.h
@@ -25,20 +25,29 @@
 #if TARGET_INSN_START_EXTRA_WORDS == 0
 static inline void tcg_gen_insn_start(uint64_t pc)
 {
-    TCGOp *op = tcg_emit_op(INDEX_op_insn_start, 64 / TCG_TARGET_REG_BITS);
+    unsigned insn_start_words = 1;
+    TCGOp *op = tcg_emit_op(INDEX_op_insn_start,
+                            insn_start_words * 64 / TCG_TARGET_REG_BITS);
+
     tcg_set_insn_start_param(op, 0, pc);
 }
 #elif TARGET_INSN_START_EXTRA_WORDS == 1
 static inline void tcg_gen_insn_start(uint64_t pc, uint64_t a1)
 {
-    TCGOp *op = tcg_emit_op(INDEX_op_insn_start, 2 * 64 / TCG_TARGET_REG_BITS);
+    unsigned insn_start_words = 1 + TARGET_INSN_START_EXTRA_WORDS;
+    TCGOp *op = tcg_emit_op(INDEX_op_insn_start,
+                            insn_start_words * 64 / TCG_TARGET_REG_BITS);
+
     tcg_set_insn_start_param(op, 0, pc);
     tcg_set_insn_start_param(op, 1, a1);
 }
 #elif TARGET_INSN_START_EXTRA_WORDS == 2
 static inline void tcg_gen_insn_start(uint64_t pc, uint64_t a1, uint64_t a2)
 {
-    TCGOp *op = tcg_emit_op(INDEX_op_insn_start, 3 * 64 / TCG_TARGET_REG_BITS);
+    unsigned insn_start_words = 1 + TARGET_INSN_START_EXTRA_WORDS;
+    TCGOp *op = tcg_emit_op(INDEX_op_insn_start,
+                            insn_start_words * 64 / TCG_TARGET_REG_BITS);
+
     tcg_set_insn_start_param(op, 0, pc);
     tcg_set_insn_start_param(op, 1, a1);
     tcg_set_insn_start_param(op, 2, a2);
-- 
2.47.1

[PATCH-for-10.1 05/12] tcg: Use TCGContext::insn_start_words in tcg_gen_insn_start()

[Philippe Mathieu-Daudé]

In tb_gen_code() we set TCGContext::insn_start_words to
TARGET_INSN_START_WORDS:

290 TranslationBlock *tb_gen_code(...)
293 {
...
351     tcg_ctx->insn_start_words = TARGET_INSN_START_WORDS;

This definition is expanded to:

 11 # define TARGET_INSN_START_WORDS (1 + TARGET_INSN_START_EXTRA_WORDS)

Directly use the identical tcg_ctx->insn_start_words variable.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
 include/tcg/tcg-op.h | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/include/tcg/tcg-op.h b/include/tcg/tcg-op.h
index e0038e70a8d..1f0d3b95304 100644
--- a/include/tcg/tcg-op.h
+++ b/include/tcg/tcg-op.h
@@ -25,7 +25,7 @@
 #if TARGET_INSN_START_EXTRA_WORDS == 0
 static inline void tcg_gen_insn_start(uint64_t pc)
 {
-    unsigned insn_start_words = 1;
+    unsigned insn_start_words = tcg_ctx->insn_start_words;
     TCGOp *op = tcg_emit_op(INDEX_op_insn_start,
                             insn_start_words * 64 / TCG_TARGET_REG_BITS);
 
@@ -34,7 +34,7 @@ static inline void tcg_gen_insn_start(uint64_t pc)
 #elif TARGET_INSN_START_EXTRA_WORDS == 1
 static inline void tcg_gen_insn_start(uint64_t pc, uint64_t a1)
 {
-    unsigned insn_start_words = 1 + TARGET_INSN_START_EXTRA_WORDS;
+    unsigned insn_start_words = tcg_ctx->insn_start_words;
     TCGOp *op = tcg_emit_op(INDEX_op_insn_start,
                             insn_start_words * 64 / TCG_TARGET_REG_BITS);
 
@@ -44,7 +44,7 @@ static inline void tcg_gen_insn_start(uint64_t pc, uint64_t a1)
 #elif TARGET_INSN_START_EXTRA_WORDS == 2
 static inline void tcg_gen_insn_start(uint64_t pc, uint64_t a1, uint64_t a2)
 {
-    unsigned insn_start_words = 1 + TARGET_INSN_START_EXTRA_WORDS;
+    unsigned insn_start_words = tcg_ctx->insn_start_words;
     TCGOp *op = tcg_emit_op(INDEX_op_insn_start,
                             insn_start_words * 64 / TCG_TARGET_REG_BITS);
 
-- 
2.47.1

[PATCH-for-10.1 06/12] tcg: Use TCGContext::insn_start_words in translate-all.c methods

[Philippe Mathieu-Daudé]

Replace TARGET_INSN_START_WORDS -> tcg_ctx->insn_start_words
(see previous commit for justification).

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
 accel/tcg/translate-all.c | 17 ++++++++++-------
 1 file changed, 10 insertions(+), 7 deletions(-)

diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c
index a857aefd756..54bba995a04 100644
--- a/accel/tcg/translate-all.c
+++ b/accel/tcg/translate-all.c
@@ -131,19 +131,20 @@ static int encode_search(TranslationBlock *tb, uint8_t *block)
     uint8_t *highwater = tcg_ctx->code_gen_highwater;
     uint64_t *insn_data = tcg_ctx->gen_insn_data;
     uint16_t *insn_end_off = tcg_ctx->gen_insn_end_off;
+    unsigned insn_start_words = tcg_ctx->insn_start_words;
     uint8_t *p = block;
     int i, j, n;
 
     for (i = 0, n = tb->icount; i < n; ++i) {
         uint64_t prev, curr;
 
-        for (j = 0; j < TARGET_INSN_START_WORDS; ++j) {
+        for (j = 0; j < insn_start_words; ++j) {
             if (i == 0) {
                 prev = (!(tb_cflags(tb) & CF_PCREL) && j == 0 ? tb->pc : 0);
             } else {
-                prev = insn_data[(i - 1) * TARGET_INSN_START_WORDS + j];
+                prev = insn_data[(i - 1) * insn_start_words + j];
             }
-            curr = insn_data[i * TARGET_INSN_START_WORDS + j];
+            curr = insn_data[i * insn_start_words + j];
             p = encode_sleb128(p, curr - prev);
         }
         prev = (i == 0 ? 0 : insn_end_off[i - 1]);
@@ -167,6 +168,7 @@ static int cpu_unwind_data_from_tb(TranslationBlock *tb, uintptr_t host_pc,
 {
     uintptr_t iter_pc = (uintptr_t)tb->tc.ptr;
     const uint8_t *p = tb->tc.ptr + tb->tc.size;
+    unsigned insn_start_words = tcg_ctx->insn_start_words;
     int i, j, num_insns = tb->icount;
 
     host_pc -= GETPC_ADJ;
@@ -175,7 +177,7 @@ static int cpu_unwind_data_from_tb(TranslationBlock *tb, uintptr_t host_pc,
         return -1;
     }
 
-    memset(data, 0, sizeof(uint64_t) * TARGET_INSN_START_WORDS);
+    memset(data, 0, sizeof(uint64_t) * insn_start_words);
     if (!(tb_cflags(tb) & CF_PCREL)) {
         data[0] = tb->pc;
     }
@@ -185,7 +187,7 @@ static int cpu_unwind_data_from_tb(TranslationBlock *tb, uintptr_t host_pc,
      * at which the end of the insn exceeds host_pc.
      */
     for (i = 0; i < num_insns; ++i) {
-        for (j = 0; j < TARGET_INSN_START_WORDS; ++j) {
+        for (j = 0; j < insn_start_words; ++j) {
             data[j] += decode_sleb128(&p);
         }
         iter_pc += decode_sleb128(&p);
@@ -443,6 +445,7 @@ TranslationBlock *tb_gen_code(CPUState *cpu,
         if (logfile) {
             int code_size, data_size;
             const tcg_target_ulong *rx_data_gen_ptr;
+            unsigned insn_start_words = tcg_ctx->insn_start_words;
             size_t chunk_start;
             int insn = 0;
 
@@ -460,7 +463,7 @@ TranslationBlock *tb_gen_code(CPUState *cpu,
             fprintf(logfile, "OUT: [size=%d]\n", gen_code_size);
             fprintf(logfile,
                     "  -- guest addr 0x%016" PRIx64 " + tb prologue\n",
-                    tcg_ctx->gen_insn_data[insn * TARGET_INSN_START_WORDS]);
+                    tcg_ctx->gen_insn_data[insn * insn_start_words]);
             chunk_start = tcg_ctx->gen_insn_end_off[insn];
             disas(logfile, tb->tc.ptr, chunk_start);
 
@@ -473,7 +476,7 @@ TranslationBlock *tb_gen_code(CPUState *cpu,
                 size_t chunk_end = tcg_ctx->gen_insn_end_off[insn];
                 if (chunk_end > chunk_start) {
                     fprintf(logfile, "  -- guest addr 0x%016" PRIx64 "\n",
-                            tcg_ctx->gen_insn_data[insn * TARGET_INSN_START_WORDS]);
+                            tcg_ctx->gen_insn_data[insn * insn_start_words]);
                     disas(logfile, tb->tc.ptr + chunk_start,
                           chunk_end - chunk_start);
                     chunk_start = chunk_end;
-- 
2.47.1

[PATCH-for-10.1 07/12] tcg: Check TARGET_INSN_START_EXTRA_WORDS range at runtime

[Philippe Mathieu-Daudé]

Define TARGET_INSN_START_WORDS_MAX and use it to check
TARGET_INSN_START_EXTRA_WORDS at runtime in tb_gen_code().

Suggested-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
 include/tcg/tcg-op.h      | 4 +---
 include/tcg/tcg.h         | 2 ++
 accel/tcg/translate-all.c | 2 ++
 3 files changed, 5 insertions(+), 3 deletions(-)

diff --git a/include/tcg/tcg-op.h b/include/tcg/tcg-op.h
index 1f0d3b95304..0915043adf8 100644
--- a/include/tcg/tcg-op.h
+++ b/include/tcg/tcg-op.h
@@ -41,7 +41,7 @@ static inline void tcg_gen_insn_start(uint64_t pc, uint64_t a1)
     tcg_set_insn_start_param(op, 0, pc);
     tcg_set_insn_start_param(op, 1, a1);
 }
-#elif TARGET_INSN_START_EXTRA_WORDS == 2
+#elif TARGET_INSN_START_EXTRA_WORDS >= 2
 static inline void tcg_gen_insn_start(uint64_t pc, uint64_t a1, uint64_t a2)
 {
     unsigned insn_start_words = tcg_ctx->insn_start_words;
@@ -52,8 +52,6 @@ static inline void tcg_gen_insn_start(uint64_t pc, uint64_t a1, uint64_t a2)
     tcg_set_insn_start_param(op, 1, a1);
     tcg_set_insn_start_param(op, 2, a2);
 }
-#else
-#error Unhandled TARGET_INSN_START_EXTRA_WORDS value
 #endif
 
 #if TARGET_LONG_BITS == 32
diff --git a/include/tcg/tcg.h b/include/tcg/tcg.h
index 84d99508b65..92a23e10218 100644
--- a/include/tcg/tcg.h
+++ b/include/tcg/tcg.h
@@ -577,6 +577,8 @@ static inline TCGv_vec temp_tcgv_vec(TCGTemp *t)
     return (TCGv_vec)temp_tcgv_i32(t);
 }
 
+#define TARGET_INSN_START_WORDS_MAX 3
+
 static inline TCGArg tcg_get_insn_param(TCGOp *op, int arg)
 {
     return op->args[arg];
diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c
index 54bba995a04..5e2a89dc474 100644
--- a/accel/tcg/translate-all.c
+++ b/accel/tcg/translate-all.c
@@ -66,6 +66,7 @@
 #include "internal-target.h"
 #include "tcg/perf.h"
 #include "tcg/insn-start-words.h"
+#include "tcg/tcg-op.h"
 
 TBContext tb_ctx;
 
@@ -351,6 +352,7 @@ TranslationBlock *tb_gen_code(CPUState *cpu,
     tcg_ctx->tlb_dyn_max_bits = CPU_TLB_DYN_MAX_BITS;
 #endif
     tcg_ctx->insn_start_words = TARGET_INSN_START_WORDS;
+    tcg_debug_assert(tcg_ctx->insn_start_words <= TARGET_INSN_START_WORDS_MAX);
 #ifdef TCG_GUEST_DEFAULT_MO
     tcg_ctx->guest_mo = TCG_GUEST_DEFAULT_MO;
 #else
-- 
2.47.1

[PATCH-for-10.1 08/12] tcg: Declare arrays using TARGET_INSN_START_WORDS_MAX

[Philippe Mathieu-Daudé]

Prefer the target-agnostic TARGET_INSN_START_WORDS_MAX definition
over the target-specific TARGET_INSN_START_WORDS. The former is
guaranty to hold the latter.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
 accel/tcg/translate-all.c    | 2 +-
 target/i386/helper.c         | 3 ++-
 target/openrisc/sys_helper.c | 3 ++-
 3 files changed, 5 insertions(+), 3 deletions(-)

diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c
index 5e2a89dc474..2f8cf6db144 100644
--- a/accel/tcg/translate-all.c
+++ b/accel/tcg/translate-all.c
@@ -206,7 +206,7 @@ static int cpu_unwind_data_from_tb(TranslationBlock *tb, uintptr_t host_pc,
 void cpu_restore_state_from_tb(CPUState *cpu, TranslationBlock *tb,
                                uintptr_t host_pc)
 {
-    uint64_t data[TARGET_INSN_START_WORDS];
+    uint64_t data[TARGET_INSN_START_WORDS_MAX];
     int insns_left = cpu_unwind_data_from_tb(tb, host_pc, data);
 
     if (insns_left < 0) {
diff --git a/target/i386/helper.c b/target/i386/helper.c
index c07b1b16ea1..90e113c8b5a 100644
--- a/target/i386/helper.c
+++ b/target/i386/helper.c
@@ -31,6 +31,7 @@
 #include "qemu/log.h"
 #ifdef CONFIG_TCG
 #include "tcg/insn-start-words.h"
+#include "tcg/tcg.h"
 #endif
 
 void cpu_sync_avx_hflag(CPUX86State *env)
@@ -524,7 +525,7 @@ void cpu_x86_inject_mce(Monitor *mon, X86CPU *cpu, int bank,
 static inline target_ulong get_memio_eip(CPUX86State *env)
 {
 #ifdef CONFIG_TCG
-    uint64_t data[TARGET_INSN_START_WORDS];
+    uint64_t data[TARGET_INSN_START_WORDS_MAX];
     CPUState *cs = env_cpu(env);
 
     if (!cpu_unwind_state_data(cs, cs->mem_io_pc, data)) {
diff --git a/target/openrisc/sys_helper.c b/target/openrisc/sys_helper.c
index 21bc137ccca..cf521461954 100644
--- a/target/openrisc/sys_helper.c
+++ b/target/openrisc/sys_helper.c
@@ -28,6 +28,7 @@
 #include "hw/boards.h"
 #endif
 #include "tcg/insn-start-words.h"
+#include "tcg/tcg.h"
 
 #define TO_SPR(group, number) (((group) << 11) + (number))
 
@@ -218,7 +219,7 @@ target_ulong HELPER(mfspr)(CPUOpenRISCState *env, target_ulong rd,
 {
     OpenRISCCPU *cpu = env_archcpu(env);
 #ifndef CONFIG_USER_ONLY
-    uint64_t data[TARGET_INSN_START_WORDS];
+    uint64_t data[TARGET_INSN_START_WORDS_MAX];
     MachineState *ms = MACHINE(qdev_get_machine());
     CPUState *cs = env_cpu(env);
     int idx;
-- 
2.47.1

[PATCH-for-10.1 09/12] tcg: Restrict TARGET_INSN_START_WORDS definition to translate-all.c

[Philippe Mathieu-Daudé]

TARGET_INSN_START_WORDS is now only used within translate-all.c,
move its declaration there.
"tcg/insn-start-words.h" header being now empty, remove it.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
 include/tcg/insn-start-words.h | 13 -------------
 accel/tcg/translate-all.c      |  3 ++-
 target/i386/helper.c           |  1 -
 target/openrisc/sys_helper.c   |  1 -
 4 files changed, 2 insertions(+), 16 deletions(-)
 delete mode 100644 include/tcg/insn-start-words.h

diff --git a/include/tcg/insn-start-words.h b/include/tcg/insn-start-words.h
deleted file mode 100644
index 394c191da8d..00000000000
--- a/include/tcg/insn-start-words.h
+++ /dev/null
@@ -1,13 +0,0 @@
-/* SPDX-License-Identifier: MIT */
-/*
- * Define TARGET_INSN_START_WORDS
- * Copyright (c) 2008 Fabrice Bellard
- */
-
-#ifndef TARGET_INSN_START_WORDS
-
-#include "cpu.h"
-
-# define TARGET_INSN_START_WORDS (1 + TARGET_INSN_START_EXTRA_WORDS)
-
-#endif /* TARGET_INSN_START_WORDS */
diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c
index 2f8cf6db144..fc55a75a3cf 100644
--- a/accel/tcg/translate-all.c
+++ b/accel/tcg/translate-all.c
@@ -65,11 +65,12 @@
 #include "internal-common.h"
 #include "internal-target.h"
 #include "tcg/perf.h"
-#include "tcg/insn-start-words.h"
 #include "tcg/tcg-op.h"
 
 TBContext tb_ctx;
 
+#define TARGET_INSN_START_WORDS     (1 + TARGET_INSN_START_EXTRA_WORDS)
+
 /*
  * Encode VAL as a signed leb128 sequence at P.
  * Return P incremented past the encoded value.
diff --git a/target/i386/helper.c b/target/i386/helper.c
index 90e113c8b5a..1f819fbff65 100644
--- a/target/i386/helper.c
+++ b/target/i386/helper.c
@@ -30,7 +30,6 @@
 #endif
 #include "qemu/log.h"
 #ifdef CONFIG_TCG
-#include "tcg/insn-start-words.h"
 #include "tcg/tcg.h"
 #endif
 
diff --git a/target/openrisc/sys_helper.c b/target/openrisc/sys_helper.c
index cf521461954..9da2bebbd5b 100644
--- a/target/openrisc/sys_helper.c
+++ b/target/openrisc/sys_helper.c
@@ -27,7 +27,6 @@
 #ifndef CONFIG_USER_ONLY
 #include "hw/boards.h"
 #endif
-#include "tcg/insn-start-words.h"
 #include "tcg/tcg.h"
 
 #define TO_SPR(group, number) (((group) << 11) + (number))
-- 
2.47.1

[PATCH-for-10.1 10/12] tcg: Unify tcg_gen_insn_start() to handle 1 or 2 arguments

[Philippe Mathieu-Daudé]

Merge the tcg_gen_insn_start() definition using 1 extra word
with the definition using 2, using a2=0 in callers.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
 include/tcg/tcg-op.h          | 16 ++++------------
 target/i386/tcg/translate.c   |  2 +-
 target/m68k/translate.c       |  2 +-
 target/microblaze/translate.c |  2 +-
 target/openrisc/translate.c   |  2 +-
 target/sh4/translate.c        |  2 +-
 target/sparc/translate.c      |  2 +-
 7 files changed, 10 insertions(+), 18 deletions(-)

diff --git a/include/tcg/tcg-op.h b/include/tcg/tcg-op.h
index 0915043adf8..df234d4e1e0 100644
--- a/include/tcg/tcg-op.h
+++ b/include/tcg/tcg-op.h
@@ -31,17 +31,7 @@ static inline void tcg_gen_insn_start(uint64_t pc)
 
     tcg_set_insn_start_param(op, 0, pc);
 }
-#elif TARGET_INSN_START_EXTRA_WORDS == 1
-static inline void tcg_gen_insn_start(uint64_t pc, uint64_t a1)
-{
-    unsigned insn_start_words = tcg_ctx->insn_start_words;
-    TCGOp *op = tcg_emit_op(INDEX_op_insn_start,
-                            insn_start_words * 64 / TCG_TARGET_REG_BITS);
-
-    tcg_set_insn_start_param(op, 0, pc);
-    tcg_set_insn_start_param(op, 1, a1);
-}
-#elif TARGET_INSN_START_EXTRA_WORDS >= 2
+#elif TARGET_INSN_START_EXTRA_WORDS >= 1
 static inline void tcg_gen_insn_start(uint64_t pc, uint64_t a1, uint64_t a2)
 {
     unsigned insn_start_words = tcg_ctx->insn_start_words;
@@ -50,7 +40,9 @@ static inline void tcg_gen_insn_start(uint64_t pc, uint64_t a1, uint64_t a2)
 
     tcg_set_insn_start_param(op, 0, pc);
     tcg_set_insn_start_param(op, 1, a1);
-    tcg_set_insn_start_param(op, 2, a2);
+    if (insn_start_words > 2) {
+        tcg_set_insn_start_param(op, 2, a2);
+    }
 }
 #endif
 
diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c
index a8935f487aa..0f1e72b1bc0 100644
--- a/target/i386/tcg/translate.c
+++ b/target/i386/tcg/translate.c
@@ -3766,7 +3766,7 @@ static void i386_tr_insn_start(DisasContextBase *dcbase, CPUState *cpu)
     if (tb_cflags(dcbase->tb) & CF_PCREL) {
         pc_arg &= ~TARGET_PAGE_MASK;
     }
-    tcg_gen_insn_start(pc_arg, dc->cc_op);
+    tcg_gen_insn_start(pc_arg, dc->cc_op, 0);
 }
 
 static void i386_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)
diff --git a/target/m68k/translate.c b/target/m68k/translate.c
index dec2967fce4..9f7052aa6b5 100644
--- a/target/m68k/translate.c
+++ b/target/m68k/translate.c
@@ -6037,7 +6037,7 @@ static void m68k_tr_tb_start(DisasContextBase *dcbase, CPUState *cpu)
 static void m68k_tr_insn_start(DisasContextBase *dcbase, CPUState *cpu)
 {
     DisasContext *dc = container_of(dcbase, DisasContext, base);
-    tcg_gen_insn_start(dc->base.pc_next, dc->cc_op);
+    tcg_gen_insn_start(dc->base.pc_next, dc->cc_op, 0);
 }
 
 static void m68k_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)
diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c
index b54e5ac4b2f..d256b317cfb 100644
--- a/target/microblaze/translate.c
+++ b/target/microblaze/translate.c
@@ -1631,7 +1631,7 @@ static void mb_tr_insn_start(DisasContextBase *dcb, CPUState *cs)
 {
     DisasContext *dc = container_of(dcb, DisasContext, base);
 
-    tcg_gen_insn_start(dc->base.pc_next, dc->tb_flags & ~MSR_TB_MASK);
+    tcg_gen_insn_start(dc->base.pc_next, dc->tb_flags & ~MSR_TB_MASK, 0);
 }
 
 static void mb_tr_translate_insn(DisasContextBase *dcb, CPUState *cs)
diff --git a/target/openrisc/translate.c b/target/openrisc/translate.c
index 7a6af183ae2..ff720e7fb6b 100644
--- a/target/openrisc/translate.c
+++ b/target/openrisc/translate.c
@@ -1558,7 +1558,7 @@ static void openrisc_tr_insn_start(DisasContextBase *dcbase, CPUState *cs)
     DisasContext *dc = container_of(dcbase, DisasContext, base);
 
     tcg_gen_insn_start(dc->base.pc_next, (dc->delayed_branch ? 1 : 0)
-                       | (dc->base.num_insns > 1 ? 2 : 0));
+                       | (dc->base.num_insns > 1 ? 2 : 0), 0);
 }
 
 static void openrisc_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs)
diff --git a/target/sh4/translate.c b/target/sh4/translate.c
index bcdd5588183..f140080c08c 100644
--- a/target/sh4/translate.c
+++ b/target/sh4/translate.c
@@ -2248,7 +2248,7 @@ static void sh4_tr_insn_start(DisasContextBase *dcbase, CPUState *cs)
 {
     DisasContext *ctx = container_of(dcbase, DisasContext, base);
 
-    tcg_gen_insn_start(ctx->base.pc_next, ctx->envflags);
+    tcg_gen_insn_start(ctx->base.pc_next, ctx->envflags, 0);
 }
 
 static void sh4_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs)
diff --git a/target/sparc/translate.c b/target/sparc/translate.c
index bfe63649db2..a775f425658 100644
--- a/target/sparc/translate.c
+++ b/target/sparc/translate.c
@@ -5725,7 +5725,7 @@ static void sparc_tr_insn_start(DisasContextBase *dcbase, CPUState *cs)
             g_assert_not_reached();
         }
     }
-    tcg_gen_insn_start(dc->pc, npc);
+    tcg_gen_insn_start(dc->pc, npc, 0);
 }
 
 static void sparc_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs)
-- 
2.47.1

[PATCH-for-10.1 11/12] tcg: Unify tcg_gen_insn_start() to handle 0 or 2 arguments

[Philippe Mathieu-Daudé]

Merge the tcg_gen_insn_start() definition using no extra word
with the definition using 2, using a1=0 and a2=0 in callers.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
 include/tcg/tcg-op.h             | 15 +++------------
 target/alpha/translate.c         |  4 ++--
 target/avr/translate.c           |  2 +-
 target/loongarch/tcg/translate.c |  2 +-
 target/ppc/translate.c           |  2 +-
 target/rx/translate.c            |  2 +-
 target/tricore/translate.c       |  2 +-
 target/xtensa/translate.c        |  2 +-
 8 files changed, 11 insertions(+), 20 deletions(-)

diff --git a/include/tcg/tcg-op.h b/include/tcg/tcg-op.h
index df234d4e1e0..cf177a1fd3b 100644
--- a/include/tcg/tcg-op.h
+++ b/include/tcg/tcg-op.h
@@ -22,16 +22,6 @@
 # error
 #endif
 
-#if TARGET_INSN_START_EXTRA_WORDS == 0
-static inline void tcg_gen_insn_start(uint64_t pc)
-{
-    unsigned insn_start_words = tcg_ctx->insn_start_words;
-    TCGOp *op = tcg_emit_op(INDEX_op_insn_start,
-                            insn_start_words * 64 / TCG_TARGET_REG_BITS);
-
-    tcg_set_insn_start_param(op, 0, pc);
-}
-#elif TARGET_INSN_START_EXTRA_WORDS >= 1
 static inline void tcg_gen_insn_start(uint64_t pc, uint64_t a1, uint64_t a2)
 {
     unsigned insn_start_words = tcg_ctx->insn_start_words;
@@ -39,12 +29,13 @@ static inline void tcg_gen_insn_start(uint64_t pc, uint64_t a1, uint64_t a2)
                             insn_start_words * 64 / TCG_TARGET_REG_BITS);
 
     tcg_set_insn_start_param(op, 0, pc);
-    tcg_set_insn_start_param(op, 1, a1);
+    if (insn_start_words > 1) {
+        tcg_set_insn_start_param(op, 1, a1);
+    }
     if (insn_start_words > 2) {
         tcg_set_insn_start_param(op, 2, a2);
     }
 }
-#endif
 
 #if TARGET_LONG_BITS == 32
 typedef TCGv_i32 TCGv;
diff --git a/target/alpha/translate.c b/target/alpha/translate.c
index 2156c022146..6586ad0a69a 100644
--- a/target/alpha/translate.c
+++ b/target/alpha/translate.c
@@ -2905,9 +2905,9 @@ static void alpha_tr_insn_start(DisasContextBase *dcbase, CPUState *cpu)
     DisasContext *ctx = container_of(dcbase, DisasContext, base);
 
     if (ctx->pcrel) {
-        tcg_gen_insn_start(dcbase->pc_next & ~TARGET_PAGE_MASK);
+        tcg_gen_insn_start(dcbase->pc_next & ~TARGET_PAGE_MASK, 0, 0);
     } else {
-        tcg_gen_insn_start(dcbase->pc_next);
+        tcg_gen_insn_start(dcbase->pc_next, 0, 0);
     }
 }
 
diff --git a/target/avr/translate.c b/target/avr/translate.c
index 4ab71d8138b..c4f1a446467 100644
--- a/target/avr/translate.c
+++ b/target/avr/translate.c
@@ -2686,7 +2686,7 @@ static void avr_tr_insn_start(DisasContextBase *dcbase, CPUState *cs)
 {
     DisasContext *ctx = container_of(dcbase, DisasContext, base);
 
-    tcg_gen_insn_start(ctx->npc);
+    tcg_gen_insn_start(ctx->npc, 0, 0);
 }
 
 static void avr_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs)
diff --git a/target/loongarch/tcg/translate.c b/target/loongarch/tcg/translate.c
index e59e4ed25b1..ee359e804af 100644
--- a/target/loongarch/tcg/translate.c
+++ b/target/loongarch/tcg/translate.c
@@ -158,7 +158,7 @@ static void loongarch_tr_insn_start(DisasContextBase *dcbase, CPUState *cs)
 {
     DisasContext *ctx = container_of(dcbase, DisasContext, base);
 
-    tcg_gen_insn_start(ctx->base.pc_next);
+    tcg_gen_insn_start(ctx->base.pc_next, 0, 0);
 }
 
 /*
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index a52cbc869ae..70458526282 100644
--- a/target/ppc/translate.c
+++ b/target/ppc/translate.c
@@ -6558,7 +6558,7 @@ static void ppc_tr_tb_start(DisasContextBase *db, CPUState *cs)
 
 static void ppc_tr_insn_start(DisasContextBase *dcbase, CPUState *cs)
 {
-    tcg_gen_insn_start(dcbase->pc_next);
+    tcg_gen_insn_start(dcbase->pc_next, 0, 0);
 }
 
 static bool is_prefix_insn(DisasContext *ctx, uint32_t insn)
diff --git a/target/rx/translate.c b/target/rx/translate.c
index bbda703be86..16a865bd40f 100644
--- a/target/rx/translate.c
+++ b/target/rx/translate.c
@@ -2210,7 +2210,7 @@ static void rx_tr_insn_start(DisasContextBase *dcbase, CPUState *cs)
 {
     DisasContext *ctx = container_of(dcbase, DisasContext, base);
 
-    tcg_gen_insn_start(ctx->base.pc_next);
+    tcg_gen_insn_start(ctx->base.pc_next, 0, 0);
 }
 
 static void rx_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs)
diff --git a/target/tricore/translate.c b/target/tricore/translate.c
index 6819b776686..636137a5f73 100644
--- a/target/tricore/translate.c
+++ b/target/tricore/translate.c
@@ -8376,7 +8376,7 @@ static void tricore_tr_insn_start(DisasContextBase *dcbase, CPUState *cpu)
 {
     DisasContext *ctx = container_of(dcbase, DisasContext, base);
 
-    tcg_gen_insn_start(ctx->base.pc_next);
+    tcg_gen_insn_start(ctx->base.pc_next, 0, 0);
 }
 
 static bool insn_crosses_page(CPUTriCoreState *env, DisasContext *ctx)
diff --git a/target/xtensa/translate.c b/target/xtensa/translate.c
index 4f02cefde34..888752f2279 100644
--- a/target/xtensa/translate.c
+++ b/target/xtensa/translate.c
@@ -1159,7 +1159,7 @@ static void xtensa_tr_tb_start(DisasContextBase *dcbase, CPUState *cpu)
 
 static void xtensa_tr_insn_start(DisasContextBase *dcbase, CPUState *cpu)
 {
-    tcg_gen_insn_start(dcbase->pc_next);
+    tcg_gen_insn_start(dcbase->pc_next, 0, 0);
 }
 
 static void xtensa_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)
-- 
2.47.1

[PATCH-for-10.1 12/12] tcg: Uninline tcg_gen_insn_start()

[Philippe Mathieu-Daudé]

tcg_gen_insn_start() is now common to all TCG frontends.
We don't need to keep it inlined, move it to tcg.c.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
 include/tcg/tcg-op.h | 15 ---------------
 include/tcg/tcg.h    |  2 ++
 tcg/tcg.c            | 15 +++++++++++++++
 3 files changed, 17 insertions(+), 15 deletions(-)

diff --git a/include/tcg/tcg-op.h b/include/tcg/tcg-op.h
index cf177a1fd3b..470cb46225e 100644
--- a/include/tcg/tcg-op.h
+++ b/include/tcg/tcg-op.h
@@ -22,21 +22,6 @@
 # error
 #endif
 
-static inline void tcg_gen_insn_start(uint64_t pc, uint64_t a1, uint64_t a2)
-{
-    unsigned insn_start_words = tcg_ctx->insn_start_words;
-    TCGOp *op = tcg_emit_op(INDEX_op_insn_start,
-                            insn_start_words * 64 / TCG_TARGET_REG_BITS);
-
-    tcg_set_insn_start_param(op, 0, pc);
-    if (insn_start_words > 1) {
-        tcg_set_insn_start_param(op, 1, a1);
-    }
-    if (insn_start_words > 2) {
-        tcg_set_insn_start_param(op, 2, a2);
-    }
-}
-
 #if TARGET_LONG_BITS == 32
 typedef TCGv_i32 TCGv;
 #define tcg_temp_new() tcg_temp_new_i32()
diff --git a/include/tcg/tcg.h b/include/tcg/tcg.h
index 92a23e10218..d87d900bf81 100644
--- a/include/tcg/tcg.h
+++ b/include/tcg/tcg.h
@@ -609,6 +609,8 @@ static inline void tcg_set_insn_start_param(TCGOp *op, int arg, uint64_t v)
     }
 }
 
+void tcg_gen_insn_start(uint64_t pc, uint64_t a1, uint64_t a2);
+
 /* The last op that was emitted.  */
 static inline TCGOp *tcg_last_op(void)
 {
diff --git a/tcg/tcg.c b/tcg/tcg.c
index e8950df2ad3..904f858e4dc 100644
--- a/tcg/tcg.c
+++ b/tcg/tcg.c
@@ -3468,6 +3468,21 @@ TCGOp *tcg_op_insert_after(TCGContext *s, TCGOp *old_op,
     return new_op;
 }
 
+void tcg_gen_insn_start(uint64_t pc, uint64_t a1, uint64_t a2)
+{
+    unsigned insn_start_words = tcg_ctx->insn_start_words;
+    TCGOp *op = tcg_emit_op(INDEX_op_insn_start,
+                            insn_start_words * 64 / TCG_TARGET_REG_BITS);
+
+    tcg_set_insn_start_param(op, 0, pc);
+    if (insn_start_words > 1) {
+        tcg_set_insn_start_param(op, 1, a1);
+    }
+    if (insn_start_words > 2) {
+        tcg_set_insn_start_param(op, 2, a2);
+    }
+}
+
 static void move_label_uses(TCGLabel *to, TCGLabel *from)
 {
     TCGLabelUse *u;
-- 
2.47.1

Re: [PATCH-for-10.1 01/12] tcg: Declare TARGET_INSN_START_EXTRA_WORDS in 'cpu-param.h'

[Richard Henderson]

On 3/19/25 06:44, Philippe Mathieu-Daudé wrote:
> To avoid including the huge "cpu.h" for a simple definition,
> move TARGET_INSN_START_EXTRA_WORDS to "cpu-param.h".
> 
> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
> ---
>   target/arm/cpu-param.h        | 14 ++++++++++++++
>   target/arm/cpu.h              | 14 --------------
>   target/hppa/cpu-param.h       |  2 ++
>   target/hppa/cpu.h             |  2 --
>   target/i386/cpu-param.h       |  2 ++
>   target/i386/cpu.h             |  2 --
>   target/m68k/cpu-param.h       |  2 ++
>   target/m68k/cpu.h             |  2 --
>   target/microblaze/cpu-param.h |  2 ++
>   target/microblaze/cpu.h       |  2 --
>   target/mips/cpu-param.h       |  2 ++
>   target/mips/cpu.h             |  2 --
>   target/openrisc/cpu-param.h   |  2 ++
>   target/openrisc/cpu.h         |  2 --
>   target/riscv/cpu-param.h      |  8 ++++++++
>   target/riscv/cpu.h            |  6 ------
>   target/s390x/cpu-param.h      |  2 ++
>   target/s390x/cpu.h            |  2 --
>   target/sh4/cpu-param.h        |  2 ++
>   target/sh4/cpu.h              |  2 --
>   target/sparc/cpu-param.h      |  2 ++
>   target/sparc/cpu.h            |  1 -
>   22 files changed, 40 insertions(+), 37 deletions(-)
> 
> diff --git a/target/arm/cpu-param.h b/target/arm/cpu-param.h
> index 896b35bd6d5..ed1f0b16e51 100644
> --- a/target/arm/cpu-param.h
> +++ b/target/arm/cpu-param.h
> @@ -38,6 +38,20 @@
>   # define TARGET_PAGE_BITS_MIN  10
>   #endif /* !CONFIG_USER_ONLY */
>   
> +/* ARM-specific extra insn start words:
> + * 1: Conditional execution bits
> + * 2: Partial exception syndrome for data aborts
> + */
> +#define TARGET_INSN_START_EXTRA_WORDS 2
> +
> +/* The 2nd extra word holding syndrome info for data aborts does not use
> + * the upper 6 bits nor the lower 13 bits. We mask and shift it down to
> + * help the sleb128 encoder do a better job.
> + * When restoring the CPU state, we shift it back up.
> + */
> +#define ARM_INSN_START_WORD2_MASK ((1 << 26) - 1)
> +#define ARM_INSN_START_WORD2_SHIFT 13

This does not belong in cpu-param.h.  This is private to target/arm/, and should probably 
be moved to internals.h or translate.h or some such.

Otherwise,
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>


r~

Re: [PATCH-for-10.1 02/12] tcg: Always define TARGET_INSN_START_EXTRA_WORDS

[Richard Henderson]

On 3/19/25 06:44, Philippe Mathieu-Daudé wrote:
> Do not define TARGET_INSN_START_EXTRA_WORDS under the
> hood, have each target explicitly define it.
> 
> Signed-off-by: Philippe Mathieu-Daudé<philmd@linaro.org>
> ---
>   include/tcg/insn-start-words.h | 4 ----
>   include/tcg/tcg-op.h           | 2 +-
>   target/alpha/cpu-param.h       | 2 ++
>   target/avr/cpu-param.h         | 2 ++
>   target/hexagon/cpu-param.h     | 2 ++
>   target/loongarch/cpu-param.h   | 2 ++
>   target/ppc/cpu-param.h         | 2 ++
>   target/rx/cpu-param.h          | 2 ++
>   target/tricore/cpu-param.h     | 2 ++
>   target/xtensa/cpu-param.h      | 2 ++
>   10 files changed, 17 insertions(+), 5 deletions(-)

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

r~

Re: [PATCH-for-10.1 03/12] tcg: Have tcg_gen_insn_start() take uint64_t arguments

[Richard Henderson]

On 3/19/25 06:44, Philippe Mathieu-Daudé wrote:
> Since restore_state_to_opc()'s rework in commits d29256896..04f105758
> and TCGContext::gen_insn_data[] widened in commit c9ad8d27caa ("tcg:
> Widen gen_insn_data to uint64_t"), tcg_set_insn_start_param()'s 3rd
> argument is uint64_t, not target_ulong. Use the same type signature
> for tcg_gen_insn_start().
> 
> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
> ---
>   include/tcg/tcg-op.h      | 7 +++----
>   accel/tcg/translate-all.c | 2 +-
>   2 files changed, 4 insertions(+), 5 deletions(-)

Your argument is flawed.  It's not that the type when extracting is different, but that 
the type when inserting is intentionally truncated to the target address size.

It's quite possible that there are no longer any odd uses, since I guess all uses of 
tcg_gen_insn_start are now in TranslatorOps.insn_start, reading from 
DisasContextBase.pc_next.  If so, I would consider changing the type here to vaddr.


r~

Re: [PATCH-for-10.1 04/12] tcg: Declare local 'insn_start_words' variable in tcg_gen_insn_start()

[Richard Henderson]

On 3/19/25 06:44, Philippe Mathieu-Daudé wrote:
> In order to keep following commits simple, introduce the
> 'insn_start_words' local variable in tcg_gen_insn_start().
> 
> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
> ---
>   include/tcg/tcg-op.h | 15 ++++++++++++---
>   1 file changed, 12 insertions(+), 3 deletions(-)

I think there's no point in this, or the follow ups vs this block of code.


r~

> 
> diff --git a/include/tcg/tcg-op.h b/include/tcg/tcg-op.h
> index 8938f386599..e0038e70a8d 100644
> --- a/include/tcg/tcg-op.h
> +++ b/include/tcg/tcg-op.h
> @@ -25,20 +25,29 @@
>   #if TARGET_INSN_START_EXTRA_WORDS == 0
>   static inline void tcg_gen_insn_start(uint64_t pc)
>   {
> -    TCGOp *op = tcg_emit_op(INDEX_op_insn_start, 64 / TCG_TARGET_REG_BITS);
> +    unsigned insn_start_words = 1;
> +    TCGOp *op = tcg_emit_op(INDEX_op_insn_start,
> +                            insn_start_words * 64 / TCG_TARGET_REG_BITS);
> +
>       tcg_set_insn_start_param(op, 0, pc);
>   }
>   #elif TARGET_INSN_START_EXTRA_WORDS == 1
>   static inline void tcg_gen_insn_start(uint64_t pc, uint64_t a1)
>   {
> -    TCGOp *op = tcg_emit_op(INDEX_op_insn_start, 2 * 64 / TCG_TARGET_REG_BITS);
> +    unsigned insn_start_words = 1 + TARGET_INSN_START_EXTRA_WORDS;
> +    TCGOp *op = tcg_emit_op(INDEX_op_insn_start,
> +                            insn_start_words * 64 / TCG_TARGET_REG_BITS);
> +
>       tcg_set_insn_start_param(op, 0, pc);
>       tcg_set_insn_start_param(op, 1, a1);
>   }
>   #elif TARGET_INSN_START_EXTRA_WORDS == 2
>   static inline void tcg_gen_insn_start(uint64_t pc, uint64_t a1, uint64_t a2)
>   {
> -    TCGOp *op = tcg_emit_op(INDEX_op_insn_start, 3 * 64 / TCG_TARGET_REG_BITS);
> +    unsigned insn_start_words = 1 + TARGET_INSN_START_EXTRA_WORDS;
> +    TCGOp *op = tcg_emit_op(INDEX_op_insn_start,
> +                            insn_start_words * 64 / TCG_TARGET_REG_BITS);
> +
>       tcg_set_insn_start_param(op, 0, pc);
>       tcg_set_insn_start_param(op, 1, a1);
>       tcg_set_insn_start_param(op, 2, a2);

Re: [PATCH-for-10.1 05/12] tcg: Use TCGContext::insn_start_words in tcg_gen_insn_start()

[Richard Henderson]

On 3/19/25 06:44, Philippe Mathieu-Daudé wrote:
> In tb_gen_code() we set TCGContext::insn_start_words to
> TARGET_INSN_START_WORDS:
> 
> 290 TranslationBlock *tb_gen_code(...)
> 293 {
> ...
> 351     tcg_ctx->insn_start_words = TARGET_INSN_START_WORDS;
> 
> This definition is expanded to:
> 
>   11 # define TARGET_INSN_START_WORDS (1 + TARGET_INSN_START_EXTRA_WORDS)
> 
> Directly use the identical tcg_ctx->insn_start_words variable.
> 
> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
> ---
>   include/tcg/tcg-op.h | 6 +++---
>   1 file changed, 3 insertions(+), 3 deletions(-)

Nack.

We are specializing the function signature to the number of arguments.
There is absolutely no point in reading that number from a variable.


r~

> 
> diff --git a/include/tcg/tcg-op.h b/include/tcg/tcg-op.h
> index e0038e70a8d..1f0d3b95304 100644
> --- a/include/tcg/tcg-op.h
> +++ b/include/tcg/tcg-op.h
> @@ -25,7 +25,7 @@
>   #if TARGET_INSN_START_EXTRA_WORDS == 0
>   static inline void tcg_gen_insn_start(uint64_t pc)
>   {
> -    unsigned insn_start_words = 1;
> +    unsigned insn_start_words = tcg_ctx->insn_start_words;
>       TCGOp *op = tcg_emit_op(INDEX_op_insn_start,
>                               insn_start_words * 64 / TCG_TARGET_REG_BITS);
>   
> @@ -34,7 +34,7 @@ static inline void tcg_gen_insn_start(uint64_t pc)
>   #elif TARGET_INSN_START_EXTRA_WORDS == 1
>   static inline void tcg_gen_insn_start(uint64_t pc, uint64_t a1)
>   {
> -    unsigned insn_start_words = 1 + TARGET_INSN_START_EXTRA_WORDS;
> +    unsigned insn_start_words = tcg_ctx->insn_start_words;
>       TCGOp *op = tcg_emit_op(INDEX_op_insn_start,
>                               insn_start_words * 64 / TCG_TARGET_REG_BITS);
>   
> @@ -44,7 +44,7 @@ static inline void tcg_gen_insn_start(uint64_t pc, uint64_t a1)
>   #elif TARGET_INSN_START_EXTRA_WORDS == 2
>   static inline void tcg_gen_insn_start(uint64_t pc, uint64_t a1, uint64_t a2)
>   {
> -    unsigned insn_start_words = 1 + TARGET_INSN_START_EXTRA_WORDS;
> +    unsigned insn_start_words = tcg_ctx->insn_start_words;
>       TCGOp *op = tcg_emit_op(INDEX_op_insn_start,
>                               insn_start_words * 64 / TCG_TARGET_REG_BITS);
>   

Re: [PATCH-for-10.1 07/12] tcg: Check TARGET_INSN_START_EXTRA_WORDS range at runtime

[Richard Henderson]

On 3/19/25 06:45, Philippe Mathieu-Daudé wrote:
> Define TARGET_INSN_START_WORDS_MAX and use it to check
> TARGET_INSN_START_EXTRA_WORDS at runtime in tb_gen_code().
> 
> Suggested-by: Peter Maydell <peter.maydell@linaro.org>
> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
> ---
>   include/tcg/tcg-op.h      | 4 +---
>   include/tcg/tcg.h         | 2 ++
>   accel/tcg/translate-all.c | 2 ++
>   3 files changed, 5 insertions(+), 3 deletions(-)

Nack.

> @@ -52,8 +52,6 @@ static inline void tcg_gen_insn_start(uint64_t pc, uint64_t a1, uint64_t a2)
>       tcg_set_insn_start_param(op, 1, a1);
>       tcg_set_insn_start_param(op, 2, a2);
>   }
> -#else
> -#error Unhandled TARGET_INSN_START_EXTRA_WORDS value
>   #endif

This is far superior to ...

> @@ -351,6 +352,7 @@ TranslationBlock *tb_gen_code(CPUState *cpu,
>       tcg_ctx->tlb_dyn_max_bits = CPU_TLB_DYN_MAX_BITS;
>   #endif
>       tcg_ctx->insn_start_words = TARGET_INSN_START_WORDS;
> +    tcg_debug_assert(tcg_ctx->insn_start_words <= TARGET_INSN_START_WORDS_MAX);

... this.


r~

Re: [PATCH-for-10.1 10/12] tcg: Unify tcg_gen_insn_start() to handle 1 or 2 arguments

[Richard Henderson]

On 3/19/25 06:45, Philippe Mathieu-Daudé wrote:
> Merge the tcg_gen_insn_start() definition using 1 extra word
> with the definition using 2, using a2=0 in callers.
> 
> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
> ---
>   include/tcg/tcg-op.h          | 16 ++++------------
>   target/i386/tcg/translate.c   |  2 +-
>   target/m68k/translate.c       |  2 +-
>   target/microblaze/translate.c |  2 +-
>   target/openrisc/translate.c   |  2 +-
>   target/sh4/translate.c        |  2 +-
>   target/sparc/translate.c      |  2 +-
>   7 files changed, 10 insertions(+), 18 deletions(-)

Nack.

> @@ -50,7 +40,9 @@ static inline void tcg_gen_insn_start(uint64_t pc, uint64_t a1, uint64_t a2)
>   
>       tcg_set_insn_start_param(op, 0, pc);
>       tcg_set_insn_start_param(op, 1, a1);
> -    tcg_set_insn_start_param(op, 2, a2);
> +    if (insn_start_words > 2) {
> +        tcg_set_insn_start_param(op, 2, a2);
> +    }

Not this, where you're passing unused arguments but for some reason are not storing them.

If you want to unify all callers on 3 arguments, that's one thing.
But conditionally not storing them?  That's just weird.

If you *do* want to unify all callers on 3 arguments, then you can dispense with 
TARGET_INSN_START_EXTRA_WORDS entirely.  Just define TCG_INSN_START_WORDS == 3 generically 
and drop everything else.


r~

Re: [PATCH-for-10.1 12/12] tcg: Uninline tcg_gen_insn_start()

[Alex Bennée]

Philippe Mathieu-Daudé <philmd@linaro.org> writes:

> tcg_gen_insn_start() is now common to all TCG frontends.
> We don't need to keep it inlined, move it to tcg.c.
>
> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
> ---
>  include/tcg/tcg-op.h | 15 ---------------
>  include/tcg/tcg.h    |  2 ++
>  tcg/tcg.c            | 15 +++++++++++++++
>  3 files changed, 17 insertions(+), 15 deletions(-)
>
> diff --git a/include/tcg/tcg-op.h b/include/tcg/tcg-op.h
> index cf177a1fd3b..470cb46225e 100644
> --- a/include/tcg/tcg-op.h
> +++ b/include/tcg/tcg-op.h
> @@ -22,21 +22,6 @@
>  # error
>  #endif
>  
> -static inline void tcg_gen_insn_start(uint64_t pc, uint64_t a1, uint64_t a2)
> -{
> -    unsigned insn_start_words = tcg_ctx->insn_start_words;
> -    TCGOp *op = tcg_emit_op(INDEX_op_insn_start,
> -                            insn_start_words * 64 / TCG_TARGET_REG_BITS);
> -
> -    tcg_set_insn_start_param(op, 0, pc);
> -    if (insn_start_words > 1) {
> -        tcg_set_insn_start_param(op, 1, a1);
> -    }
> -    if (insn_start_words > 2) {
> -        tcg_set_insn_start_param(op, 2, a2);
> -    }
> -}
> -
>  #if TARGET_LONG_BITS == 32
>  typedef TCGv_i32 TCGv;
>  #define tcg_temp_new() tcg_temp_new_i32()
> diff --git a/include/tcg/tcg.h b/include/tcg/tcg.h
> index 92a23e10218..d87d900bf81 100644
> --- a/include/tcg/tcg.h
> +++ b/include/tcg/tcg.h
> @@ -609,6 +609,8 @@ static inline void tcg_set_insn_start_param(TCGOp *op, int arg, uint64_t v)
>      }
>  }
>  
> +void tcg_gen_insn_start(uint64_t pc, uint64_t a1, uint64_t a2);
> +

Is would be nice to docstring the function to explain what it does and
note where the additional data is interpreted
(cpu_restore_state_from_tb?).

Otherwise:

Reviewed-by: Alex Bennée <alex.bennee@linaro.org>

-- 
Alex Bennée
Virtualisation Tech Lead @ Linaro