From: Pierrick Bouvier <pierrick.bouvier@linaro.org>
To: qemu-devel@nongnu.org
Cc: kvm@vger.kernel.org, qemu-arm@nongnu.org,
"Peter Maydell" <peter.maydell@linaro.org>,
"Paolo Bonzini" <pbonzini@redhat.com>,
"Philippe Mathieu-Daudé" <philmd@linaro.org>,
"Richard Henderson" <richard.henderson@linaro.org>,
"Alex Bennée" <alex.bennee@linaro.org>,
"Pierrick Bouvier" <pierrick.bouvier@linaro.org>
Subject: [PATCH v2 02/30] exec/cpu-all: extract tlb flags defines to exec/tlb-flags.h
Date: Thu, 20 Mar 2025 15:29:34 -0700 [thread overview]
Message-ID: <20250320223002.2915728-3-pierrick.bouvier@linaro.org> (raw)
In-Reply-To: <20250320223002.2915728-1-pierrick.bouvier@linaro.org>
Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
---
include/exec/cpu-all.h | 63 --------------------
include/exec/tlb-flags.h | 87 ++++++++++++++++++++++++++++
accel/tcg/cputlb.c | 1 +
accel/tcg/user-exec.c | 1 +
semihosting/uaccess.c | 1 +
target/arm/ptw.c | 1 +
target/arm/tcg/helper-a64.c | 1 +
target/arm/tcg/mte_helper.c | 1 +
target/arm/tcg/sve_helper.c | 1 +
target/i386/tcg/system/excp_helper.c | 1 +
target/riscv/op_helper.c | 1 +
target/riscv/vector_helper.c | 1 +
target/s390x/tcg/mem_helper.c | 1 +
target/sparc/mmu_helper.c | 1 +
14 files changed, 99 insertions(+), 63 deletions(-)
create mode 100644 include/exec/tlb-flags.h
diff --git a/include/exec/cpu-all.h b/include/exec/cpu-all.h
index 013fcc9412a..d2895fb55b1 100644
--- a/include/exec/cpu-all.h
+++ b/include/exec/cpu-all.h
@@ -36,69 +36,6 @@ CPUArchState *cpu_copy(CPUArchState *env);
#include "cpu.h"
-#ifdef CONFIG_USER_ONLY
-
-/*
- * Allow some level of source compatibility with softmmu. We do not
- * support any of the more exotic features, so only invalid pages may
- * be signaled by probe_access_flags().
- */
-#define TLB_INVALID_MASK (1 << (TARGET_PAGE_BITS_MIN - 1))
-#define TLB_MMIO (1 << (TARGET_PAGE_BITS_MIN - 2))
-#define TLB_WATCHPOINT 0
-
-#else
-
-/*
- * Flags stored in the low bits of the TLB virtual address.
- * These are defined so that fast path ram access is all zeros.
- * The flags all must be between TARGET_PAGE_BITS and
- * maximum address alignment bit.
- *
- * Use TARGET_PAGE_BITS_MIN so that these bits are constant
- * when TARGET_PAGE_BITS_VARY is in effect.
- *
- * The count, if not the placement of these bits is known
- * to tcg/tcg-op-ldst.c, check_max_alignment().
- */
-/* Zero if TLB entry is valid. */
-#define TLB_INVALID_MASK (1 << (TARGET_PAGE_BITS_MIN - 1))
-/* Set if TLB entry references a clean RAM page. The iotlb entry will
- contain the page physical address. */
-#define TLB_NOTDIRTY (1 << (TARGET_PAGE_BITS_MIN - 2))
-/* Set if TLB entry is an IO callback. */
-#define TLB_MMIO (1 << (TARGET_PAGE_BITS_MIN - 3))
-/* Set if TLB entry writes ignored. */
-#define TLB_DISCARD_WRITE (1 << (TARGET_PAGE_BITS_MIN - 4))
-/* Set if the slow path must be used; more flags in CPUTLBEntryFull. */
-#define TLB_FORCE_SLOW (1 << (TARGET_PAGE_BITS_MIN - 5))
-
-/*
- * Use this mask to check interception with an alignment mask
- * in a TCG backend.
- */
-#define TLB_FLAGS_MASK \
- (TLB_INVALID_MASK | TLB_NOTDIRTY | TLB_MMIO \
- | TLB_FORCE_SLOW | TLB_DISCARD_WRITE)
-
-/*
- * Flags stored in CPUTLBEntryFull.slow_flags[x].
- * TLB_FORCE_SLOW must be set in CPUTLBEntry.addr_idx[x].
- */
-/* Set if TLB entry requires byte swap. */
-#define TLB_BSWAP (1 << 0)
-/* Set if TLB entry contains a watchpoint. */
-#define TLB_WATCHPOINT (1 << 1)
-/* Set if TLB entry requires aligned accesses. */
-#define TLB_CHECK_ALIGNED (1 << 2)
-
-#define TLB_SLOW_FLAGS_MASK (TLB_BSWAP | TLB_WATCHPOINT | TLB_CHECK_ALIGNED)
-
-/* The two sets of flags must not overlap. */
-QEMU_BUILD_BUG_ON(TLB_FLAGS_MASK & TLB_SLOW_FLAGS_MASK);
-
-#endif /* !CONFIG_USER_ONLY */
-
/* Validate correct placement of CPUArchState. */
QEMU_BUILD_BUG_ON(offsetof(ArchCPU, parent_obj) != 0);
QEMU_BUILD_BUG_ON(offsetof(ArchCPU, env) != sizeof(CPUState));
diff --git a/include/exec/tlb-flags.h b/include/exec/tlb-flags.h
new file mode 100644
index 00000000000..c371ae77602
--- /dev/null
+++ b/include/exec/tlb-flags.h
@@ -0,0 +1,87 @@
+/*
+ * TLB flags definition
+ *
+ * Copyright (c) 2003 Fabrice Bellard
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 2.1 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library; if not, see <http://www.gnu.org/licenses/>.
+ */
+#ifndef TLB_FLAGS_H
+#define TLB_FLAGS_H
+
+#include "exec/cpu-defs.h"
+
+#ifdef CONFIG_USER_ONLY
+
+/*
+ * Allow some level of source compatibility with softmmu. We do not
+ * support any of the more exotic features, so only invalid pages may
+ * be signaled by probe_access_flags().
+ */
+#define TLB_INVALID_MASK (1 << (TARGET_PAGE_BITS_MIN - 1))
+#define TLB_MMIO (1 << (TARGET_PAGE_BITS_MIN - 2))
+#define TLB_WATCHPOINT 0
+
+#else
+
+/*
+ * Flags stored in the low bits of the TLB virtual address.
+ * These are defined so that fast path ram access is all zeros.
+ * The flags all must be between TARGET_PAGE_BITS and
+ * maximum address alignment bit.
+ *
+ * Use TARGET_PAGE_BITS_MIN so that these bits are constant
+ * when TARGET_PAGE_BITS_VARY is in effect.
+ *
+ * The count, if not the placement of these bits is known
+ * to tcg/tcg-op-ldst.c, check_max_alignment().
+ */
+/* Zero if TLB entry is valid. */
+#define TLB_INVALID_MASK (1 << (TARGET_PAGE_BITS_MIN - 1))
+/* Set if TLB entry references a clean RAM page. The iotlb entry will
+ contain the page physical address. */
+#define TLB_NOTDIRTY (1 << (TARGET_PAGE_BITS_MIN - 2))
+/* Set if TLB entry is an IO callback. */
+#define TLB_MMIO (1 << (TARGET_PAGE_BITS_MIN - 3))
+/* Set if TLB entry writes ignored. */
+#define TLB_DISCARD_WRITE (1 << (TARGET_PAGE_BITS_MIN - 4))
+/* Set if the slow path must be used; more flags in CPUTLBEntryFull. */
+#define TLB_FORCE_SLOW (1 << (TARGET_PAGE_BITS_MIN - 5))
+
+/*
+ * Use this mask to check interception with an alignment mask
+ * in a TCG backend.
+ */
+#define TLB_FLAGS_MASK \
+ (TLB_INVALID_MASK | TLB_NOTDIRTY | TLB_MMIO \
+ | TLB_FORCE_SLOW | TLB_DISCARD_WRITE)
+
+/*
+ * Flags stored in CPUTLBEntryFull.slow_flags[x].
+ * TLB_FORCE_SLOW must be set in CPUTLBEntry.addr_idx[x].
+ */
+/* Set if TLB entry requires byte swap. */
+#define TLB_BSWAP (1 << 0)
+/* Set if TLB entry contains a watchpoint. */
+#define TLB_WATCHPOINT (1 << 1)
+/* Set if TLB entry requires aligned accesses. */
+#define TLB_CHECK_ALIGNED (1 << 2)
+
+#define TLB_SLOW_FLAGS_MASK (TLB_BSWAP | TLB_WATCHPOINT | TLB_CHECK_ALIGNED)
+
+/* The two sets of flags must not overlap. */
+QEMU_BUILD_BUG_ON(TLB_FLAGS_MASK & TLB_SLOW_FLAGS_MASK);
+
+#endif /* !CONFIG_USER_ONLY */
+
+#endif /* TLB_FLAGS_H */
diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c
index 613f919fffb..b2db49e305e 100644
--- a/accel/tcg/cputlb.c
+++ b/accel/tcg/cputlb.c
@@ -34,6 +34,7 @@
#include "qemu/error-report.h"
#include "exec/log.h"
#include "exec/helper-proto-common.h"
+#include "exec/tlb-flags.h"
#include "qemu/atomic.h"
#include "qemu/atomic128.h"
#include "tb-internal.h"
diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c
index ebc7c3ecf54..667c5e03543 100644
--- a/accel/tcg/user-exec.c
+++ b/accel/tcg/user-exec.c
@@ -21,6 +21,7 @@
#include "disas/disas.h"
#include "exec/vaddr.h"
#include "exec/exec-all.h"
+#include "exec/tlb-flags.h"
#include "tcg/tcg.h"
#include "qemu/bitops.h"
#include "qemu/rcu.h"
diff --git a/semihosting/uaccess.c b/semihosting/uaccess.c
index a9578911669..cb64725a37c 100644
--- a/semihosting/uaccess.c
+++ b/semihosting/uaccess.c
@@ -11,6 +11,7 @@
#include "exec/cpu-all.h"
#include "exec/cpu-mmu-index.h"
#include "exec/exec-all.h"
+#include "exec/tlb-flags.h"
#include "semihosting/uaccess.h"
void *uaccess_lock_user(CPUArchState *env, target_ulong addr,
diff --git a/target/arm/ptw.c b/target/arm/ptw.c
index 43309003486..8d4e9e07a94 100644
--- a/target/arm/ptw.c
+++ b/target/arm/ptw.c
@@ -12,6 +12,7 @@
#include "qemu/main-loop.h"
#include "exec/exec-all.h"
#include "exec/page-protection.h"
+#include "exec/tlb-flags.h"
#include "cpu.h"
#include "internals.h"
#include "cpu-features.h"
diff --git a/target/arm/tcg/helper-a64.c b/target/arm/tcg/helper-a64.c
index 9244848efed..fa79d19425f 100644
--- a/target/arm/tcg/helper-a64.c
+++ b/target/arm/tcg/helper-a64.c
@@ -31,6 +31,7 @@
#include "exec/cpu-common.h"
#include "exec/exec-all.h"
#include "exec/cpu_ldst.h"
+#include "exec/tlb-flags.h"
#include "qemu/int128.h"
#include "qemu/atomic128.h"
#include "fpu/softfloat.h"
diff --git a/target/arm/tcg/mte_helper.c b/target/arm/tcg/mte_helper.c
index 80164a80504..888c6707547 100644
--- a/target/arm/tcg/mte_helper.c
+++ b/target/arm/tcg/mte_helper.c
@@ -31,6 +31,7 @@
#endif
#include "exec/cpu_ldst.h"
#include "exec/helper-proto.h"
+#include "exec/tlb-flags.h"
#include "accel/tcg/cpu-ops.h"
#include "qapi/error.h"
#include "qemu/guest-random.h"
diff --git a/target/arm/tcg/sve_helper.c b/target/arm/tcg/sve_helper.c
index d786b4b1118..e3bed77b48e 100644
--- a/target/arm/tcg/sve_helper.c
+++ b/target/arm/tcg/sve_helper.c
@@ -23,6 +23,7 @@
#include "exec/exec-all.h"
#include "exec/page-protection.h"
#include "exec/helper-proto.h"
+#include "exec/tlb-flags.h"
#include "tcg/tcg-gvec-desc.h"
#include "fpu/softfloat.h"
#include "tcg/tcg.h"
diff --git a/target/i386/tcg/system/excp_helper.c b/target/i386/tcg/system/excp_helper.c
index 6876329de21..b0b74df72fd 100644
--- a/target/i386/tcg/system/excp_helper.c
+++ b/target/i386/tcg/system/excp_helper.c
@@ -22,6 +22,7 @@
#include "exec/cpu_ldst.h"
#include "exec/cputlb.h"
#include "exec/page-protection.h"
+#include "exec/tlb-flags.h"
#include "tcg/helper-tcg.h"
typedef struct TranslateParams {
diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c
index 0d4220ba93b..8208bec078a 100644
--- a/target/riscv/op_helper.c
+++ b/target/riscv/op_helper.c
@@ -25,6 +25,7 @@
#include "exec/cputlb.h"
#include "exec/cpu_ldst.h"
#include "exec/helper-proto.h"
+#include "exec/tlb-flags.h"
#include "trace.h"
/* Exceptions processing helpers */
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index 7773df6a7c7..ff05390baef 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -25,6 +25,7 @@
#include "exec/cpu_ldst.h"
#include "exec/page-protection.h"
#include "exec/helper-proto.h"
+#include "exec/tlb-flags.h"
#include "fpu/softfloat.h"
#include "tcg/tcg-gvec-desc.h"
#include "internals.h"
diff --git a/target/s390x/tcg/mem_helper.c b/target/s390x/tcg/mem_helper.c
index 8187b917ba1..0ff2e10d816 100644
--- a/target/s390x/tcg/mem_helper.c
+++ b/target/s390x/tcg/mem_helper.c
@@ -29,6 +29,7 @@
#include "exec/cputlb.h"
#include "exec/page-protection.h"
#include "exec/cpu_ldst.h"
+#include "exec/tlb-flags.h"
#include "accel/tcg/cpu-ops.h"
#include "qemu/int128.h"
#include "qemu/atomic128.h"
diff --git a/target/sparc/mmu_helper.c b/target/sparc/mmu_helper.c
index 4a0cedd9e21..cce3046b694 100644
--- a/target/sparc/mmu_helper.c
+++ b/target/sparc/mmu_helper.c
@@ -23,6 +23,7 @@
#include "exec/cputlb.h"
#include "exec/cpu-mmu-index.h"
#include "exec/page-protection.h"
+#include "exec/tlb-flags.h"
#include "qemu/qemu-print.h"
#include "trace.h"
--
2.39.5
next prev parent reply other threads:[~2025-03-20 22:32 UTC|newest]
Thread overview: 77+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-03-20 22:29 [PATCH v2 00/30] single-binary: start make hw/arm/ common Pierrick Bouvier
2025-03-20 22:29 ` [PATCH v2 01/30] exec/cpu-all: remove BSWAP_NEEDED Pierrick Bouvier
2025-03-23 19:26 ` Richard Henderson
2025-03-24 20:54 ` Pierrick Bouvier
2025-03-20 22:29 ` Pierrick Bouvier [this message]
2025-03-23 19:28 ` [PATCH v2 02/30] exec/cpu-all: extract tlb flags defines to exec/tlb-flags.h Richard Henderson
2025-03-20 22:29 ` [PATCH v2 03/30] exec/cpu-all: move cpu_copy to linux-user/qemu.h Pierrick Bouvier
2025-03-21 15:36 ` Richard Henderson
2025-03-20 22:29 ` [PATCH v2 04/30] include/exec/cpu-all: move compile time check for CPUArchState to cpu-target.c Pierrick Bouvier
2025-03-21 15:42 ` Richard Henderson
2025-03-20 22:29 ` [PATCH v2 05/30] exec/cpu-all: remove system/memory include Pierrick Bouvier
2025-03-21 16:36 ` Richard Henderson
2025-03-20 22:29 ` [PATCH v2 06/30] exec/cpu-all: remove exec/page-protection include Pierrick Bouvier
2025-03-21 16:37 ` Richard Henderson
2025-03-20 22:29 ` [PATCH v2 07/30] exec/cpu-all: remove tswap include Pierrick Bouvier
2025-03-21 16:37 ` Richard Henderson
2025-03-20 22:29 ` [PATCH v2 08/30] exec/cpu-all: remove exec/cpu-interrupt include Pierrick Bouvier
2025-03-21 16:38 ` Richard Henderson
2025-03-20 22:29 ` [PATCH v2 09/30] exec/cpu-all: remove exec/cpu-defs include Pierrick Bouvier
2025-03-21 16:38 ` Richard Henderson
2025-03-20 22:29 ` [PATCH v2 10/30] exec/cpu-all: remove exec/target_page include Pierrick Bouvier
2025-03-23 19:29 ` Richard Henderson
2025-03-20 22:29 ` [PATCH v2 11/30] exec/cpu-all: remove hw/core/cpu.h include Pierrick Bouvier
2025-03-21 18:00 ` Richard Henderson
2025-03-20 22:29 ` [PATCH v2 12/30] accel/tcg: fix missing includes for TCG_GUEST_DEFAULT_MO Pierrick Bouvier
2025-03-21 18:01 ` Richard Henderson
2025-03-20 22:29 ` [PATCH v2 13/30] accel/tcg: fix missing includes for TARGET_HAS_PRECISE_SMC Pierrick Bouvier
2025-03-21 18:02 ` Richard Henderson
2025-03-20 22:29 ` [PATCH v2 14/30] exec/cpu-all: remove cpu include Pierrick Bouvier
2025-03-21 18:02 ` Richard Henderson
2025-03-20 22:29 ` [PATCH v2 15/30] exec/cpu-all: transfer exec/cpu-common include to cpu.h headers Pierrick Bouvier
2025-03-21 18:03 ` Richard Henderson
2025-03-20 22:29 ` [PATCH v2 16/30] exec/cpu-all: remove this header Pierrick Bouvier
2025-03-21 18:04 ` Richard Henderson
2025-03-20 22:29 ` [PATCH v2 17/30] exec/target_page: runtime defintion for TARGET_PAGE_BITS_MIN Pierrick Bouvier
2025-03-21 18:05 ` Richard Henderson
2025-03-21 18:09 ` Pierrick Bouvier
2025-03-21 19:27 ` Richard Henderson
2025-03-21 20:11 ` Pierrick Bouvier
2025-03-21 22:19 ` Richard Henderson
2025-03-22 0:01 ` Pierrick Bouvier
2025-03-22 0:20 ` Pierrick Bouvier
2025-03-22 20:55 ` Richard Henderson
2025-03-24 21:39 ` Pierrick Bouvier
2025-03-20 22:29 ` [PATCH v2 18/30] accel/kvm: move KVM_HAVE_MCE_INJECTION define to kvm-all.c Pierrick Bouvier
2025-03-23 19:35 ` Richard Henderson
2025-03-20 22:29 ` [PATCH v2 19/30] exec/poison: KVM_HAVE_MCE_INJECTION can now be poisoned Pierrick Bouvier
2025-03-20 22:29 ` [PATCH v2 20/30] target/arm/cpu: always define kvm related registers Pierrick Bouvier
2025-03-23 19:37 ` Richard Henderson
2025-03-24 21:11 ` Pierrick Bouvier
2025-03-25 1:24 ` Richard Henderson
2025-04-02 13:36 ` Philippe Mathieu-Daudé
2025-04-02 15:06 ` Pierrick Bouvier
2025-03-20 22:29 ` [PATCH v2 21/30] target/arm/cpu: flags2 is always uint64_t Pierrick Bouvier
2025-03-20 22:29 ` [PATCH v2 22/30] target/arm/cpu: define same set of registers for aarch32 and aarch64 Pierrick Bouvier
2025-03-20 22:29 ` [PATCH v2 23/30] target/arm/cpu: remove inline stubs for aarch32 emulation Pierrick Bouvier
2025-03-23 19:41 ` Richard Henderson
2025-03-20 22:29 ` [PATCH v2 24/30] meson: add common hw files Pierrick Bouvier
2025-03-23 19:58 ` Richard Henderson
2025-03-24 21:21 ` Pierrick Bouvier
2025-03-20 22:29 ` [PATCH v2 25/30] hw/arm/boot: make compilation unit hw common Pierrick Bouvier
2025-03-23 19:46 ` Richard Henderson
2025-03-20 22:29 ` [PATCH v2 26/30] hw/arm/armv7m: prepare compilation unit to be common Pierrick Bouvier
2025-03-23 19:48 ` Richard Henderson
2025-03-24 21:31 ` Pierrick Bouvier
2025-03-25 1:22 ` Richard Henderson
2025-03-25 1:48 ` Pierrick Bouvier
2025-03-20 22:29 ` [PATCH v2 27/30] hw/arm/digic_boards: " Pierrick Bouvier
2025-03-23 19:49 ` Richard Henderson
2025-03-20 22:30 ` [PATCH v2 28/30] hw/arm/xlnx-zynqmp: " Pierrick Bouvier
2025-03-23 19:50 ` Richard Henderson
2025-03-24 21:23 ` Pierrick Bouvier
2025-03-20 22:30 ` [PATCH v2 29/30] hw/arm/xlnx-versal: " Pierrick Bouvier
2025-03-23 19:50 ` Richard Henderson
2025-03-20 22:30 ` [PATCH v2 30/30] hw/arm: make most of the compilation units common Pierrick Bouvier
2025-03-23 19:51 ` Richard Henderson
2025-03-20 22:49 ` [PATCH v2 00/30] single-binary: start make hw/arm/ common Pierrick Bouvier
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