From: "Philippe Mathieu-Daudé" <philmd@linaro.org>
To: qemu-devel@nongnu.org
Cc: "Frederic Konrad" <konrad.frederic@yahoo.fr>,
"Artyom Tarasenko" <atar4qemu@gmail.com>,
"Mark Cave-Ayland" <mark.cave-ayland@ilande.co.uk>,
"Clément Chigot" <chigot@adacore.com>,
"Philippe Mathieu-Daudé" <philmd@linaro.org>
Subject: [PATCH-for-10.1 2/4] target/sparc: Restrict SPARC64 specific features
Date: Tue, 25 Mar 2025 13:39:25 +0100 [thread overview]
Message-ID: <20250325123927.74939-3-philmd@linaro.org> (raw)
In-Reply-To: <20250325123927.74939-1-philmd@linaro.org>
Following commit 554abe47c7b ("target/sparc: Partition cpu
features"), avoid compiling SPARC64 specific code on 32-bit
binary.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
target/sparc/cpu-feature.h.inc | 20 ++++++++++++--------
target/sparc/translate.c | 10 ++++++++--
2 files changed, 20 insertions(+), 10 deletions(-)
diff --git a/target/sparc/cpu-feature.h.inc b/target/sparc/cpu-feature.h.inc
index be810052376..7b7b94a0562 100644
--- a/target/sparc/cpu-feature.h.inc
+++ b/target/sparc/cpu-feature.h.inc
@@ -1,12 +1,8 @@
FEATURE(FLOAT128)
-FEATURE(MUL)
-FEATURE(DIV)
-FEATURE(VIS1)
-FEATURE(VIS2)
-FEATURE(FSMULD)
-FEATURE(HYPV)
-FEATURE(CMT)
-FEATURE(GL)
+FEATURE(MUL) /* Mandatory in v9 */
+FEATURE(DIV) /* Mandatory in v9 */
+FEATURE(FSMULD) /* Mandatory in v9 */
+
FEATURE(TA0_SHUTDOWN) /* Shutdown on "ta 0x0" */
FEATURE(ASR17)
FEATURE(CACHE_CTRL)
@@ -16,3 +12,11 @@ FEATURE(FMAF)
FEATURE(VIS3)
FEATURE(IMA)
FEATURE(VIS4)
+
+#ifdef TARGET_SPARC64
+FEATURE(HYPV)
+FEATURE(CMT)
+FEATURE(GL)
+FEATURE(VIS1)
+FEATURE(VIS2)
+#endif
diff --git a/target/sparc/translate.c b/target/sparc/translate.c
index bfe63649db2..53b145848b9 100644
--- a/target/sparc/translate.c
+++ b/target/sparc/translate.c
@@ -1850,10 +1850,12 @@ static void gen_st_asi(DisasContext *dc, DisasASI *da, TCGv src, TCGv addr)
if (TARGET_LONG_BITS == 32) {
gen_exception(dc, TT_ILL_INSN);
break;
+#ifdef TARGET_SPARC64
} else if (!(dc->def->features & CPU_FEATURE_HYPV)) {
/* Pre OpenSPARC CPUs don't have these */
gen_exception(dc, TT_ILL_INSN);
break;
+#endif
}
/* In OpenSPARC T1+ CPUs TWINX ASIs in store are ST_BLKINIT_ ASIs */
/* fall through */
@@ -2750,12 +2752,16 @@ static bool trans_SETHI(DisasContext *dc, arg_SETHI *a)
static bool do_tcc(DisasContext *dc, int cond, int cc,
int rs1, bool imm, int rs2_or_imm)
{
- int mask = ((dc->def->features & CPU_FEATURE_HYPV) && supervisor(dc)
- ? UA2005_HTRAP_MASK : V8_TRAP_MASK);
+ int mask = 0;
DisasCompare cmp;
TCGLabel *lab;
TCGv_i32 trap;
+#ifdef TARGET_SPARC64
+ mask = ((dc->def->features & CPU_FEATURE_HYPV) && supervisor(dc))
+ ? UA2005_HTRAP_MASK : V8_TRAP_MASK;
+#endif
+
/* Trap never. */
if (cond == 0) {
return advance_pc(dc);
--
2.47.1
next prev parent reply other threads:[~2025-03-25 12:40 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-03-25 12:39 [PATCH-for-10.1 0/4] target/sparc: Spring cleanups around CPU features & LEON3 Philippe Mathieu-Daudé
2025-03-25 12:39 ` [PATCH-for-10.1 1/4] target/sparc: Expose more CPU features Philippe Mathieu-Daudé
2025-03-25 14:11 ` Richard Henderson
2025-03-25 14:43 ` Philippe Mathieu-Daudé
2025-03-25 12:39 ` Philippe Mathieu-Daudé [this message]
2025-03-25 14:07 ` [PATCH-for-10.1 2/4] target/sparc: Restrict SPARC64 specific features Richard Henderson
2025-03-25 14:41 ` Philippe Mathieu-Daudé
2025-03-25 12:39 ` [PATCH-for-10.1 3/4] target/sparc: Log unimplemented ASI load/store accesses Philippe Mathieu-Daudé
2025-03-26 14:49 ` Clément Chigot
2025-03-25 12:39 ` [PATCH-for-10.1 4/4] target/sparc: Move hardware fields from CPUSPARCState to SPARCCPU Philippe Mathieu-Daudé
2025-03-26 14:54 ` Clément Chigot
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