[PATCH v2 00/12] Fix RVV encoding corner cases

[PATCH v2 00/12] Fix RVV encoding corner cases

[Max Chou]

This patch series fixes several corner cases of RISC-V vector
instruction's encoding constraints.

Building on Anton's original work, this v2 series specifically
addresses:

1. Illegal overlaps between source registers
2. Corner cases in complex vector instructions like vrgatherei16
3. Handling of register overlaps in vector widening/narrowing
instructions
4. Fix unmasked RVV instruction encoding (e.g. vcompress.vm)


Anton Blanchard (2):
  target/riscv: rvv: Source vector registers cannot overlap mask
    register
  target/riscv: rvv: Add CHECK arg to GEN_OPFVF_WIDEN_TRANS

Max Chou (10):
  target/riscv: Add vext_check_input_eew to check mismatched input EEWs
    encoding constraint
  target/riscv: rvv: Apply vext_check_input_eew to vector register
    gather instructions
  target/riscv: rvv: Apply vext_check_input_eew to
    OPIVI/OPIVX/OPFVF(vext_check_ss) instructions
  target/riscv: rvv: Apply vext_check_input_eew to
    OPIVV/OPFVV(vext_check_sss) instructions
  target/riscv: rvv: Apply vext_check_input_eew to vector slide
    instructions(OPIVI/OPIVX)
  target/riscv: rvv: Apply vext_check_input_eew to vector integer
    extension instructions(OPMVV)
  target/riscv: rvv: Apply vext_check_input_eew to vector widen
    instructions(OPMVV/OPMVX/etc.)
  target/riscv: rvv: Apply vext_check_input_eew to vector narrow
    instructions
  target/riscv: rvv: Apply vext_check_input_eew to vector indexed
    load/store instructions
  target/riscv: Fix the rvv reserved encoding of unmasked instructions

 target/riscv/insn32.decode                 |  18 +--
 target/riscv/insn_trans/trans_rvbf16.c.inc |   9 +-
 target/riscv/insn_trans/trans_rvv.c.inc    | 167 +++++++++++++++++----
 3 files changed, 154 insertions(+), 40 deletions(-)

-- 
2.43.0

[PATCH v2 01/12] target/riscv: rvv: Source vector registers cannot overlap mask register

[Max Chou]

From: Anton Blanchard <antonb@tenstorrent.com>

Add the relevant ISA paragraphs explaining why source (and destination)
registers cannot overlap the mask register.

Signed-off-by: Anton Blanchard <antonb@tenstorrent.com>
Signed-off-by: Max Chou <max.chou@sifive.com>
---
 target/riscv/insn_trans/trans_rvv.c.inc | 29 ++++++++++++++++++++++---
 1 file changed, 26 insertions(+), 3 deletions(-)

diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
index b9883a5d323..20b1cb127b4 100644
--- a/target/riscv/insn_trans/trans_rvv.c.inc
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
@@ -100,10 +100,33 @@ static bool require_scale_rvfmin(DisasContext *s)
     }
 }
 
-/* Destination vector register group cannot overlap source mask register. */
-static bool require_vm(int vm, int vd)
+/*
+ * Source and destination vector register groups cannot overlap source mask
+ * register:
+ *
+ * A vector register cannot be used to provide source operands with more than
+ * one EEW for a single instruction. A mask register source is considered to
+ * have EEW=1 for this constraint. An encoding that would result in the same
+ * vector register being read with two or more different EEWs, including when
+ * the vector register appears at different positions within two or more vector
+ * register groups, is reserved.
+ * (Section 5.2)
+ *
+ * A destination vector register group can overlap a source vector
+ * register group only if one of the following holds:
+ *  1. The destination EEW equals the source EEW.
+ *  2. The destination EEW is smaller than the source EEW and the overlap
+ *     is in the lowest-numbered part of the source register group.
+ *  3. The destination EEW is greater than the source EEW, the source EMUL
+ *     is at least 1, and the overlap is in the highest-numbered part of
+ *     the destination register group.
+ * For the purpose of determining register group overlap constraints, mask
+ * elements have EEW=1.
+ * (Section 5.2)
+ */
+static bool require_vm(int vm, int v)
 {
-    return (vm != 0 || vd != 0);
+    return (vm != 0 || v != 0);
 }
 
 static bool require_nf(int vd, int nf, int lmul)
-- 
2.43.0

[PATCH v2 02/12] target/riscv: rvv: Add CHECK arg to GEN_OPFVF_WIDEN_TRANS

[Max Chou]

From: Anton Blanchard <antonb@tenstorrent.com>

Signed-off-by: Anton Blanchard <antonb@tenstorrent.com>
Signed-off-by: Max Chou <max.chou@sifive.com>
---
 target/riscv/insn_trans/trans_rvv.c.inc | 18 +++++++++---------
 1 file changed, 9 insertions(+), 9 deletions(-)

diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
index 20b1cb127b4..e630f8661e1 100644
--- a/target/riscv/insn_trans/trans_rvv.c.inc
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
@@ -2403,10 +2403,10 @@ static bool opfvf_widen_check(DisasContext *s, arg_rmrr *a)
 }
 
 /* OPFVF with WIDEN */
-#define GEN_OPFVF_WIDEN_TRANS(NAME)                              \
+#define GEN_OPFVF_WIDEN_TRANS(NAME, CHECK)                       \
 static bool trans_##NAME(DisasContext *s, arg_rmrr *a)           \
 {                                                                \
-    if (opfvf_widen_check(s, a)) {                               \
+    if (CHECK(s, a)) {                                           \
         uint32_t data = 0;                                       \
         static gen_helper_opfvf *const fns[2] = {                \
             gen_helper_##NAME##_h, gen_helper_##NAME##_w,        \
@@ -2422,8 +2422,8 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a)           \
     return false;                                                \
 }
 
-GEN_OPFVF_WIDEN_TRANS(vfwadd_vf)
-GEN_OPFVF_WIDEN_TRANS(vfwsub_vf)
+GEN_OPFVF_WIDEN_TRANS(vfwadd_vf, opfvf_widen_check)
+GEN_OPFVF_WIDEN_TRANS(vfwsub_vf, opfvf_widen_check)
 
 static bool opfwv_widen_check(DisasContext *s, arg_rmrr *a)
 {
@@ -2505,7 +2505,7 @@ GEN_OPFVF_TRANS(vfrdiv_vf,  opfvf_check)
 
 /* Vector Widening Floating-Point Multiply */
 GEN_OPFVV_WIDEN_TRANS(vfwmul_vv, opfvv_widen_check)
-GEN_OPFVF_WIDEN_TRANS(vfwmul_vf)
+GEN_OPFVF_WIDEN_TRANS(vfwmul_vf, opfvf_widen_check)
 
 /* Vector Single-Width Floating-Point Fused Multiply-Add Instructions */
 GEN_OPFVV_TRANS(vfmacc_vv, opfvv_check)
@@ -2530,10 +2530,10 @@ GEN_OPFVV_WIDEN_TRANS(vfwmacc_vv, opfvv_widen_check)
 GEN_OPFVV_WIDEN_TRANS(vfwnmacc_vv, opfvv_widen_check)
 GEN_OPFVV_WIDEN_TRANS(vfwmsac_vv, opfvv_widen_check)
 GEN_OPFVV_WIDEN_TRANS(vfwnmsac_vv, opfvv_widen_check)
-GEN_OPFVF_WIDEN_TRANS(vfwmacc_vf)
-GEN_OPFVF_WIDEN_TRANS(vfwnmacc_vf)
-GEN_OPFVF_WIDEN_TRANS(vfwmsac_vf)
-GEN_OPFVF_WIDEN_TRANS(vfwnmsac_vf)
+GEN_OPFVF_WIDEN_TRANS(vfwmacc_vf, opfvf_widen_check)
+GEN_OPFVF_WIDEN_TRANS(vfwnmacc_vf, opfvf_widen_check)
+GEN_OPFVF_WIDEN_TRANS(vfwmsac_vf, opfvf_widen_check)
+GEN_OPFVF_WIDEN_TRANS(vfwnmsac_vf, opfvf_widen_check)
 
 /* Vector Floating-Point Square-Root Instruction */
 
-- 
2.43.0

[PATCH v2 03/12] target/riscv: Add vext_check_input_eew to check mismatched input EEWs encoding constraint

[Max Chou]

According to the v spec, a vector register cannot be used to provide source
operands with more than one EEW for a single instruction.

Signed-off-by: Max Chou <max.chou@sifive.com>
---
 target/riscv/insn_trans/trans_rvv.c.inc | 29 +++++++++++++++++++++++++
 1 file changed, 29 insertions(+)

diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
index e630f8661e1..70c19c49ae4 100644
--- a/target/riscv/insn_trans/trans_rvv.c.inc
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
@@ -379,6 +379,35 @@ static bool vext_check_ld_index(DisasContext *s, int vd, int vs2,
     return ret;
 }
 
+/*
+ * Check whether a vector register is used to provide source operands with
+ * more than one EEW for the vector instruction.
+ * Returns true if the instruction has valid encoding
+ * Returns false if encoding violates the mismatched input EEWs constraint
+ */
+static bool vext_check_input_eew(DisasContext *s, int vs1, uint8_t eew_vs1,
+                                 int vs2, uint8_t eew_vs2, int vm)
+{
+    bool is_valid = true;
+    int8_t emul_vs1 = eew_vs1 - s->sew + s->lmul;
+    int8_t emul_vs2 = eew_vs2 - s->sew + s->lmul;
+
+    /* When vm is 0, vs1 & vs2(EEW!=1) group can't overlap v0 (EEW=1) */
+    if ((vs1 != -1 && !require_vm(vm, vs1)) ||
+        (vs2 != -1 && !require_vm(vm, vs2))) {
+        is_valid = false;
+    }
+
+    /* When eew_vs1 != eew_vs2, check whether vs1 and vs2 are overlapped */
+    if ((vs1 != -1 && vs2 != -1) && (eew_vs1 != eew_vs2) &&
+        is_overlapped(vs1, 1 << MAX(emul_vs1, 0),
+                      vs2, 1 << MAX(emul_vs2, 0))) {
+        is_valid = false;
+    }
+
+    return is_valid;
+}
+
 static bool vext_check_ss(DisasContext *s, int vd, int vs, int vm)
 {
     return require_vm(vm, vd) &&
-- 
2.43.0

[PATCH v2 04/12] target/riscv: rvv: Apply vext_check_input_eew to vector register gather instructions

[Max Chou]

Handle the overlap of source registers with different EEWs.
The vs1 EEW of vrgatherei16.vv is 16.

Co-authored-by: Anton Blanchard <antonb@tenstorrent.com>
Co-authored-by: Max Chou <max.chou@sifive.com>
Signed-off-by: Max Chou <max.chou@sifive.com>
---
 target/riscv/insn_trans/trans_rvv.c.inc | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
index 70c19c49ae4..4a0c9fbeff3 100644
--- a/target/riscv/insn_trans/trans_rvv.c.inc
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
@@ -3478,6 +3478,7 @@ static bool vrgather_vv_check(DisasContext *s, arg_rmrr *a)
 {
     return require_rvv(s) &&
            vext_check_isa_ill(s) &&
+           vext_check_input_eew(s, a->rs1, s->sew, a->rs2, s->sew, a->vm) &&
            require_align(a->rd, s->lmul) &&
            require_align(a->rs1, s->lmul) &&
            require_align(a->rs2, s->lmul) &&
@@ -3490,6 +3491,7 @@ static bool vrgatherei16_vv_check(DisasContext *s, arg_rmrr *a)
     int8_t emul = MO_16 - s->sew + s->lmul;
     return require_rvv(s) &&
            vext_check_isa_ill(s) &&
+           vext_check_input_eew(s, a->rs1, MO_16, a->rs2, s->sew, a->vm) &&
            (emul >= -3 && emul <= 3) &&
            require_align(a->rd, s->lmul) &&
            require_align(a->rs1, emul) &&
@@ -3509,6 +3511,7 @@ static bool vrgather_vx_check(DisasContext *s, arg_rmrr *a)
 {
     return require_rvv(s) &&
            vext_check_isa_ill(s) &&
+           vext_check_input_eew(s, -1, MO_64, a->rs2, s->sew, a->vm) &&
            require_align(a->rd, s->lmul) &&
            require_align(a->rs2, s->lmul) &&
            (a->rd != a->rs2) &&
-- 
2.43.0

[PATCH v2 05/12] target/riscv: rvv: Apply vext_check_input_eew to OPIVI/OPIVX/OPFVF(vext_check_ss) instructions

[Max Chou]

Handle the overlap of source registers with different EEWs.

Co-authored-by: Anton Blanchard <antonb@tenstorrent.com>
Co-authored-by: Max Chou <max.chou@sifive.com>
Signed-off-by: Max Chou <max.chou@sifive.com>
---
 target/riscv/insn_trans/trans_rvv.c.inc | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
index 4a0c9fbeff3..3d02a2f9ec8 100644
--- a/target/riscv/insn_trans/trans_rvv.c.inc
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
@@ -412,7 +412,9 @@ static bool vext_check_ss(DisasContext *s, int vd, int vs, int vm)
 {
     return require_vm(vm, vd) &&
            require_align(vd, s->lmul) &&
-           require_align(vs, s->lmul);
+           require_align(vs, s->lmul) &&
+           vext_check_input_eew(s, vs, s->sew, -1, s->sew, vm);
+
 }
 
 /*
-- 
2.43.0

[PATCH v2 06/12] target/riscv: rvv: Apply vext_check_input_eew to OPIVV/OPFVV(vext_check_sss) instructions

[Max Chou]

Handle the overlap of source registers with different EEWs.

Co-authored-by: Anton Blanchard <antonb@tenstorrent.com>
Co-authored-by: Max Chou <max.chou@sifive.com>
Signed-off-by: Max Chou <max.chou@sifive.com>
---
 target/riscv/insn_trans/trans_rvv.c.inc | 1 +
 1 file changed, 1 insertion(+)

diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
index 3d02a2f9ec8..2282b89801c 100644
--- a/target/riscv/insn_trans/trans_rvv.c.inc
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
@@ -433,6 +433,7 @@ static bool vext_check_ss(DisasContext *s, int vd, int vs, int vm)
 static bool vext_check_sss(DisasContext *s, int vd, int vs1, int vs2, int vm)
 {
     return vext_check_ss(s, vd, vs2, vm) &&
+           vext_check_input_eew(s, vs1, s->sew, vs2, s->sew, vm) &&
            require_align(vs1, s->lmul);
 }
 
-- 
2.43.0

[PATCH v2 07/12] target/riscv: rvv: Apply vext_check_input_eew to vector slide instructions(OPIVI/OPIVX)

[Max Chou]

Handle the overlap of source registers with different EEWs.

Co-authored-by: Anton Blanchard <antonb@tenstorrent.com>
Co-authored-by: Max Chou <max.chou@sifive.com>
Signed-off-by: Max Chou <max.chou@sifive.com>
---
 target/riscv/insn_trans/trans_rvv.c.inc | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
index 2282b89801c..f397ae46446 100644
--- a/target/riscv/insn_trans/trans_rvv.c.inc
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
@@ -639,7 +639,9 @@ static bool vext_check_slide(DisasContext *s, int vd, int vs2,
 {
     bool ret = require_align(vs2, s->lmul) &&
                require_align(vd, s->lmul) &&
-               require_vm(vm, vd);
+               require_vm(vm, vd) &&
+               vext_check_input_eew(s, -1, 0, vs2, s->sew, vm);
+
     if (is_over) {
         ret &= (vd != vs2);
     }
-- 
2.43.0

[PATCH v2 08/12] target/riscv: rvv: Apply vext_check_input_eew to vector integer extension instructions(OPMVV)

[Max Chou]

Handle the overlap of source registers with different EEWs.

Co-authored-by: Anton Blanchard <antonb@tenstorrent.com>
Co-authored-by: Max Chou <max.chou@sifive.com>
Signed-off-by: Max Chou <max.chou@sifive.com>
---
 target/riscv/insn_trans/trans_rvv.c.inc | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
index f397ae46446..728912fc1f2 100644
--- a/target/riscv/insn_trans/trans_rvv.c.inc
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
@@ -3660,7 +3660,9 @@ static bool int_ext_check(DisasContext *s, arg_rmr *a, uint8_t div)
         require_align(a->rd, s->lmul) &&
         require_align(a->rs2, s->lmul - div) &&
         require_vm(a->vm, a->rd) &&
-        require_noover(a->rd, s->lmul, a->rs2, s->lmul - div);
+        require_noover(a->rd, s->lmul, a->rs2, s->lmul - div) &&
+        vext_check_input_eew(s, -1, 0, a->rs2, s->sew, a->vm);
+
     return ret;
 }
 
-- 
2.43.0

[PATCH v2 09/12] target/riscv: rvv: Apply vext_check_input_eew to vector widen instructions(OPMVV/OPMVX/etc.)

[Max Chou]

Handle the overlap of source registers with different EEWs.
The vd of vector widening mul-add instructions is one of the input
operands.

Co-authored-by: Anton Blanchard <antonb@tenstorrent.com>
Co-authored-by: Max Chou <max.chou@sifive.com>
Signed-off-by: Max Chou <max.chou@sifive.com>
---
 target/riscv/insn_trans/trans_rvbf16.c.inc |  9 ++-
 target/riscv/insn_trans/trans_rvv.c.inc    | 73 +++++++++++++++++-----
 2 files changed, 65 insertions(+), 17 deletions(-)

diff --git a/target/riscv/insn_trans/trans_rvbf16.c.inc b/target/riscv/insn_trans/trans_rvbf16.c.inc
index 0a9cd1ec315..066dc364c5b 100644
--- a/target/riscv/insn_trans/trans_rvbf16.c.inc
+++ b/target/riscv/insn_trans/trans_rvbf16.c.inc
@@ -119,8 +119,11 @@ static bool trans_vfwmaccbf16_vv(DisasContext *ctx, arg_vfwmaccbf16_vv *a)
     REQUIRE_FPU;
     REQUIRE_ZVFBFWMA(ctx);
 
+    uint8_t sew = ctx->sew;
     if (require_rvv(ctx) && vext_check_isa_ill(ctx) && (ctx->sew == MO_16) &&
-        vext_check_dss(ctx, a->rd, a->rs1, a->rs2, a->vm)) {
+        vext_check_dss(ctx, a->rd, a->rs1, a->rs2, a->vm) &&
+        vext_check_input_eew(ctx, a->rd, sew + 1, a->rs1, sew, a->vm) &&
+        vext_check_input_eew(ctx, a->rd, sew + 1, a->rs2, sew, a->vm)) {
         uint32_t data = 0;
 
         gen_set_rm_chkfrm(ctx, RISCV_FRM_DYN);
@@ -146,8 +149,10 @@ static bool trans_vfwmaccbf16_vf(DisasContext *ctx, arg_vfwmaccbf16_vf *a)
     REQUIRE_FPU;
     REQUIRE_ZVFBFWMA(ctx);
 
+    uint8_t sew = ctx->sew;
     if (require_rvv(ctx) && (ctx->sew == MO_16) && vext_check_isa_ill(ctx) &&
-        vext_check_ds(ctx, a->rd, a->rs2, a->vm)) {
+        vext_check_ds(ctx, a->rd, a->rs2, a->vm) &&
+        vext_check_input_eew(ctx, a->rd, sew + 1, a->rs2, sew, a->vm)) {
         uint32_t data = 0;
 
         gen_set_rm(ctx, RISCV_FRM_DYN);
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
index 728912fc1f2..f30157939b8 100644
--- a/target/riscv/insn_trans/trans_rvv.c.inc
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
@@ -529,6 +529,7 @@ static bool vext_narrow_check_common(DisasContext *s, int vd, int vs2,
 static bool vext_check_ds(DisasContext *s, int vd, int vs, int vm)
 {
     return vext_wide_check_common(s, vd, vm) &&
+           vext_check_input_eew(s, vs, s->sew, -1, 0, vm) &&
            require_align(vs, s->lmul) &&
            require_noover(vd, s->lmul + 1, vs, s->lmul);
 }
@@ -536,6 +537,7 @@ static bool vext_check_ds(DisasContext *s, int vd, int vs, int vm)
 static bool vext_check_dd(DisasContext *s, int vd, int vs, int vm)
 {
     return vext_wide_check_common(s, vd, vm) &&
+           vext_check_input_eew(s, vs, s->sew + 1, -1, 0, vm) &&
            require_align(vs, s->lmul + 1);
 }
 
@@ -554,6 +556,7 @@ static bool vext_check_dd(DisasContext *s, int vd, int vs, int vm)
 static bool vext_check_dss(DisasContext *s, int vd, int vs1, int vs2, int vm)
 {
     return vext_check_ds(s, vd, vs2, vm) &&
+           vext_check_input_eew(s, vs1, s->sew, vs2, s->sew, vm) &&
            require_align(vs1, s->lmul) &&
            require_noover(vd, s->lmul + 1, vs1, s->lmul);
 }
@@ -576,6 +579,7 @@ static bool vext_check_dss(DisasContext *s, int vd, int vs1, int vs2, int vm)
 static bool vext_check_dds(DisasContext *s, int vd, int vs1, int vs2, int vm)
 {
     return vext_check_ds(s, vd, vs1, vm) &&
+           vext_check_input_eew(s, vs1, s->sew, vs2, s->sew + 1, vm) &&
            require_align(vs2, s->lmul + 1);
 }
 
@@ -1532,6 +1536,16 @@ static bool opivv_widen_check(DisasContext *s, arg_rmrr *a)
            vext_check_dss(s, a->rd, a->rs1, a->rs2, a->vm);
 }
 
+/* OPIVV with overwrite and WIDEN */
+static bool opivv_overwrite_widen_check(DisasContext *s, arg_rmrr *a)
+{
+    return require_rvv(s) &&
+           vext_check_isa_ill(s) &&
+           vext_check_dss(s, a->rd, a->rs1, a->rs2, a->vm) &&
+           vext_check_input_eew(s, a->rd, s->sew + 1, a->rs1, s->sew, a->vm) &&
+           vext_check_input_eew(s, a->rd, s->sew + 1, a->rs2, s->sew, a->vm);
+}
+
 static bool do_opivv_widen(DisasContext *s, arg_rmrr *a,
                            gen_helper_gvec_4_ptr *fn,
                            bool (*checkfn)(DisasContext *, arg_rmrr *))
@@ -1579,6 +1593,14 @@ static bool opivx_widen_check(DisasContext *s, arg_rmrr *a)
            vext_check_ds(s, a->rd, a->rs2, a->vm);
 }
 
+static bool opivx_overwrite_widen_check(DisasContext *s, arg_rmrr *a)
+{
+    return require_rvv(s) &&
+           vext_check_isa_ill(s) &&
+           vext_check_ds(s, a->rd, a->rs2, a->vm) &&
+           vext_check_input_eew(s, a->rd, s->sew + 1, a->rs2, s->sew, a->vm);
+}
+
 #define GEN_OPIVX_WIDEN_TRANS(NAME, CHECK) \
 static bool trans_##NAME(DisasContext *s, arg_rmrr *a)                    \
 {                                                                         \
@@ -2050,13 +2072,13 @@ GEN_OPIVX_TRANS(vmadd_vx, opivx_check)
 GEN_OPIVX_TRANS(vnmsub_vx, opivx_check)
 
 /* Vector Widening Integer Multiply-Add Instructions */
-GEN_OPIVV_WIDEN_TRANS(vwmaccu_vv, opivv_widen_check)
-GEN_OPIVV_WIDEN_TRANS(vwmacc_vv, opivv_widen_check)
-GEN_OPIVV_WIDEN_TRANS(vwmaccsu_vv, opivv_widen_check)
-GEN_OPIVX_WIDEN_TRANS(vwmaccu_vx, opivx_widen_check)
-GEN_OPIVX_WIDEN_TRANS(vwmacc_vx, opivx_widen_check)
-GEN_OPIVX_WIDEN_TRANS(vwmaccsu_vx, opivx_widen_check)
-GEN_OPIVX_WIDEN_TRANS(vwmaccus_vx, opivx_widen_check)
+GEN_OPIVV_WIDEN_TRANS(vwmaccu_vv, opivv_overwrite_widen_check)
+GEN_OPIVV_WIDEN_TRANS(vwmacc_vv, opivv_overwrite_widen_check)
+GEN_OPIVV_WIDEN_TRANS(vwmaccsu_vv, opivv_overwrite_widen_check)
+GEN_OPIVX_WIDEN_TRANS(vwmaccu_vx, opivx_overwrite_widen_check)
+GEN_OPIVX_WIDEN_TRANS(vwmacc_vx, opivx_overwrite_widen_check)
+GEN_OPIVX_WIDEN_TRANS(vwmaccsu_vx, opivx_overwrite_widen_check)
+GEN_OPIVX_WIDEN_TRANS(vwmaccus_vx, opivx_overwrite_widen_check)
 
 /* Vector Integer Merge and Move Instructions */
 static bool trans_vmv_v_v(DisasContext *s, arg_vmv_v_v *a)
@@ -2397,6 +2419,17 @@ static bool opfvv_widen_check(DisasContext *s, arg_rmrr *a)
            vext_check_dss(s, a->rd, a->rs1, a->rs2, a->vm);
 }
 
+static bool opfvv_overwrite_widen_check(DisasContext *s, arg_rmrr *a)
+{
+    return require_rvv(s) &&
+           require_rvf(s) &&
+           require_scale_rvf(s) &&
+           vext_check_isa_ill(s) &&
+           vext_check_dss(s, a->rd, a->rs1, a->rs2, a->vm) &&
+           vext_check_input_eew(s, a->rd, s->sew + 1, a->rs1, s->sew, a->vm) &&
+           vext_check_input_eew(s, a->rd, s->sew + 1, a->rs2, s->sew, a->vm);
+}
+
 /* OPFVV with WIDEN */
 #define GEN_OPFVV_WIDEN_TRANS(NAME, CHECK)                       \
 static bool trans_##NAME(DisasContext *s, arg_rmrr *a)           \
@@ -2436,6 +2469,16 @@ static bool opfvf_widen_check(DisasContext *s, arg_rmrr *a)
            vext_check_ds(s, a->rd, a->rs2, a->vm);
 }
 
+static bool opfvf_overwrite_widen_check(DisasContext *s, arg_rmrr *a)
+{
+    return require_rvv(s) &&
+           require_rvf(s) &&
+           require_scale_rvf(s) &&
+           vext_check_isa_ill(s) &&
+           vext_check_ds(s, a->rd, a->rs2, a->vm) &&
+           vext_check_input_eew(s, a->rd, s->sew + 1, a->rs2, s->sew, a->vm);
+}
+
 /* OPFVF with WIDEN */
 #define GEN_OPFVF_WIDEN_TRANS(NAME, CHECK)                       \
 static bool trans_##NAME(DisasContext *s, arg_rmrr *a)           \
@@ -2560,14 +2603,14 @@ GEN_OPFVF_TRANS(vfmsub_vf, opfvf_check)
 GEN_OPFVF_TRANS(vfnmsub_vf, opfvf_check)
 
 /* Vector Widening Floating-Point Fused Multiply-Add Instructions */
-GEN_OPFVV_WIDEN_TRANS(vfwmacc_vv, opfvv_widen_check)
-GEN_OPFVV_WIDEN_TRANS(vfwnmacc_vv, opfvv_widen_check)
-GEN_OPFVV_WIDEN_TRANS(vfwmsac_vv, opfvv_widen_check)
-GEN_OPFVV_WIDEN_TRANS(vfwnmsac_vv, opfvv_widen_check)
-GEN_OPFVF_WIDEN_TRANS(vfwmacc_vf, opfvf_widen_check)
-GEN_OPFVF_WIDEN_TRANS(vfwnmacc_vf, opfvf_widen_check)
-GEN_OPFVF_WIDEN_TRANS(vfwmsac_vf, opfvf_widen_check)
-GEN_OPFVF_WIDEN_TRANS(vfwnmsac_vf, opfvf_widen_check)
+GEN_OPFVV_WIDEN_TRANS(vfwmacc_vv, opfvv_overwrite_widen_check)
+GEN_OPFVV_WIDEN_TRANS(vfwnmacc_vv, opfvv_overwrite_widen_check)
+GEN_OPFVV_WIDEN_TRANS(vfwmsac_vv, opfvv_overwrite_widen_check)
+GEN_OPFVV_WIDEN_TRANS(vfwnmsac_vv, opfvv_overwrite_widen_check)
+GEN_OPFVF_WIDEN_TRANS(vfwmacc_vf, opfvf_overwrite_widen_check)
+GEN_OPFVF_WIDEN_TRANS(vfwnmacc_vf, opfvf_overwrite_widen_check)
+GEN_OPFVF_WIDEN_TRANS(vfwmsac_vf, opfvf_overwrite_widen_check)
+GEN_OPFVF_WIDEN_TRANS(vfwnmsac_vf, opfvf_overwrite_widen_check)
 
 /* Vector Floating-Point Square-Root Instruction */
 
-- 
2.43.0

[PATCH v2 10/12] target/riscv: rvv: Apply vext_check_input_eew to vector narrow instructions

[Max Chou]

Handle the overlap of source registers with different EEWs.

Co-authored-by: Anton Blanchard <antonb@tenstorrent.com>
Co-authored-by: Max Chou <max.chou@sifive.com>
Signed-off-by: Max Chou <max.chou@sifive.com>
---
 target/riscv/insn_trans/trans_rvv.c.inc | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
index f30157939b8..d4d1ad055fa 100644
--- a/target/riscv/insn_trans/trans_rvv.c.inc
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
@@ -585,7 +585,8 @@ static bool vext_check_dds(DisasContext *s, int vd, int vs1, int vs2, int vm)
 
 static bool vext_check_sd(DisasContext *s, int vd, int vs, int vm)
 {
-    bool ret = vext_narrow_check_common(s, vd, vs, vm);
+    bool ret = vext_narrow_check_common(s, vd, vs, vm) &&
+               vext_check_input_eew(s, vs, s->sew + 1, -1, 0, vm);
     if (vd != vs) {
         ret &= require_noover(vd, s->lmul, vs, s->lmul + 1);
     }
@@ -608,6 +609,7 @@ static bool vext_check_sd(DisasContext *s, int vd, int vs, int vm)
 static bool vext_check_sds(DisasContext *s, int vd, int vs1, int vs2, int vm)
 {
     return vext_check_sd(s, vd, vs2, vm) &&
+           vext_check_input_eew(s, vs1, s->sew, vs2, s->sew + 1, vm) &&
            require_align(vs1, s->lmul);
 }
 
-- 
2.43.0

[PATCH v2 11/12] target/riscv: rvv: Apply vext_check_input_eew to vector indexed load/store instructions

[Max Chou]

Handle the overlap of source registers with different EEWs.

Co-authored-by: Anton Blanchard <antonb@tenstorrent.com>
Co-authored-by: Max Chou <max.chou@sifive.com>
Signed-off-by: Max Chou <max.chou@sifive.com>
---
 target/riscv/insn_trans/trans_rvv.c.inc | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
index d4d1ad055fa..3b36464176a 100644
--- a/target/riscv/insn_trans/trans_rvv.c.inc
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
@@ -1044,7 +1044,8 @@ static bool ld_index_check(DisasContext *s, arg_rnfvm* a, uint8_t eew)
 {
     return require_rvv(s) &&
            vext_check_isa_ill(s) &&
-           vext_check_ld_index(s, a->rd, a->rs2, a->nf, a->vm, eew);
+           vext_check_ld_index(s, a->rd, a->rs2, a->nf, a->vm, eew) &&
+           vext_check_input_eew(s, -1, 0, a->rs2, eew, a->vm);
 }
 
 GEN_VEXT_TRANS(vlxei8_v,  MO_8,  rnfvm, ld_index_op, ld_index_check)
@@ -1096,7 +1097,8 @@ static bool st_index_check(DisasContext *s, arg_rnfvm* a, uint8_t eew)
 {
     return require_rvv(s) &&
            vext_check_isa_ill(s) &&
-           vext_check_st_index(s, a->rd, a->rs2, a->nf, eew);
+           vext_check_st_index(s, a->rd, a->rs2, a->nf, eew) &&
+           vext_check_input_eew(s, a->rd, s->sew, a->rs2, eew, a->vm);
 }
 
 GEN_VEXT_TRANS(vsxei8_v,  MO_8,  rnfvm, st_index_op, st_index_check)
-- 
2.43.0

[PATCH v2 12/12] target/riscv: Fix the rvv reserved encoding of unmasked instructions

[Max Chou]

According to the v spec, the encodings of vcomoress.vm and vector
mask-register logical instructions with vm=0 are reserved.

Signed-off-by: Max Chou <max.chou@sifive.com>
---
 target/riscv/insn32.decode | 18 +++++++++---------
 1 file changed, 9 insertions(+), 9 deletions(-)

diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index 6d1a13c8260..cd23b1f3a9b 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -703,14 +703,14 @@ vfredmax_vs     000111 . ..... ..... 001 ..... 1010111 @r_vm
 # Vector widening ordered and unordered float reduction sum
 vfwredusum_vs   110001 . ..... ..... 001 ..... 1010111 @r_vm
 vfwredosum_vs   110011 . ..... ..... 001 ..... 1010111 @r_vm
-vmand_mm        011001 - ..... ..... 010 ..... 1010111 @r
-vmnand_mm       011101 - ..... ..... 010 ..... 1010111 @r
-vmandn_mm       011000 - ..... ..... 010 ..... 1010111 @r
-vmxor_mm        011011 - ..... ..... 010 ..... 1010111 @r
-vmor_mm         011010 - ..... ..... 010 ..... 1010111 @r
-vmnor_mm        011110 - ..... ..... 010 ..... 1010111 @r
-vmorn_mm        011100 - ..... ..... 010 ..... 1010111 @r
-vmxnor_mm       011111 - ..... ..... 010 ..... 1010111 @r
+vmand_mm        011001 1 ..... ..... 010 ..... 1010111 @r
+vmnand_mm       011101 1 ..... ..... 010 ..... 1010111 @r
+vmandn_mm       011000 1 ..... ..... 010 ..... 1010111 @r
+vmxor_mm        011011 1 ..... ..... 010 ..... 1010111 @r
+vmor_mm         011010 1 ..... ..... 010 ..... 1010111 @r
+vmnor_mm        011110 1 ..... ..... 010 ..... 1010111 @r
+vmorn_mm        011100 1 ..... ..... 010 ..... 1010111 @r
+vmxnor_mm       011111 1 ..... ..... 010 ..... 1010111 @r
 vcpop_m         010000 . ..... 10000 010 ..... 1010111 @r2_vm
 vfirst_m        010000 . ..... 10001 010 ..... 1010111 @r2_vm
 vmsbf_m         010100 . ..... 00001 010 ..... 1010111 @r2_vm
@@ -732,7 +732,7 @@ vrgather_vv     001100 . ..... ..... 000 ..... 1010111 @r_vm
 vrgatherei16_vv 001110 . ..... ..... 000 ..... 1010111 @r_vm
 vrgather_vx     001100 . ..... ..... 100 ..... 1010111 @r_vm
 vrgather_vi     001100 . ..... ..... 011 ..... 1010111 @r_vm
-vcompress_vm    010111 - ..... ..... 010 ..... 1010111 @r
+vcompress_vm    010111 1 ..... ..... 010 ..... 1010111 @r
 vmv1r_v         100111 1 ..... 00000 011 ..... 1010111 @r2rd
 vmv2r_v         100111 1 ..... 00001 011 ..... 1010111 @r2rd
 vmv4r_v         100111 1 ..... 00011 011 ..... 1010111 @r2rd
-- 
2.43.0

Re: [PATCH v2 01/12] target/riscv: rvv: Source vector registers cannot overlap mask register

[Daniel Henrique Barboza]

On 3/29/25 11:44 AM, Max Chou wrote:
> From: Anton Blanchard <antonb@tenstorrent.com>
> 
> Add the relevant ISA paragraphs explaining why source (and destination)
> registers cannot overlap the mask register.
> 
> Signed-off-by: Anton Blanchard <antonb@tenstorrent.com>
> Signed-off-by: Max Chou <max.chou@sifive.com>
> ---


Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>

>   target/riscv/insn_trans/trans_rvv.c.inc | 29 ++++++++++++++++++++++---
>   1 file changed, 26 insertions(+), 3 deletions(-)
> 
> diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
> index b9883a5d323..20b1cb127b4 100644
> --- a/target/riscv/insn_trans/trans_rvv.c.inc
> +++ b/target/riscv/insn_trans/trans_rvv.c.inc
> @@ -100,10 +100,33 @@ static bool require_scale_rvfmin(DisasContext *s)
>       }
>   }
>   
> -/* Destination vector register group cannot overlap source mask register. */
> -static bool require_vm(int vm, int vd)
> +/*
> + * Source and destination vector register groups cannot overlap source mask
> + * register:
> + *
> + * A vector register cannot be used to provide source operands with more than
> + * one EEW for a single instruction. A mask register source is considered to
> + * have EEW=1 for this constraint. An encoding that would result in the same
> + * vector register being read with two or more different EEWs, including when
> + * the vector register appears at different positions within two or more vector
> + * register groups, is reserved.
> + * (Section 5.2)
> + *
> + * A destination vector register group can overlap a source vector
> + * register group only if one of the following holds:
> + *  1. The destination EEW equals the source EEW.
> + *  2. The destination EEW is smaller than the source EEW and the overlap
> + *     is in the lowest-numbered part of the source register group.
> + *  3. The destination EEW is greater than the source EEW, the source EMUL
> + *     is at least 1, and the overlap is in the highest-numbered part of
> + *     the destination register group.
> + * For the purpose of determining register group overlap constraints, mask
> + * elements have EEW=1.
> + * (Section 5.2)
> + */
> +static bool require_vm(int vm, int v)
>   {
> -    return (vm != 0 || vd != 0);
> +    return (vm != 0 || v != 0);
>   }
>   
>   static bool require_nf(int vd, int nf, int lmul)

Re: [PATCH v2 02/12] target/riscv: rvv: Add CHECK arg to GEN_OPFVF_WIDEN_TRANS

[Daniel Henrique Barboza]

On 3/29/25 11:44 AM, Max Chou wrote:
> From: Anton Blanchard <antonb@tenstorrent.com>
> 
> Signed-off-by: Anton Blanchard <antonb@tenstorrent.com>
> Signed-off-by: Max Chou <max.chou@sifive.com>
> ---

Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>

>   target/riscv/insn_trans/trans_rvv.c.inc | 18 +++++++++---------
>   1 file changed, 9 insertions(+), 9 deletions(-)
> 
> diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
> index 20b1cb127b4..e630f8661e1 100644
> --- a/target/riscv/insn_trans/trans_rvv.c.inc
> +++ b/target/riscv/insn_trans/trans_rvv.c.inc
> @@ -2403,10 +2403,10 @@ static bool opfvf_widen_check(DisasContext *s, arg_rmrr *a)
>   }
>   
>   /* OPFVF with WIDEN */
> -#define GEN_OPFVF_WIDEN_TRANS(NAME)                              \
> +#define GEN_OPFVF_WIDEN_TRANS(NAME, CHECK)                       \
>   static bool trans_##NAME(DisasContext *s, arg_rmrr *a)           \
>   {                                                                \
> -    if (opfvf_widen_check(s, a)) {                               \
> +    if (CHECK(s, a)) {                                           \
>           uint32_t data = 0;                                       \
>           static gen_helper_opfvf *const fns[2] = {                \
>               gen_helper_##NAME##_h, gen_helper_##NAME##_w,        \
> @@ -2422,8 +2422,8 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a)           \
>       return false;                                                \
>   }
>   
> -GEN_OPFVF_WIDEN_TRANS(vfwadd_vf)
> -GEN_OPFVF_WIDEN_TRANS(vfwsub_vf)
> +GEN_OPFVF_WIDEN_TRANS(vfwadd_vf, opfvf_widen_check)
> +GEN_OPFVF_WIDEN_TRANS(vfwsub_vf, opfvf_widen_check)
>   
>   static bool opfwv_widen_check(DisasContext *s, arg_rmrr *a)
>   {
> @@ -2505,7 +2505,7 @@ GEN_OPFVF_TRANS(vfrdiv_vf,  opfvf_check)
>   
>   /* Vector Widening Floating-Point Multiply */
>   GEN_OPFVV_WIDEN_TRANS(vfwmul_vv, opfvv_widen_check)
> -GEN_OPFVF_WIDEN_TRANS(vfwmul_vf)
> +GEN_OPFVF_WIDEN_TRANS(vfwmul_vf, opfvf_widen_check)
>   
>   /* Vector Single-Width Floating-Point Fused Multiply-Add Instructions */
>   GEN_OPFVV_TRANS(vfmacc_vv, opfvv_check)
> @@ -2530,10 +2530,10 @@ GEN_OPFVV_WIDEN_TRANS(vfwmacc_vv, opfvv_widen_check)
>   GEN_OPFVV_WIDEN_TRANS(vfwnmacc_vv, opfvv_widen_check)
>   GEN_OPFVV_WIDEN_TRANS(vfwmsac_vv, opfvv_widen_check)
>   GEN_OPFVV_WIDEN_TRANS(vfwnmsac_vv, opfvv_widen_check)
> -GEN_OPFVF_WIDEN_TRANS(vfwmacc_vf)
> -GEN_OPFVF_WIDEN_TRANS(vfwnmacc_vf)
> -GEN_OPFVF_WIDEN_TRANS(vfwmsac_vf)
> -GEN_OPFVF_WIDEN_TRANS(vfwnmsac_vf)
> +GEN_OPFVF_WIDEN_TRANS(vfwmacc_vf, opfvf_widen_check)
> +GEN_OPFVF_WIDEN_TRANS(vfwnmacc_vf, opfvf_widen_check)
> +GEN_OPFVF_WIDEN_TRANS(vfwmsac_vf, opfvf_widen_check)
> +GEN_OPFVF_WIDEN_TRANS(vfwnmsac_vf, opfvf_widen_check)
>   
>   /* Vector Floating-Point Square-Root Instruction */
>   

Re: [PATCH v2 03/12] target/riscv: Add vext_check_input_eew to check mismatched input EEWs encoding constraint

[Daniel Henrique Barboza]

On 3/29/25 11:44 AM, Max Chou wrote:
> According to the v spec, a vector register cannot be used to provide source
> operands with more than one EEW for a single instruction.
> 
> Signed-off-by: Max Chou <max.chou@sifive.com>
> ---
>   target/riscv/insn_trans/trans_rvv.c.inc | 29 +++++++++++++++++++++++++
>   1 file changed, 29 insertions(+)
> 
> diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
> index e630f8661e1..70c19c49ae4 100644
> --- a/target/riscv/insn_trans/trans_rvv.c.inc
> +++ b/target/riscv/insn_trans/trans_rvv.c.inc
> @@ -379,6 +379,35 @@ static bool vext_check_ld_index(DisasContext *s, int vd, int vs2,
>       return ret;
>   }
>   
> +/*
> + * Check whether a vector register is used to provide source operands with
> + * more than one EEW for the vector instruction.
> + * Returns true if the instruction has valid encoding
> + * Returns false if encoding violates the mismatched input EEWs constraint
> + */
> +static bool vext_check_input_eew(DisasContext *s, int vs1, uint8_t eew_vs1,
> +                                 int vs2, uint8_t eew_vs2, int vm)
> +{
> +    bool is_valid = true;
> +    int8_t emul_vs1 = eew_vs1 - s->sew + s->lmul;
> +    int8_t emul_vs2 = eew_vs2 - s->sew + s->lmul;
> +
> +    /* When vm is 0, vs1 & vs2(EEW!=1) group can't overlap v0 (EEW=1) */
> +    if ((vs1 != -1 && !require_vm(vm, vs1)) ||
> +        (vs2 != -1 && !require_vm(vm, vs2))) {
> +        is_valid = false;
> +    }
> +
> +    /* When eew_vs1 != eew_vs2, check whether vs1 and vs2 are overlapped */
> +    if ((vs1 != -1 && vs2 != -1) && (eew_vs1 != eew_vs2) &&
> +        is_overlapped(vs1, 1 << MAX(emul_vs1, 0),
> +                      vs2, 1 << MAX(emul_vs2, 0))) {
> +        is_valid = false;
> +    }
> +
> +    return is_valid;
> +}
> +

Code LGTM but the patch won't compile on its own because there's no callers for
it:


In file included from ../target/riscv/translate.c:1182:
../target/riscv/insn_trans/trans_rvv.c.inc:388:13: error: ‘vext_check_input_eew’ defined but not used [-Werror=unused-function]
   388 | static bool vext_check_input_eew(DisasContext *s, int vs1, uint8_t eew_vs1,
       |             ^~~~~~~~~~~~~~~~~~~~
cc1: all warnings being treated as errors
ninja: build stopped: subcommand failed.


We want each patch to be "buildable" and with test passing to make our lives easier
when doing bisects.

You can merge this patch with patch 4 to introduce the new function and add its first
callers. Thanks,


Daniel



>   static bool vext_check_ss(DisasContext *s, int vd, int vs, int vm)
>   {
>       return require_vm(vm, vd) &&

Re: [PATCH v2 04/12] target/riscv: rvv: Apply vext_check_input_eew to vector register gather instructions

[Daniel Henrique Barboza]

On 3/29/25 11:44 AM, Max Chou wrote:
> Handle the overlap of source registers with different EEWs.
> The vs1 EEW of vrgatherei16.vv is 16.
> 
> Co-authored-by: Anton Blanchard <antonb@tenstorrent.com>
> Co-authored-by: Max Chou <max.chou@sifive.com>

Since you're marked as Author you don't need this co-authored-by tag
in your name too.

Same thing for patches 5 to 11.

> Signed-off-by: Max Chou <max.chou@sifive.com>
> ---

With the co-authored-by tag removed:

Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>

>   target/riscv/insn_trans/trans_rvv.c.inc | 3 +++
>   1 file changed, 3 insertions(+)
> 
> diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
> index 70c19c49ae4..4a0c9fbeff3 100644
> --- a/target/riscv/insn_trans/trans_rvv.c.inc
> +++ b/target/riscv/insn_trans/trans_rvv.c.inc
> @@ -3478,6 +3478,7 @@ static bool vrgather_vv_check(DisasContext *s, arg_rmrr *a)
>   {
>       return require_rvv(s) &&
>              vext_check_isa_ill(s) &&
> +           vext_check_input_eew(s, a->rs1, s->sew, a->rs2, s->sew, a->vm) &&
>              require_align(a->rd, s->lmul) &&
>              require_align(a->rs1, s->lmul) &&
>              require_align(a->rs2, s->lmul) &&
> @@ -3490,6 +3491,7 @@ static bool vrgatherei16_vv_check(DisasContext *s, arg_rmrr *a)
>       int8_t emul = MO_16 - s->sew + s->lmul;
>       return require_rvv(s) &&
>              vext_check_isa_ill(s) &&
> +           vext_check_input_eew(s, a->rs1, MO_16, a->rs2, s->sew, a->vm) &&
>              (emul >= -3 && emul <= 3) &&
>              require_align(a->rd, s->lmul) &&
>              require_align(a->rs1, emul) &&
> @@ -3509,6 +3511,7 @@ static bool vrgather_vx_check(DisasContext *s, arg_rmrr *a)
>   {
>       return require_rvv(s) &&
>              vext_check_isa_ill(s) &&
> +           vext_check_input_eew(s, -1, MO_64, a->rs2, s->sew, a->vm) &&
>              require_align(a->rd, s->lmul) &&
>              require_align(a->rs2, s->lmul) &&
>              (a->rd != a->rs2) &&

Re: [PATCH v2 05/12] target/riscv: rvv: Apply vext_check_input_eew to OPIVI/OPIVX/OPFVF(vext_check_ss) instructions

[Daniel Henrique Barboza]

On 3/29/25 11:44 AM, Max Chou wrote:
> Handle the overlap of source registers with different EEWs.
> 
> Co-authored-by: Anton Blanchard <antonb@tenstorrent.com>
> Co-authored-by: Max Chou <max.chou@sifive.com>
> Signed-off-by: Max Chou <max.chou@sifive.com>
> ---
>   target/riscv/insn_trans/trans_rvv.c.inc | 4 +++-
>   1 file changed, 3 insertions(+), 1 deletion(-)
> 
> diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
> index 4a0c9fbeff3..3d02a2f9ec8 100644
> --- a/target/riscv/insn_trans/trans_rvv.c.inc
> +++ b/target/riscv/insn_trans/trans_rvv.c.inc
> @@ -412,7 +412,9 @@ static bool vext_check_ss(DisasContext *s, int vd, int vs, int vm)
>   {
>       return require_vm(vm, vd) &&
>              require_align(vd, s->lmul) &&
> -           require_align(vs, s->lmul);
> +           require_align(vs, s->lmul) &&
> +           vext_check_input_eew(s, vs, s->sew, -1, s->sew, vm);
> +

Please remove the extra blank line. And with your co-authored-by removed:

Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>

>   }
>   
>   /*

Re: [PATCH v2 06/12] target/riscv: rvv: Apply vext_check_input_eew to OPIVV/OPFVV(vext_check_sss) instructions

[Daniel Henrique Barboza]

On 3/29/25 11:44 AM, Max Chou wrote:
> Handle the overlap of source registers with different EEWs.
> 
> Co-authored-by: Anton Blanchard <antonb@tenstorrent.com>
> Co-authored-by: Max Chou <max.chou@sifive.com>
> Signed-off-by: Max Chou <max.chou@sifive.com>
> ---

With your co-authored-by tag removed:

Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>

>   target/riscv/insn_trans/trans_rvv.c.inc | 1 +
>   1 file changed, 1 insertion(+)
> 
> diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
> index 3d02a2f9ec8..2282b89801c 100644
> --- a/target/riscv/insn_trans/trans_rvv.c.inc
> +++ b/target/riscv/insn_trans/trans_rvv.c.inc
> @@ -433,6 +433,7 @@ static bool vext_check_ss(DisasContext *s, int vd, int vs, int vm)
>   static bool vext_check_sss(DisasContext *s, int vd, int vs1, int vs2, int vm)
>   {
>       return vext_check_ss(s, vd, vs2, vm) &&
> +           vext_check_input_eew(s, vs1, s->sew, vs2, s->sew, vm) &&
>              require_align(vs1, s->lmul);
>   }
>   

Re: [PATCH v2 07/12] target/riscv: rvv: Apply vext_check_input_eew to vector slide instructions(OPIVI/OPIVX)

[Daniel Henrique Barboza]

On 3/29/25 11:44 AM, Max Chou wrote:
> Handle the overlap of source registers with different EEWs.
> 
> Co-authored-by: Anton Blanchard <antonb@tenstorrent.com>
> Co-authored-by: Max Chou <max.chou@sifive.com>
> Signed-off-by: Max Chou <max.chou@sifive.com>
> ---


With your co-authored-by tag removed:

Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>

>   target/riscv/insn_trans/trans_rvv.c.inc | 4 +++-
>   1 file changed, 3 insertions(+), 1 deletion(-)
> 
> diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
> index 2282b89801c..f397ae46446 100644
> --- a/target/riscv/insn_trans/trans_rvv.c.inc
> +++ b/target/riscv/insn_trans/trans_rvv.c.inc
> @@ -639,7 +639,9 @@ static bool vext_check_slide(DisasContext *s, int vd, int vs2,
>   {
>       bool ret = require_align(vs2, s->lmul) &&
>                  require_align(vd, s->lmul) &&
> -               require_vm(vm, vd);
> +               require_vm(vm, vd) &&
> +               vext_check_input_eew(s, -1, 0, vs2, s->sew, vm);
> +
>       if (is_over) {
>           ret &= (vd != vs2);
>       }

Re: [PATCH v2 08/12] target/riscv: rvv: Apply vext_check_input_eew to vector integer extension instructions(OPMVV)

[Daniel Henrique Barboza]

On 3/29/25 11:44 AM, Max Chou wrote:
> Handle the overlap of source registers with different EEWs.
> 
> Co-authored-by: Anton Blanchard <antonb@tenstorrent.com>
> Co-authored-by: Max Chou <max.chou@sifive.com>
> Signed-off-by: Max Chou <max.chou@sifive.com>
> ---


With your co-authored-by tag removed:

Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>

>   target/riscv/insn_trans/trans_rvv.c.inc | 4 +++-
>   1 file changed, 3 insertions(+), 1 deletion(-)
> 
> diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
> index f397ae46446..728912fc1f2 100644
> --- a/target/riscv/insn_trans/trans_rvv.c.inc
> +++ b/target/riscv/insn_trans/trans_rvv.c.inc
> @@ -3660,7 +3660,9 @@ static bool int_ext_check(DisasContext *s, arg_rmr *a, uint8_t div)
>           require_align(a->rd, s->lmul) &&
>           require_align(a->rs2, s->lmul - div) &&
>           require_vm(a->vm, a->rd) &&
> -        require_noover(a->rd, s->lmul, a->rs2, s->lmul - div);
> +        require_noover(a->rd, s->lmul, a->rs2, s->lmul - div) &&
> +        vext_check_input_eew(s, -1, 0, a->rs2, s->sew, a->vm);
> +
>       return ret;
>   }
>   

Re: [PATCH v2 09/12] target/riscv: rvv: Apply vext_check_input_eew to vector widen instructions(OPMVV/OPMVX/etc.)

[Daniel Henrique Barboza]

On 3/29/25 11:44 AM, Max Chou wrote:
> Handle the overlap of source registers with different EEWs.
> The vd of vector widening mul-add instructions is one of the input
> operands.
> 
> Co-authored-by: Anton Blanchard <antonb@tenstorrent.com>
> Co-authored-by: Max Chou <max.chou@sifive.com>
> Signed-off-by: Max Chou <max.chou@sifive.com>
> ---


With your co-authored-by tag removed:

Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>

>   target/riscv/insn_trans/trans_rvbf16.c.inc |  9 ++-
>   target/riscv/insn_trans/trans_rvv.c.inc    | 73 +++++++++++++++++-----
>   2 files changed, 65 insertions(+), 17 deletions(-)
> 
> diff --git a/target/riscv/insn_trans/trans_rvbf16.c.inc b/target/riscv/insn_trans/trans_rvbf16.c.inc
> index 0a9cd1ec315..066dc364c5b 100644
> --- a/target/riscv/insn_trans/trans_rvbf16.c.inc
> +++ b/target/riscv/insn_trans/trans_rvbf16.c.inc
> @@ -119,8 +119,11 @@ static bool trans_vfwmaccbf16_vv(DisasContext *ctx, arg_vfwmaccbf16_vv *a)
>       REQUIRE_FPU;
>       REQUIRE_ZVFBFWMA(ctx);
>   
> +    uint8_t sew = ctx->sew;
>       if (require_rvv(ctx) && vext_check_isa_ill(ctx) && (ctx->sew == MO_16) &&
> -        vext_check_dss(ctx, a->rd, a->rs1, a->rs2, a->vm)) {
> +        vext_check_dss(ctx, a->rd, a->rs1, a->rs2, a->vm) &&
> +        vext_check_input_eew(ctx, a->rd, sew + 1, a->rs1, sew, a->vm) &&
> +        vext_check_input_eew(ctx, a->rd, sew + 1, a->rs2, sew, a->vm)) {
>           uint32_t data = 0;
>   
>           gen_set_rm_chkfrm(ctx, RISCV_FRM_DYN);
> @@ -146,8 +149,10 @@ static bool trans_vfwmaccbf16_vf(DisasContext *ctx, arg_vfwmaccbf16_vf *a)
>       REQUIRE_FPU;
>       REQUIRE_ZVFBFWMA(ctx);
>   
> +    uint8_t sew = ctx->sew;
>       if (require_rvv(ctx) && (ctx->sew == MO_16) && vext_check_isa_ill(ctx) &&
> -        vext_check_ds(ctx, a->rd, a->rs2, a->vm)) {
> +        vext_check_ds(ctx, a->rd, a->rs2, a->vm) &&
> +        vext_check_input_eew(ctx, a->rd, sew + 1, a->rs2, sew, a->vm)) {
>           uint32_t data = 0;
>   
>           gen_set_rm(ctx, RISCV_FRM_DYN);
> diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
> index 728912fc1f2..f30157939b8 100644
> --- a/target/riscv/insn_trans/trans_rvv.c.inc
> +++ b/target/riscv/insn_trans/trans_rvv.c.inc
> @@ -529,6 +529,7 @@ static bool vext_narrow_check_common(DisasContext *s, int vd, int vs2,
>   static bool vext_check_ds(DisasContext *s, int vd, int vs, int vm)
>   {
>       return vext_wide_check_common(s, vd, vm) &&
> +           vext_check_input_eew(s, vs, s->sew, -1, 0, vm) &&
>              require_align(vs, s->lmul) &&
>              require_noover(vd, s->lmul + 1, vs, s->lmul);
>   }
> @@ -536,6 +537,7 @@ static bool vext_check_ds(DisasContext *s, int vd, int vs, int vm)
>   static bool vext_check_dd(DisasContext *s, int vd, int vs, int vm)
>   {
>       return vext_wide_check_common(s, vd, vm) &&
> +           vext_check_input_eew(s, vs, s->sew + 1, -1, 0, vm) &&
>              require_align(vs, s->lmul + 1);
>   }
>   
> @@ -554,6 +556,7 @@ static bool vext_check_dd(DisasContext *s, int vd, int vs, int vm)
>   static bool vext_check_dss(DisasContext *s, int vd, int vs1, int vs2, int vm)
>   {
>       return vext_check_ds(s, vd, vs2, vm) &&
> +           vext_check_input_eew(s, vs1, s->sew, vs2, s->sew, vm) &&
>              require_align(vs1, s->lmul) &&
>              require_noover(vd, s->lmul + 1, vs1, s->lmul);
>   }
> @@ -576,6 +579,7 @@ static bool vext_check_dss(DisasContext *s, int vd, int vs1, int vs2, int vm)
>   static bool vext_check_dds(DisasContext *s, int vd, int vs1, int vs2, int vm)
>   {
>       return vext_check_ds(s, vd, vs1, vm) &&
> +           vext_check_input_eew(s, vs1, s->sew, vs2, s->sew + 1, vm) &&
>              require_align(vs2, s->lmul + 1);
>   }
>   
> @@ -1532,6 +1536,16 @@ static bool opivv_widen_check(DisasContext *s, arg_rmrr *a)
>              vext_check_dss(s, a->rd, a->rs1, a->rs2, a->vm);
>   }
>   
> +/* OPIVV with overwrite and WIDEN */
> +static bool opivv_overwrite_widen_check(DisasContext *s, arg_rmrr *a)
> +{
> +    return require_rvv(s) &&
> +           vext_check_isa_ill(s) &&
> +           vext_check_dss(s, a->rd, a->rs1, a->rs2, a->vm) &&
> +           vext_check_input_eew(s, a->rd, s->sew + 1, a->rs1, s->sew, a->vm) &&
> +           vext_check_input_eew(s, a->rd, s->sew + 1, a->rs2, s->sew, a->vm);
> +}
> +
>   static bool do_opivv_widen(DisasContext *s, arg_rmrr *a,
>                              gen_helper_gvec_4_ptr *fn,
>                              bool (*checkfn)(DisasContext *, arg_rmrr *))
> @@ -1579,6 +1593,14 @@ static bool opivx_widen_check(DisasContext *s, arg_rmrr *a)
>              vext_check_ds(s, a->rd, a->rs2, a->vm);
>   }
>   
> +static bool opivx_overwrite_widen_check(DisasContext *s, arg_rmrr *a)
> +{
> +    return require_rvv(s) &&
> +           vext_check_isa_ill(s) &&
> +           vext_check_ds(s, a->rd, a->rs2, a->vm) &&
> +           vext_check_input_eew(s, a->rd, s->sew + 1, a->rs2, s->sew, a->vm);
> +}
> +
>   #define GEN_OPIVX_WIDEN_TRANS(NAME, CHECK) \
>   static bool trans_##NAME(DisasContext *s, arg_rmrr *a)                    \
>   {                                                                         \
> @@ -2050,13 +2072,13 @@ GEN_OPIVX_TRANS(vmadd_vx, opivx_check)
>   GEN_OPIVX_TRANS(vnmsub_vx, opivx_check)
>   
>   /* Vector Widening Integer Multiply-Add Instructions */
> -GEN_OPIVV_WIDEN_TRANS(vwmaccu_vv, opivv_widen_check)
> -GEN_OPIVV_WIDEN_TRANS(vwmacc_vv, opivv_widen_check)
> -GEN_OPIVV_WIDEN_TRANS(vwmaccsu_vv, opivv_widen_check)
> -GEN_OPIVX_WIDEN_TRANS(vwmaccu_vx, opivx_widen_check)
> -GEN_OPIVX_WIDEN_TRANS(vwmacc_vx, opivx_widen_check)
> -GEN_OPIVX_WIDEN_TRANS(vwmaccsu_vx, opivx_widen_check)
> -GEN_OPIVX_WIDEN_TRANS(vwmaccus_vx, opivx_widen_check)
> +GEN_OPIVV_WIDEN_TRANS(vwmaccu_vv, opivv_overwrite_widen_check)
> +GEN_OPIVV_WIDEN_TRANS(vwmacc_vv, opivv_overwrite_widen_check)
> +GEN_OPIVV_WIDEN_TRANS(vwmaccsu_vv, opivv_overwrite_widen_check)
> +GEN_OPIVX_WIDEN_TRANS(vwmaccu_vx, opivx_overwrite_widen_check)
> +GEN_OPIVX_WIDEN_TRANS(vwmacc_vx, opivx_overwrite_widen_check)
> +GEN_OPIVX_WIDEN_TRANS(vwmaccsu_vx, opivx_overwrite_widen_check)
> +GEN_OPIVX_WIDEN_TRANS(vwmaccus_vx, opivx_overwrite_widen_check)
>   
>   /* Vector Integer Merge and Move Instructions */
>   static bool trans_vmv_v_v(DisasContext *s, arg_vmv_v_v *a)
> @@ -2397,6 +2419,17 @@ static bool opfvv_widen_check(DisasContext *s, arg_rmrr *a)
>              vext_check_dss(s, a->rd, a->rs1, a->rs2, a->vm);
>   }
>   
> +static bool opfvv_overwrite_widen_check(DisasContext *s, arg_rmrr *a)
> +{
> +    return require_rvv(s) &&
> +           require_rvf(s) &&
> +           require_scale_rvf(s) &&
> +           vext_check_isa_ill(s) &&
> +           vext_check_dss(s, a->rd, a->rs1, a->rs2, a->vm) &&
> +           vext_check_input_eew(s, a->rd, s->sew + 1, a->rs1, s->sew, a->vm) &&
> +           vext_check_input_eew(s, a->rd, s->sew + 1, a->rs2, s->sew, a->vm);
> +}
> +
>   /* OPFVV with WIDEN */
>   #define GEN_OPFVV_WIDEN_TRANS(NAME, CHECK)                       \
>   static bool trans_##NAME(DisasContext *s, arg_rmrr *a)           \
> @@ -2436,6 +2469,16 @@ static bool opfvf_widen_check(DisasContext *s, arg_rmrr *a)
>              vext_check_ds(s, a->rd, a->rs2, a->vm);
>   }
>   
> +static bool opfvf_overwrite_widen_check(DisasContext *s, arg_rmrr *a)
> +{
> +    return require_rvv(s) &&
> +           require_rvf(s) &&
> +           require_scale_rvf(s) &&
> +           vext_check_isa_ill(s) &&
> +           vext_check_ds(s, a->rd, a->rs2, a->vm) &&
> +           vext_check_input_eew(s, a->rd, s->sew + 1, a->rs2, s->sew, a->vm);
> +}
> +
>   /* OPFVF with WIDEN */
>   #define GEN_OPFVF_WIDEN_TRANS(NAME, CHECK)                       \
>   static bool trans_##NAME(DisasContext *s, arg_rmrr *a)           \
> @@ -2560,14 +2603,14 @@ GEN_OPFVF_TRANS(vfmsub_vf, opfvf_check)
>   GEN_OPFVF_TRANS(vfnmsub_vf, opfvf_check)
>   
>   /* Vector Widening Floating-Point Fused Multiply-Add Instructions */
> -GEN_OPFVV_WIDEN_TRANS(vfwmacc_vv, opfvv_widen_check)
> -GEN_OPFVV_WIDEN_TRANS(vfwnmacc_vv, opfvv_widen_check)
> -GEN_OPFVV_WIDEN_TRANS(vfwmsac_vv, opfvv_widen_check)
> -GEN_OPFVV_WIDEN_TRANS(vfwnmsac_vv, opfvv_widen_check)
> -GEN_OPFVF_WIDEN_TRANS(vfwmacc_vf, opfvf_widen_check)
> -GEN_OPFVF_WIDEN_TRANS(vfwnmacc_vf, opfvf_widen_check)
> -GEN_OPFVF_WIDEN_TRANS(vfwmsac_vf, opfvf_widen_check)
> -GEN_OPFVF_WIDEN_TRANS(vfwnmsac_vf, opfvf_widen_check)
> +GEN_OPFVV_WIDEN_TRANS(vfwmacc_vv, opfvv_overwrite_widen_check)
> +GEN_OPFVV_WIDEN_TRANS(vfwnmacc_vv, opfvv_overwrite_widen_check)
> +GEN_OPFVV_WIDEN_TRANS(vfwmsac_vv, opfvv_overwrite_widen_check)
> +GEN_OPFVV_WIDEN_TRANS(vfwnmsac_vv, opfvv_overwrite_widen_check)
> +GEN_OPFVF_WIDEN_TRANS(vfwmacc_vf, opfvf_overwrite_widen_check)
> +GEN_OPFVF_WIDEN_TRANS(vfwnmacc_vf, opfvf_overwrite_widen_check)
> +GEN_OPFVF_WIDEN_TRANS(vfwmsac_vf, opfvf_overwrite_widen_check)
> +GEN_OPFVF_WIDEN_TRANS(vfwnmsac_vf, opfvf_overwrite_widen_check)
>   
>   /* Vector Floating-Point Square-Root Instruction */
>   

Re: [PATCH v2 10/12] target/riscv: rvv: Apply vext_check_input_eew to vector narrow instructions

[Daniel Henrique Barboza]

On 3/29/25 11:44 AM, Max Chou wrote:
> Handle the overlap of source registers with different EEWs.
> 
> Co-authored-by: Anton Blanchard <antonb@tenstorrent.com>
> Co-authored-by: Max Chou <max.chou@sifive.com>
> Signed-off-by: Max Chou <max.chou@sifive.com>
> ---


With your co-authored-by tag removed:

Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>

>   target/riscv/insn_trans/trans_rvv.c.inc | 4 +++-
>   1 file changed, 3 insertions(+), 1 deletion(-)
> 
> diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
> index f30157939b8..d4d1ad055fa 100644
> --- a/target/riscv/insn_trans/trans_rvv.c.inc
> +++ b/target/riscv/insn_trans/trans_rvv.c.inc
> @@ -585,7 +585,8 @@ static bool vext_check_dds(DisasContext *s, int vd, int vs1, int vs2, int vm)
>   
>   static bool vext_check_sd(DisasContext *s, int vd, int vs, int vm)
>   {
> -    bool ret = vext_narrow_check_common(s, vd, vs, vm);
> +    bool ret = vext_narrow_check_common(s, vd, vs, vm) &&
> +               vext_check_input_eew(s, vs, s->sew + 1, -1, 0, vm);
>       if (vd != vs) {
>           ret &= require_noover(vd, s->lmul, vs, s->lmul + 1);
>       }
> @@ -608,6 +609,7 @@ static bool vext_check_sd(DisasContext *s, int vd, int vs, int vm)
>   static bool vext_check_sds(DisasContext *s, int vd, int vs1, int vs2, int vm)
>   {
>       return vext_check_sd(s, vd, vs2, vm) &&
> +           vext_check_input_eew(s, vs1, s->sew, vs2, s->sew + 1, vm) &&
>              require_align(vs1, s->lmul);
>   }
>   

Re: [PATCH v2 11/12] target/riscv: rvv: Apply vext_check_input_eew to vector indexed load/store instructions

[Daniel Henrique Barboza]

On 3/29/25 11:44 AM, Max Chou wrote:
> Handle the overlap of source registers with different EEWs.
> 
> Co-authored-by: Anton Blanchard <antonb@tenstorrent.com>
> Co-authored-by: Max Chou <max.chou@sifive.com>
> Signed-off-by: Max Chou <max.chou@sifive.com>
> ---


With your co-authored-by tag removed:

Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>

>   target/riscv/insn_trans/trans_rvv.c.inc | 6 ++++--
>   1 file changed, 4 insertions(+), 2 deletions(-)
> 
> diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
> index d4d1ad055fa..3b36464176a 100644
> --- a/target/riscv/insn_trans/trans_rvv.c.inc
> +++ b/target/riscv/insn_trans/trans_rvv.c.inc
> @@ -1044,7 +1044,8 @@ static bool ld_index_check(DisasContext *s, arg_rnfvm* a, uint8_t eew)
>   {
>       return require_rvv(s) &&
>              vext_check_isa_ill(s) &&
> -           vext_check_ld_index(s, a->rd, a->rs2, a->nf, a->vm, eew);
> +           vext_check_ld_index(s, a->rd, a->rs2, a->nf, a->vm, eew) &&
> +           vext_check_input_eew(s, -1, 0, a->rs2, eew, a->vm);
>   }
>   
>   GEN_VEXT_TRANS(vlxei8_v,  MO_8,  rnfvm, ld_index_op, ld_index_check)
> @@ -1096,7 +1097,8 @@ static bool st_index_check(DisasContext *s, arg_rnfvm* a, uint8_t eew)
>   {
>       return require_rvv(s) &&
>              vext_check_isa_ill(s) &&
> -           vext_check_st_index(s, a->rd, a->rs2, a->nf, eew);
> +           vext_check_st_index(s, a->rd, a->rs2, a->nf, eew) &&
> +           vext_check_input_eew(s, a->rd, s->sew, a->rs2, eew, a->vm);
>   }
>   
>   GEN_VEXT_TRANS(vsxei8_v,  MO_8,  rnfvm, st_index_op, st_index_check)

Re: [PATCH v2 12/12] target/riscv: Fix the rvv reserved encoding of unmasked instructions

[Daniel Henrique Barboza]

On 3/29/25 11:44 AM, Max Chou wrote:
> According to the v spec, the encodings of vcomoress.vm and vector
> mask-register logical instructions with vm=0 are reserved.
> 
> Signed-off-by: Max Chou <max.chou@sifive.com>
> ---

Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>

>   target/riscv/insn32.decode | 18 +++++++++---------
>   1 file changed, 9 insertions(+), 9 deletions(-)
> 
> diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
> index 6d1a13c8260..cd23b1f3a9b 100644
> --- a/target/riscv/insn32.decode
> +++ b/target/riscv/insn32.decode
> @@ -703,14 +703,14 @@ vfredmax_vs     000111 . ..... ..... 001 ..... 1010111 @r_vm
>   # Vector widening ordered and unordered float reduction sum
>   vfwredusum_vs   110001 . ..... ..... 001 ..... 1010111 @r_vm
>   vfwredosum_vs   110011 . ..... ..... 001 ..... 1010111 @r_vm
> -vmand_mm        011001 - ..... ..... 010 ..... 1010111 @r
> -vmnand_mm       011101 - ..... ..... 010 ..... 1010111 @r
> -vmandn_mm       011000 - ..... ..... 010 ..... 1010111 @r
> -vmxor_mm        011011 - ..... ..... 010 ..... 1010111 @r
> -vmor_mm         011010 - ..... ..... 010 ..... 1010111 @r
> -vmnor_mm        011110 - ..... ..... 010 ..... 1010111 @r
> -vmorn_mm        011100 - ..... ..... 010 ..... 1010111 @r
> -vmxnor_mm       011111 - ..... ..... 010 ..... 1010111 @r
> +vmand_mm        011001 1 ..... ..... 010 ..... 1010111 @r
> +vmnand_mm       011101 1 ..... ..... 010 ..... 1010111 @r
> +vmandn_mm       011000 1 ..... ..... 010 ..... 1010111 @r
> +vmxor_mm        011011 1 ..... ..... 010 ..... 1010111 @r
> +vmor_mm         011010 1 ..... ..... 010 ..... 1010111 @r
> +vmnor_mm        011110 1 ..... ..... 010 ..... 1010111 @r
> +vmorn_mm        011100 1 ..... ..... 010 ..... 1010111 @r
> +vmxnor_mm       011111 1 ..... ..... 010 ..... 1010111 @r
>   vcpop_m         010000 . ..... 10000 010 ..... 1010111 @r2_vm
>   vfirst_m        010000 . ..... 10001 010 ..... 1010111 @r2_vm
>   vmsbf_m         010100 . ..... 00001 010 ..... 1010111 @r2_vm
> @@ -732,7 +732,7 @@ vrgather_vv     001100 . ..... ..... 000 ..... 1010111 @r_vm
>   vrgatherei16_vv 001110 . ..... ..... 000 ..... 1010111 @r_vm
>   vrgather_vx     001100 . ..... ..... 100 ..... 1010111 @r_vm
>   vrgather_vi     001100 . ..... ..... 011 ..... 1010111 @r_vm
> -vcompress_vm    010111 - ..... ..... 010 ..... 1010111 @r
> +vcompress_vm    010111 1 ..... ..... 010 ..... 1010111 @r
>   vmv1r_v         100111 1 ..... 00000 011 ..... 1010111 @r2rd
>   vmv2r_v         100111 1 ..... 00001 011 ..... 1010111 @r2rd
>   vmv4r_v         100111 1 ..... 00011 011 ..... 1010111 @r2rd

Re: [PATCH v2 03/12] target/riscv: Add vext_check_input_eew to check mismatched input EEWs encoding constraint

[Max Chou]

On 2025/4/5 5:09 PM, Daniel Henrique Barboza wrote:
>
>
> On 3/29/25 11:44 AM, Max Chou wrote:
>> According to the v spec, a vector register cannot be used to provide 
>> source
>> operands with more than one EEW for a single instruction.
>>
>> Signed-off-by: Max Chou <max.chou@sifive.com>
>> ---
>>   target/riscv/insn_trans/trans_rvv.c.inc | 29 +++++++++++++++++++++++++
>>   1 file changed, 29 insertions(+)
>>
>> diff --git a/target/riscv/insn_trans/trans_rvv.c.inc 
>> b/target/riscv/insn_trans/trans_rvv.c.inc
>> index e630f8661e1..70c19c49ae4 100644
>> --- a/target/riscv/insn_trans/trans_rvv.c.inc
>> +++ b/target/riscv/insn_trans/trans_rvv.c.inc
>> @@ -379,6 +379,35 @@ static bool vext_check_ld_index(DisasContext *s, 
>> int vd, int vs2,
>>       return ret;
>>   }
>>   +/*
>> + * Check whether a vector register is used to provide source 
>> operands with
>> + * more than one EEW for the vector instruction.
>> + * Returns true if the instruction has valid encoding
>> + * Returns false if encoding violates the mismatched input EEWs 
>> constraint
>> + */
>> +static bool vext_check_input_eew(DisasContext *s, int vs1, uint8_t 
>> eew_vs1,
>> +                                 int vs2, uint8_t eew_vs2, int vm)
>> +{
>> +    bool is_valid = true;
>> +    int8_t emul_vs1 = eew_vs1 - s->sew + s->lmul;
>> +    int8_t emul_vs2 = eew_vs2 - s->sew + s->lmul;
>> +
>> +    /* When vm is 0, vs1 & vs2(EEW!=1) group can't overlap v0 
>> (EEW=1) */
>> +    if ((vs1 != -1 && !require_vm(vm, vs1)) ||
>> +        (vs2 != -1 && !require_vm(vm, vs2))) {
>> +        is_valid = false;
>> +    }
>> +
>> +    /* When eew_vs1 != eew_vs2, check whether vs1 and vs2 are 
>> overlapped */
>> +    if ((vs1 != -1 && vs2 != -1) && (eew_vs1 != eew_vs2) &&
>> +        is_overlapped(vs1, 1 << MAX(emul_vs1, 0),
>> +                      vs2, 1 << MAX(emul_vs2, 0))) {
>> +        is_valid = false;
>> +    }
>> +
>> +    return is_valid;
>> +}
>> +
>
> Code LGTM but the patch won't compile on its own because there's no 
> callers for
> it:
>
>
> In file included from ../target/riscv/translate.c:1182:
> ../target/riscv/insn_trans/trans_rvv.c.inc:388:13: error: 
> ‘vext_check_input_eew’ defined but not used [-Werror=unused-function]
>   388 | static bool vext_check_input_eew(DisasContext *s, int vs1, 
> uint8_t eew_vs1,
>       |             ^~~~~~~~~~~~~~~~~~~~
> cc1: all warnings being treated as errors
> ninja: build stopped: subcommand failed.
>
>
> We want each patch to be "buildable" and with test passing to make our 
> lives easier
> when doing bisects.
>
> You can merge this patch with patch 4 to introduce the new function 
> and add its first
> callers. Thanks,
>
>
> Daniel
Thanks for the suggestion. Will fix this issue at v3.

Max
>
>
>
>>   static bool vext_check_ss(DisasContext *s, int vd, int vs, int vm)
>>   {
>>       return require_vm(vm, vd) &&
>

Re: [PATCH v2 04/12] target/riscv: rvv: Apply vext_check_input_eew to vector register gather instructions

[Max Chou]

On 2025/4/5 5:14 PM, Daniel Henrique Barboza wrote:
>
>
> On 3/29/25 11:44 AM, Max Chou wrote:
>> Handle the overlap of source registers with different EEWs.
>> The vs1 EEW of vrgatherei16.vv is 16.
>>
>> Co-authored-by: Anton Blanchard <antonb@tenstorrent.com>
>> Co-authored-by: Max Chou <max.chou@sifive.com>
>
> Since you're marked as Author you don't need this co-authored-by tag
> in your name too.
>
> Same thing for patches 5 to 11.
Thanks for the suggestion. I'll remove the co-authored-by tag from 
patches 5 to 11 at v3.

Max
>
>> Signed-off-by: Max Chou <max.chou@sifive.com>
>> ---
>
> With the co-authored-by tag removed:
>
> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
>
>>   target/riscv/insn_trans/trans_rvv.c.inc | 3 +++
>>   1 file changed, 3 insertions(+)
>>
>> diff --git a/target/riscv/insn_trans/trans_rvv.c.inc 
>> b/target/riscv/insn_trans/trans_rvv.c.inc
>> index 70c19c49ae4..4a0c9fbeff3 100644
>> --- a/target/riscv/insn_trans/trans_rvv.c.inc
>> +++ b/target/riscv/insn_trans/trans_rvv.c.inc
>> @@ -3478,6 +3478,7 @@ static bool vrgather_vv_check(DisasContext *s, 
>> arg_rmrr *a)
>>   {
>>       return require_rvv(s) &&
>>              vext_check_isa_ill(s) &&
>> +           vext_check_input_eew(s, a->rs1, s->sew, a->rs2, s->sew, 
>> a->vm) &&
>>              require_align(a->rd, s->lmul) &&
>>              require_align(a->rs1, s->lmul) &&
>>              require_align(a->rs2, s->lmul) &&
>> @@ -3490,6 +3491,7 @@ static bool vrgatherei16_vv_check(DisasContext 
>> *s, arg_rmrr *a)
>>       int8_t emul = MO_16 - s->sew + s->lmul;
>>       return require_rvv(s) &&
>>              vext_check_isa_ill(s) &&
>> +           vext_check_input_eew(s, a->rs1, MO_16, a->rs2, s->sew, 
>> a->vm) &&
>>              (emul >= -3 && emul <= 3) &&
>>              require_align(a->rd, s->lmul) &&
>>              require_align(a->rs1, emul) &&
>> @@ -3509,6 +3511,7 @@ static bool vrgather_vx_check(DisasContext *s, 
>> arg_rmrr *a)
>>   {
>>       return require_rvv(s) &&
>>              vext_check_isa_ill(s) &&
>> +           vext_check_input_eew(s, -1, MO_64, a->rs2, s->sew, a->vm) &&
>>              require_align(a->rd, s->lmul) &&
>>              require_align(a->rs2, s->lmul) &&
>>              (a->rd != a->rs2) &&
>

Re: [PATCH v2 05/12] target/riscv: rvv: Apply vext_check_input_eew to OPIVI/OPIVX/OPFVF(vext_check_ss) instructions

[Max Chou]

On 2025/4/5 5:17 PM, Daniel Henrique Barboza wrote:
>
>
> On 3/29/25 11:44 AM, Max Chou wrote:
>> Handle the overlap of source registers with different EEWs.
>>
>> Co-authored-by: Anton Blanchard <antonb@tenstorrent.com>
>> Co-authored-by: Max Chou <max.chou@sifive.com>
>> Signed-off-by: Max Chou <max.chou@sifive.com>
>> ---
>>   target/riscv/insn_trans/trans_rvv.c.inc | 4 +++-
>>   1 file changed, 3 insertions(+), 1 deletion(-)
>>
>> diff --git a/target/riscv/insn_trans/trans_rvv.c.inc 
>> b/target/riscv/insn_trans/trans_rvv.c.inc
>> index 4a0c9fbeff3..3d02a2f9ec8 100644
>> --- a/target/riscv/insn_trans/trans_rvv.c.inc
>> +++ b/target/riscv/insn_trans/trans_rvv.c.inc
>> @@ -412,7 +412,9 @@ static bool vext_check_ss(DisasContext *s, int 
>> vd, int vs, int vm)
>>   {
>>       return require_vm(vm, vd) &&
>>              require_align(vd, s->lmul) &&
>> -           require_align(vs, s->lmul);
>> +           require_align(vs, s->lmul) &&
>> +           vext_check_input_eew(s, vs, s->sew, -1, s->sew, vm);
>> +
>
> Please remove the extra blank line. And with your co-authored-by removed:
>
> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
>
Thanks for the suggestion. Will fix the issues at v3.

Max

>>   }
>>     /*
>