From: "Philippe Mathieu-Daudé" <philmd@linaro.org>
To: qemu-devel@nongnu.org
Cc: "Gustavo Romero" <gustavo.romero@linaro.org>,
"Pierrick Bouvier" <pierrick.bouvier@linaro.org>,
"Paolo Bonzini" <pbonzini@redhat.com>,
"Richard Henderson" <richard.henderson@linaro.org>,
"Philippe Mathieu-Daudé" <philmd@linaro.org>
Subject: [PATCH-for-10.1 24/24] exec: Restrict cpu-mmu-index.h to accel/tcg/
Date: Tue, 1 Apr 2025 10:09:37 +0200 [thread overview]
Message-ID: <20250401080938.32278-25-philmd@linaro.org> (raw)
In-Reply-To: <20250401080938.32278-1-philmd@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
include/{exec => accel/tcg}/cpu-mmu-index.h | 6 +++---
include/exec/cpu_ldst.h | 2 +-
accel/tcg/translator.c | 2 +-
semihosting/uaccess.c | 2 +-
target/arm/gdbstub64.c | 2 +-
target/hppa/mem_helper.c | 2 +-
target/i386/tcg/translate.c | 2 +-
target/loongarch/cpu_helper.c | 2 +-
target/microblaze/helper.c | 2 +-
target/microblaze/mmu.c | 2 +-
target/openrisc/translate.c | 2 +-
target/sparc/cpu.c | 2 +-
target/sparc/mmu_helper.c | 2 +-
target/tricore/helper.c | 2 +-
target/xtensa/mmu_helper.c | 2 +-
15 files changed, 17 insertions(+), 17 deletions(-)
rename include/{exec => accel/tcg}/cpu-mmu-index.h (87%)
diff --git a/include/exec/cpu-mmu-index.h b/include/accel/tcg/cpu-mmu-index.h
similarity index 87%
rename from include/exec/cpu-mmu-index.h
rename to include/accel/tcg/cpu-mmu-index.h
index a87b6f7c4b7..3699c18b4cb 100644
--- a/include/exec/cpu-mmu-index.h
+++ b/include/accel/tcg/cpu-mmu-index.h
@@ -6,8 +6,8 @@
* SPDX-License-Identifier: LGPL-2.1-or-later
*/
-#ifndef EXEC_CPU_MMU_INDEX_H
-#define EXEC_CPU_MMU_INDEX_H
+#ifndef ACCEL_TCG_CPU_MMU_INDEX_H
+#define ACCEL_TCG_CPU_MMU_INDEX_H
#include "hw/core/cpu.h"
#include "accel/tcg/cpu-ops.h"
@@ -37,4 +37,4 @@ static inline int cpu_mmu_index(CPUState *cs, bool ifetch)
return ret;
}
-#endif /* EXEC_CPU_MMU_INDEX_H */
+#endif /* ACCEL_TCG_CPU_MMU_INDEX_H */
diff --git a/include/exec/cpu_ldst.h b/include/exec/cpu_ldst.h
index 313100fcda1..63847f6e618 100644
--- a/include/exec/cpu_ldst.h
+++ b/include/exec/cpu_ldst.h
@@ -68,7 +68,7 @@
#include "exec/cpu-common.h"
#include "exec/cpu-ldst-common.h"
-#include "exec/cpu-mmu-index.h"
+#include "accel/tcg/cpu-mmu-index.h"
#include "exec/abi_ptr.h"
#if defined(CONFIG_USER_ONLY)
diff --git a/accel/tcg/translator.c b/accel/tcg/translator.c
index 36a6a9e0408..c53bbdef99f 100644
--- a/accel/tcg/translator.c
+++ b/accel/tcg/translator.c
@@ -12,7 +12,7 @@
#include "qemu/log.h"
#include "qemu/error-report.h"
#include "exec/cpu-ldst-common.h"
-#include "exec/cpu-mmu-index.h"
+#include "accel/tcg/cpu-mmu-index.h"
#include "exec/target_page.h"
#include "exec/translator.h"
#include "exec/plugin-gen.h"
diff --git a/semihosting/uaccess.c b/semihosting/uaccess.c
index 92b2421dce5..81ffecaaba4 100644
--- a/semihosting/uaccess.c
+++ b/semihosting/uaccess.c
@@ -8,7 +8,7 @@
*/
#include "qemu/osdep.h"
-#include "exec/cpu-mmu-index.h"
+#include "accel/tcg/cpu-mmu-index.h"
#include "exec/exec-all.h"
#include "exec/target_page.h"
#include "exec/tlb-flags.h"
diff --git a/target/arm/gdbstub64.c b/target/arm/gdbstub64.c
index 3bbca4cbb98..64ee9b3b567 100644
--- a/target/arm/gdbstub64.c
+++ b/target/arm/gdbstub64.c
@@ -28,7 +28,7 @@
#include "mte_user_helper.h"
#endif
#ifdef CONFIG_TCG
-#include "exec/cpu-mmu-index.h"
+#include "accel/tcg/cpu-mmu-index.h"
#include "exec/target_page.h"
#endif
diff --git a/target/hppa/mem_helper.c b/target/hppa/mem_helper.c
index df4e35f4de6..554d7bf4d14 100644
--- a/target/hppa/mem_helper.c
+++ b/target/hppa/mem_helper.c
@@ -22,7 +22,7 @@
#include "cpu.h"
#include "exec/exec-all.h"
#include "exec/cputlb.h"
-#include "exec/cpu-mmu-index.h"
+#include "accel/tcg/cpu-mmu-index.h"
#include "exec/page-protection.h"
#include "exec/target_page.h"
#include "exec/helper-proto.h"
diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c
index 7e6d1ef9379..ca49f8d6dcb 100644
--- a/target/i386/tcg/translate.c
+++ b/target/i386/tcg/translate.c
@@ -20,7 +20,7 @@
#include "qemu/host-utils.h"
#include "cpu.h"
-#include "exec/cpu-mmu-index.h"
+#include "accel/tcg/cpu-mmu-index.h"
#include "exec/exec-all.h"
#include "exec/translation-block.h"
#include "tcg/tcg-op.h"
diff --git a/target/loongarch/cpu_helper.c b/target/loongarch/cpu_helper.c
index 4597e29b153..bb343078bf7 100644
--- a/target/loongarch/cpu_helper.c
+++ b/target/loongarch/cpu_helper.c
@@ -8,7 +8,7 @@
#include "qemu/osdep.h"
#include "cpu.h"
-#include "exec/cpu-mmu-index.h"
+#include "accel/tcg/cpu-mmu-index.h"
#include "exec/target_page.h"
#include "internals.h"
#include "cpu-csr.h"
diff --git a/target/microblaze/helper.c b/target/microblaze/helper.c
index 9e6969ccc9a..92031924830 100644
--- a/target/microblaze/helper.c
+++ b/target/microblaze/helper.c
@@ -21,7 +21,7 @@
#include "qemu/osdep.h"
#include "cpu.h"
#include "exec/cputlb.h"
-#include "exec/cpu-mmu-index.h"
+#include "accel/tcg/cpu-mmu-index.h"
#include "exec/page-protection.h"
#include "exec/target_page.h"
#include "qemu/host-utils.h"
diff --git a/target/microblaze/mmu.c b/target/microblaze/mmu.c
index 7f20c4e4c69..95a12e16f8e 100644
--- a/target/microblaze/mmu.c
+++ b/target/microblaze/mmu.c
@@ -22,7 +22,7 @@
#include "qemu/log.h"
#include "cpu.h"
#include "exec/cputlb.h"
-#include "exec/cpu-mmu-index.h"
+#include "accel/tcg/cpu-mmu-index.h"
#include "exec/page-protection.h"
#include "exec/target_page.h"
diff --git a/target/openrisc/translate.c b/target/openrisc/translate.c
index 4a8e203cf88..d4ce60188bd 100644
--- a/target/openrisc/translate.c
+++ b/target/openrisc/translate.c
@@ -20,7 +20,7 @@
#include "qemu/osdep.h"
#include "cpu.h"
-#include "exec/cpu-mmu-index.h"
+#include "accel/tcg/cpu-mmu-index.h"
#include "exec/exec-all.h"
#include "tcg/tcg-op.h"
#include "qemu/log.h"
diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c
index 072d5da5736..af3cec43e78 100644
--- a/target/sparc/cpu.c
+++ b/target/sparc/cpu.c
@@ -22,7 +22,7 @@
#include "cpu.h"
#include "qemu/module.h"
#include "qemu/qemu-print.h"
-#include "exec/cpu-mmu-index.h"
+#include "accel/tcg/cpu-mmu-index.h"
#include "exec/exec-all.h"
#include "exec/translation-block.h"
#include "hw/qdev-properties.h"
diff --git a/target/sparc/mmu_helper.c b/target/sparc/mmu_helper.c
index b3351eebd0a..217580a4d8c 100644
--- a/target/sparc/mmu_helper.c
+++ b/target/sparc/mmu_helper.c
@@ -21,7 +21,7 @@
#include "qemu/log.h"
#include "cpu.h"
#include "exec/cputlb.h"
-#include "exec/cpu-mmu-index.h"
+#include "accel/tcg/cpu-mmu-index.h"
#include "exec/page-protection.h"
#include "exec/target_page.h"
#include "exec/tlb-flags.h"
diff --git a/target/tricore/helper.c b/target/tricore/helper.c
index a5ae5bcb619..e4c53d453dd 100644
--- a/target/tricore/helper.c
+++ b/target/tricore/helper.c
@@ -20,7 +20,7 @@
#include "hw/registerfields.h"
#include "cpu.h"
#include "exec/cputlb.h"
-#include "exec/cpu-mmu-index.h"
+#include "accel/tcg/cpu-mmu-index.h"
#include "exec/page-protection.h"
#include "exec/target_page.h"
#include "fpu/softfloat-helpers.h"
diff --git a/target/xtensa/mmu_helper.c b/target/xtensa/mmu_helper.c
index 45601a4b850..a7dd8100555 100644
--- a/target/xtensa/mmu_helper.c
+++ b/target/xtensa/mmu_helper.c
@@ -33,7 +33,7 @@
#include "exec/helper-proto.h"
#include "qemu/host-utils.h"
#include "exec/cputlb.h"
-#include "exec/cpu-mmu-index.h"
+#include "accel/tcg/cpu-mmu-index.h"
#include "exec/exec-all.h"
#include "exec/page-protection.h"
#include "exec/target_page.h"
--
2.47.1
next prev parent reply other threads:[~2025-04-01 8:14 UTC|newest]
Thread overview: 31+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-04-01 8:09 [PATCH-for-10.1 00/24] cpus: Restrict SoftMMU mmu_index() to TCG Philippe Mathieu-Daudé
2025-04-01 8:09 ` [PATCH-for-10.1 01/24] hw/core/cpu: Update CPUClass::mmu_index docstring Philippe Mathieu-Daudé
2025-04-03 16:41 ` Richard Henderson
2025-04-01 8:09 ` [PATCH-for-10.1 02/24] accel/tcg: Introduce TCGCPUOps::mmu_index() callback Philippe Mathieu-Daudé
2025-04-03 16:42 ` Richard Henderson
2025-04-01 8:09 ` [PATCH-for-10.1 03/24] target/alpha: Restrict SoftMMU mmu_index() to TCG Philippe Mathieu-Daudé
2025-04-01 8:09 ` [PATCH-for-10.1 04/24] target/arm: " Philippe Mathieu-Daudé
2025-04-01 8:09 ` [PATCH-for-10.1 05/24] target/avr: " Philippe Mathieu-Daudé
2025-04-01 8:09 ` [PATCH-for-10.1 06/24] target/hppa: " Philippe Mathieu-Daudé
2025-04-01 8:09 ` [PATCH-for-10.1 07/24] target/i386: Remove unused cpu_(ldub, stb)_kernel macros Philippe Mathieu-Daudé
2025-04-01 8:09 ` [PATCH-for-10.1 08/24] target/i386: Restrict cpu_mmu_index_kernel() to TCG Philippe Mathieu-Daudé
2025-04-01 8:09 ` [PATCH-for-10.1 09/24] target/i386: Restrict SoftMMU mmu_index() " Philippe Mathieu-Daudé
2025-04-01 8:09 ` [PATCH-for-10.1 10/24] target/loongarch: " Philippe Mathieu-Daudé
2025-04-01 8:09 ` [PATCH-for-10.1 11/24] target/m68k: " Philippe Mathieu-Daudé
2025-04-01 8:09 ` [PATCH-for-10.1 12/24] target/microblaze: " Philippe Mathieu-Daudé
2025-04-01 8:09 ` [PATCH-for-10.1 13/24] target/mips: " Philippe Mathieu-Daudé
2025-04-01 8:09 ` [PATCH-for-10.1 14/24] target/openrisc: " Philippe Mathieu-Daudé
2025-04-01 8:09 ` [PATCH-for-10.1 15/24] target/ppc: " Philippe Mathieu-Daudé
2025-04-01 8:09 ` [PATCH-for-10.1 16/24] target/riscv: " Philippe Mathieu-Daudé
2025-04-01 8:09 ` [PATCH-for-10.1 17/24] target/rx: " Philippe Mathieu-Daudé
2025-04-01 8:09 ` [PATCH-for-10.1 18/24] target/s390x: " Philippe Mathieu-Daudé
2025-04-01 8:09 ` [PATCH-for-10.1 19/24] target/sh4: " Philippe Mathieu-Daudé
2025-04-01 8:09 ` [PATCH-for-10.1 20/24] target/sparc: " Philippe Mathieu-Daudé
2025-04-01 8:09 ` [PATCH-for-10.1 21/24] target/tricore: " Philippe Mathieu-Daudé
2025-04-01 8:09 ` [PATCH-for-10.1 22/24] target/xtensa: " Philippe Mathieu-Daudé
2025-04-01 8:09 ` [PATCH-for-10.1 23/24] hw/core/cpu: Remove CPUClass::mmu_index() Philippe Mathieu-Daudé
2025-04-02 3:50 ` Philippe Mathieu-Daudé
2025-04-03 16:42 ` Richard Henderson
2025-04-01 8:09 ` Philippe Mathieu-Daudé [this message]
2025-04-01 17:52 ` [PATCH-for-10.1 00/24] cpus: Restrict SoftMMU mmu_index() to TCG Richard Henderson
2025-04-03 17:21 ` Richard Henderson
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