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From: "Philippe Mathieu-Daudé" <philmd@linaro.org>
To: qemu-devel@nongnu.org
Cc: "Gustavo Romero" <gustavo.romero@linaro.org>,
	"Pierrick Bouvier" <pierrick.bouvier@linaro.org>,
	"Paolo Bonzini" <pbonzini@redhat.com>,
	"Richard Henderson" <richard.henderson@linaro.org>,
	"Philippe Mathieu-Daudé" <philmd@linaro.org>
Subject: [PATCH-for-10.1 02/24] accel/tcg: Introduce TCGCPUOps::mmu_index() callback
Date: Tue,  1 Apr 2025 10:09:15 +0200	[thread overview]
Message-ID: <20250401080938.32278-3-philmd@linaro.org> (raw)
In-Reply-To: <20250401080938.32278-1-philmd@linaro.org>

We'll move CPUClass::mmu_index() to TCGCPUOps::mmu_index().

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
 include/accel/tcg/cpu-ops.h  | 3 +++
 include/exec/cpu-mmu-index.h | 5 ++++-
 2 files changed, 7 insertions(+), 1 deletion(-)

diff --git a/include/accel/tcg/cpu-ops.h b/include/accel/tcg/cpu-ops.h
index f60e5303f21..106a0688da8 100644
--- a/include/accel/tcg/cpu-ops.h
+++ b/include/accel/tcg/cpu-ops.h
@@ -67,6 +67,9 @@ struct TCGCPUOps {
     /** @debug_excp_handler: Callback for handling debug exceptions */
     void (*debug_excp_handler)(CPUState *cpu);
 
+    /** @mmu_index: Callback for choosing softmmu mmu index */
+    int (*mmu_index)(CPUState *cpu, bool ifetch);
+
 #ifdef CONFIG_USER_ONLY
     /**
      * @fake_user_interrupt: Callback for 'fake exception' handling.
diff --git a/include/exec/cpu-mmu-index.h b/include/exec/cpu-mmu-index.h
index cfc13d46bea..651526e9f97 100644
--- a/include/exec/cpu-mmu-index.h
+++ b/include/exec/cpu-mmu-index.h
@@ -10,6 +10,7 @@
 #define EXEC_CPU_MMU_INDEX_H
 
 #include "hw/core/cpu.h"
+#include "accel/tcg/cpu-ops.h"
 #include "tcg/debug-assert.h"
 #ifdef COMPILING_PER_TARGET
 #include "cpu.h"
@@ -31,7 +32,9 @@ static inline int cpu_mmu_index(CPUState *cs, bool ifetch)
 # endif
 #endif
 
-    int ret = cs->cc->mmu_index(cs, ifetch);
+    const TCGCPUOps *tcg_ops = cs->cc->tcg_ops;
+    int ret = tcg_ops->mmu_index ? tcg_ops->mmu_index(cs, ifetch)
+                                 : cs->cc->mmu_index(cs, ifetch);
     tcg_debug_assert(ret >= 0 && ret < NB_MMU_MODES);
     return ret;
 }
-- 
2.47.1



  parent reply	other threads:[~2025-04-01  8:10 UTC|newest]

Thread overview: 31+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-04-01  8:09 [PATCH-for-10.1 00/24] cpus: Restrict SoftMMU mmu_index() to TCG Philippe Mathieu-Daudé
2025-04-01  8:09 ` [PATCH-for-10.1 01/24] hw/core/cpu: Update CPUClass::mmu_index docstring Philippe Mathieu-Daudé
2025-04-03 16:41   ` Richard Henderson
2025-04-01  8:09 ` Philippe Mathieu-Daudé [this message]
2025-04-03 16:42   ` [PATCH-for-10.1 02/24] accel/tcg: Introduce TCGCPUOps::mmu_index() callback Richard Henderson
2025-04-01  8:09 ` [PATCH-for-10.1 03/24] target/alpha: Restrict SoftMMU mmu_index() to TCG Philippe Mathieu-Daudé
2025-04-01  8:09 ` [PATCH-for-10.1 04/24] target/arm: " Philippe Mathieu-Daudé
2025-04-01  8:09 ` [PATCH-for-10.1 05/24] target/avr: " Philippe Mathieu-Daudé
2025-04-01  8:09 ` [PATCH-for-10.1 06/24] target/hppa: " Philippe Mathieu-Daudé
2025-04-01  8:09 ` [PATCH-for-10.1 07/24] target/i386: Remove unused cpu_(ldub, stb)_kernel macros Philippe Mathieu-Daudé
2025-04-01  8:09 ` [PATCH-for-10.1 08/24] target/i386: Restrict cpu_mmu_index_kernel() to TCG Philippe Mathieu-Daudé
2025-04-01  8:09 ` [PATCH-for-10.1 09/24] target/i386: Restrict SoftMMU mmu_index() " Philippe Mathieu-Daudé
2025-04-01  8:09 ` [PATCH-for-10.1 10/24] target/loongarch: " Philippe Mathieu-Daudé
2025-04-01  8:09 ` [PATCH-for-10.1 11/24] target/m68k: " Philippe Mathieu-Daudé
2025-04-01  8:09 ` [PATCH-for-10.1 12/24] target/microblaze: " Philippe Mathieu-Daudé
2025-04-01  8:09 ` [PATCH-for-10.1 13/24] target/mips: " Philippe Mathieu-Daudé
2025-04-01  8:09 ` [PATCH-for-10.1 14/24] target/openrisc: " Philippe Mathieu-Daudé
2025-04-01  8:09 ` [PATCH-for-10.1 15/24] target/ppc: " Philippe Mathieu-Daudé
2025-04-01  8:09 ` [PATCH-for-10.1 16/24] target/riscv: " Philippe Mathieu-Daudé
2025-04-01  8:09 ` [PATCH-for-10.1 17/24] target/rx: " Philippe Mathieu-Daudé
2025-04-01  8:09 ` [PATCH-for-10.1 18/24] target/s390x: " Philippe Mathieu-Daudé
2025-04-01  8:09 ` [PATCH-for-10.1 19/24] target/sh4: " Philippe Mathieu-Daudé
2025-04-01  8:09 ` [PATCH-for-10.1 20/24] target/sparc: " Philippe Mathieu-Daudé
2025-04-01  8:09 ` [PATCH-for-10.1 21/24] target/tricore: " Philippe Mathieu-Daudé
2025-04-01  8:09 ` [PATCH-for-10.1 22/24] target/xtensa: " Philippe Mathieu-Daudé
2025-04-01  8:09 ` [PATCH-for-10.1 23/24] hw/core/cpu: Remove CPUClass::mmu_index() Philippe Mathieu-Daudé
2025-04-02  3:50   ` Philippe Mathieu-Daudé
2025-04-03 16:42     ` Richard Henderson
2025-04-01  8:09 ` [PATCH-for-10.1 24/24] exec: Restrict cpu-mmu-index.h to accel/tcg/ Philippe Mathieu-Daudé
2025-04-01 17:52 ` [PATCH-for-10.1 00/24] cpus: Restrict SoftMMU mmu_index() to TCG Richard Henderson
2025-04-03 17:21 ` Richard Henderson

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