From: "Philippe Mathieu-Daudé" <philmd@linaro.org>
To: qemu-devel@nongnu.org
Cc: "Gustavo Romero" <gustavo.romero@linaro.org>,
"Pierrick Bouvier" <pierrick.bouvier@linaro.org>,
"Paolo Bonzini" <pbonzini@redhat.com>,
"Richard Henderson" <richard.henderson@linaro.org>,
"Philippe Mathieu-Daudé" <philmd@linaro.org>
Subject: [PATCH-for-10.1 08/24] target/i386: Restrict cpu_mmu_index_kernel() to TCG
Date: Tue, 1 Apr 2025 10:09:21 +0200 [thread overview]
Message-ID: <20250401080938.32278-9-philmd@linaro.org> (raw)
In-Reply-To: <20250401080938.32278-1-philmd@linaro.org>
Move cpu_mmu_index_kernel() to seg_helper.c.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
target/i386/cpu.h | 1 -
target/i386/tcg/seg_helper.h | 4 ++++
target/i386/cpu.c | 16 ----------------
target/i386/tcg/seg_helper.c | 16 ++++++++++++++++
4 files changed, 20 insertions(+), 17 deletions(-)
diff --git a/target/i386/cpu.h b/target/i386/cpu.h
index 44ee263d8f1..e23a947a7c7 100644
--- a/target/i386/cpu.h
+++ b/target/i386/cpu.h
@@ -2598,7 +2598,6 @@ static inline bool is_mmu_index_32(int mmu_index)
}
int x86_mmu_index_pl(CPUX86State *env, unsigned pl);
-int cpu_mmu_index_kernel(CPUX86State *env);
#define CC_DST (env->cc_dst)
#define CC_SRC (env->cc_src)
diff --git a/target/i386/tcg/seg_helper.h b/target/i386/tcg/seg_helper.h
index 6b8606cd6d8..ea98e1a98ed 100644
--- a/target/i386/tcg/seg_helper.h
+++ b/target/i386/tcg/seg_helper.h
@@ -20,6 +20,8 @@
#ifndef SEG_HELPER_H
#define SEG_HELPER_H
+#include "cpu.h"
+
//#define DEBUG_PCALL
#ifdef DEBUG_PCALL
@@ -31,6 +33,8 @@
# define LOG_PCALL_STATE(cpu) do { } while (0)
#endif
+int cpu_mmu_index_kernel(CPUX86State *env);
+
/*
* TODO: Convert callers to compute cpu_mmu_index_kernel once
* and use *_mmuidx_ra directly.
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index af46c7a392a..0b74b9a3754 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -8669,22 +8669,6 @@ static int x86_cpu_mmu_index(CPUState *cs, bool ifetch)
return x86_mmu_index_pl(env, env->hflags & HF_CPL_MASK);
}
-static int x86_mmu_index_kernel_pl(CPUX86State *env, unsigned pl)
-{
- int mmu_index_32 = (env->hflags & HF_LMA_MASK) ? 0 : 1;
- int mmu_index_base =
- !(env->hflags & HF_SMAP_MASK) ? MMU_KNOSMAP64_IDX :
- (pl < 3 && (env->eflags & AC_MASK)
- ? MMU_KNOSMAP64_IDX : MMU_KSMAP64_IDX);
-
- return mmu_index_base + mmu_index_32;
-}
-
-int cpu_mmu_index_kernel(CPUX86State *env)
-{
- return x86_mmu_index_kernel_pl(env, env->hflags & HF_CPL_MASK);
-}
-
static void x86_disas_set_info(CPUState *cs, disassemble_info *info)
{
X86CPU *cpu = X86_CPU(cs);
diff --git a/target/i386/tcg/seg_helper.c b/target/i386/tcg/seg_helper.c
index 71962113fb8..f4370202fed 100644
--- a/target/i386/tcg/seg_helper.c
+++ b/target/i386/tcg/seg_helper.c
@@ -128,6 +128,22 @@ int get_pg_mode(CPUX86State *env)
return pg_mode;
}
+static int x86_mmu_index_kernel_pl(CPUX86State *env, unsigned pl)
+{
+ int mmu_index_32 = (env->hflags & HF_LMA_MASK) ? 0 : 1;
+ int mmu_index_base =
+ !(env->hflags & HF_SMAP_MASK) ? MMU_KNOSMAP64_IDX :
+ (pl < 3 && (env->eflags & AC_MASK)
+ ? MMU_KNOSMAP64_IDX : MMU_KSMAP64_IDX);
+
+ return mmu_index_base + mmu_index_32;
+}
+
+int cpu_mmu_index_kernel(CPUX86State *env)
+{
+ return x86_mmu_index_kernel_pl(env, env->hflags & HF_CPL_MASK);
+}
+
/* return non zero if error */
static inline int load_segment_ra(CPUX86State *env, uint32_t *e1_ptr,
uint32_t *e2_ptr, int selector,
--
2.47.1
next prev parent reply other threads:[~2025-04-01 8:12 UTC|newest]
Thread overview: 31+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-04-01 8:09 [PATCH-for-10.1 00/24] cpus: Restrict SoftMMU mmu_index() to TCG Philippe Mathieu-Daudé
2025-04-01 8:09 ` [PATCH-for-10.1 01/24] hw/core/cpu: Update CPUClass::mmu_index docstring Philippe Mathieu-Daudé
2025-04-03 16:41 ` Richard Henderson
2025-04-01 8:09 ` [PATCH-for-10.1 02/24] accel/tcg: Introduce TCGCPUOps::mmu_index() callback Philippe Mathieu-Daudé
2025-04-03 16:42 ` Richard Henderson
2025-04-01 8:09 ` [PATCH-for-10.1 03/24] target/alpha: Restrict SoftMMU mmu_index() to TCG Philippe Mathieu-Daudé
2025-04-01 8:09 ` [PATCH-for-10.1 04/24] target/arm: " Philippe Mathieu-Daudé
2025-04-01 8:09 ` [PATCH-for-10.1 05/24] target/avr: " Philippe Mathieu-Daudé
2025-04-01 8:09 ` [PATCH-for-10.1 06/24] target/hppa: " Philippe Mathieu-Daudé
2025-04-01 8:09 ` [PATCH-for-10.1 07/24] target/i386: Remove unused cpu_(ldub, stb)_kernel macros Philippe Mathieu-Daudé
2025-04-01 8:09 ` Philippe Mathieu-Daudé [this message]
2025-04-01 8:09 ` [PATCH-for-10.1 09/24] target/i386: Restrict SoftMMU mmu_index() to TCG Philippe Mathieu-Daudé
2025-04-01 8:09 ` [PATCH-for-10.1 10/24] target/loongarch: " Philippe Mathieu-Daudé
2025-04-01 8:09 ` [PATCH-for-10.1 11/24] target/m68k: " Philippe Mathieu-Daudé
2025-04-01 8:09 ` [PATCH-for-10.1 12/24] target/microblaze: " Philippe Mathieu-Daudé
2025-04-01 8:09 ` [PATCH-for-10.1 13/24] target/mips: " Philippe Mathieu-Daudé
2025-04-01 8:09 ` [PATCH-for-10.1 14/24] target/openrisc: " Philippe Mathieu-Daudé
2025-04-01 8:09 ` [PATCH-for-10.1 15/24] target/ppc: " Philippe Mathieu-Daudé
2025-04-01 8:09 ` [PATCH-for-10.1 16/24] target/riscv: " Philippe Mathieu-Daudé
2025-04-01 8:09 ` [PATCH-for-10.1 17/24] target/rx: " Philippe Mathieu-Daudé
2025-04-01 8:09 ` [PATCH-for-10.1 18/24] target/s390x: " Philippe Mathieu-Daudé
2025-04-01 8:09 ` [PATCH-for-10.1 19/24] target/sh4: " Philippe Mathieu-Daudé
2025-04-01 8:09 ` [PATCH-for-10.1 20/24] target/sparc: " Philippe Mathieu-Daudé
2025-04-01 8:09 ` [PATCH-for-10.1 21/24] target/tricore: " Philippe Mathieu-Daudé
2025-04-01 8:09 ` [PATCH-for-10.1 22/24] target/xtensa: " Philippe Mathieu-Daudé
2025-04-01 8:09 ` [PATCH-for-10.1 23/24] hw/core/cpu: Remove CPUClass::mmu_index() Philippe Mathieu-Daudé
2025-04-02 3:50 ` Philippe Mathieu-Daudé
2025-04-03 16:42 ` Richard Henderson
2025-04-01 8:09 ` [PATCH-for-10.1 24/24] exec: Restrict cpu-mmu-index.h to accel/tcg/ Philippe Mathieu-Daudé
2025-04-01 17:52 ` [PATCH-for-10.1 00/24] cpus: Restrict SoftMMU mmu_index() to TCG Richard Henderson
2025-04-03 17:21 ` Richard Henderson
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