From: "Philippe Mathieu-Daudé" <philmd@linaro.org>
To: Richard Henderson <richard.henderson@linaro.org>, qemu-devel@nongnu.org
Subject: [PATCH-for-10.1 31/43] tcg: Always define TCG_GUEST_DEFAULT_MO
Date: Wed, 2 Apr 2025 23:03:16 +0200 [thread overview]
Message-ID: <20250402210328.52897-32-philmd@linaro.org> (raw)
In-Reply-To: <20250402210328.52897-1-philmd@linaro.org>
We only require the TCG_GUEST_DEFAULT_MO for MTTCG-enabled
frontends, otherwise we use a default value of TCG_MO_ALL.
In order to simplify, require the definition for all targets,
defining it for hexagon, m68k, rx, sh4 and tricore.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Anton Johansson <anjo@rev.ng>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
---
target/hexagon/cpu-param.h | 3 +++
target/m68k/cpu-param.h | 3 +++
target/rx/cpu-param.h | 3 +++
target/sh4/cpu-param.h | 3 +++
target/tricore/cpu-param.h | 3 +++
accel/tcg/translate-all.c | 4 ----
6 files changed, 15 insertions(+), 4 deletions(-)
diff --git a/target/hexagon/cpu-param.h b/target/hexagon/cpu-param.h
index 635d509e743..7cc63a01d4b 100644
--- a/target/hexagon/cpu-param.h
+++ b/target/hexagon/cpu-param.h
@@ -25,4 +25,7 @@
#define TARGET_INSN_START_EXTRA_WORDS 0
+/* MTTCG not yet supported: require strict ordering */
+#define TCG_GUEST_DEFAULT_MO TCG_MO_ALL
+
#endif
diff --git a/target/m68k/cpu-param.h b/target/m68k/cpu-param.h
index 256a2b5f8b2..10a8d74bfa9 100644
--- a/target/m68k/cpu-param.h
+++ b/target/m68k/cpu-param.h
@@ -19,4 +19,7 @@
#define TARGET_INSN_START_EXTRA_WORDS 1
+/* MTTCG not yet supported: require strict ordering */
+#define TCG_GUEST_DEFAULT_MO TCG_MO_ALL
+
#endif
diff --git a/target/rx/cpu-param.h b/target/rx/cpu-param.h
index 84934f3bcaf..fe39a77ca38 100644
--- a/target/rx/cpu-param.h
+++ b/target/rx/cpu-param.h
@@ -26,4 +26,7 @@
#define TARGET_INSN_START_EXTRA_WORDS 0
+/* MTTCG not yet supported: require strict ordering */
+#define TCG_GUEST_DEFAULT_MO TCG_MO_ALL
+
#endif
diff --git a/target/sh4/cpu-param.h b/target/sh4/cpu-param.h
index f328715ee86..acdf2397495 100644
--- a/target/sh4/cpu-param.h
+++ b/target/sh4/cpu-param.h
@@ -18,4 +18,7 @@
#define TARGET_INSN_START_EXTRA_WORDS 1
+/* MTTCG not yet supported: require strict ordering */
+#define TCG_GUEST_DEFAULT_MO TCG_MO_ALL
+
#endif
diff --git a/target/tricore/cpu-param.h b/target/tricore/cpu-param.h
index eb33a67c419..45fde756b6a 100644
--- a/target/tricore/cpu-param.h
+++ b/target/tricore/cpu-param.h
@@ -14,4 +14,7 @@
#define TARGET_INSN_START_EXTRA_WORDS 0
+/* MTTCG not yet supported: require strict ordering */
+#define TCG_GUEST_DEFAULT_MO TCG_MO_ALL
+
#endif
diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c
index ed41fc5d0cc..cb1cf270888 100644
--- a/accel/tcg/translate-all.c
+++ b/accel/tcg/translate-all.c
@@ -352,11 +352,7 @@ TranslationBlock *tb_gen_code(CPUState *cpu,
tcg_ctx->tlb_dyn_max_bits = CPU_TLB_DYN_MAX_BITS;
#endif
tcg_ctx->insn_start_words = TARGET_INSN_START_WORDS;
-#ifdef TCG_GUEST_DEFAULT_MO
tcg_ctx->guest_mo = TCG_GUEST_DEFAULT_MO;
-#else
- tcg_ctx->guest_mo = TCG_MO_ALL;
-#endif
restart_translate:
trace_translate_block(tb, pc, tb->tc.ptr);
--
2.47.1
next prev parent reply other threads:[~2025-04-02 21:07 UTC|newest]
Thread overview: 48+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-04-02 21:02 [PATCH-for-10.1 00/43] tcg: philmd's queue Philippe Mathieu-Daudé
2025-04-02 21:02 ` [PATCH-for-10.1 01/43] tcg: Declare TARGET_INSN_START_EXTRA_WORDS in 'cpu-param.h' Philippe Mathieu-Daudé
2025-04-03 21:29 ` Philippe Mathieu-Daudé
2025-04-03 21:43 ` Philippe Mathieu-Daudé
2025-04-02 21:02 ` [PATCH-for-10.1 02/43] tcg: Always define TARGET_INSN_START_EXTRA_WORDS Philippe Mathieu-Daudé
2025-04-02 21:02 ` [PATCH-for-10.1 03/43] hw/core/cpu: Update CPUClass::mmu_index docstring Philippe Mathieu-Daudé
2025-04-02 21:02 ` [PATCH-for-10.1 04/43] accel/tcg: Introduce TCGCPUOps::mmu_index() callback Philippe Mathieu-Daudé
2025-04-02 21:02 ` [PATCH-for-10.1 05/43] target/alpha: Restrict SoftMMU mmu_index() to TCG Philippe Mathieu-Daudé
2025-04-02 21:02 ` [PATCH-for-10.1 06/43] target/arm: " Philippe Mathieu-Daudé
2025-04-02 21:02 ` [PATCH-for-10.1 07/43] target/avr: " Philippe Mathieu-Daudé
2025-04-02 21:02 ` [PATCH-for-10.1 08/43] target/hppa: " Philippe Mathieu-Daudé
2025-04-02 21:02 ` [PATCH-for-10.1 09/43] target/i386: Remove unused cpu_(ldub, stb)_kernel macros Philippe Mathieu-Daudé
2025-04-02 21:02 ` [PATCH-for-10.1 10/43] target/i386: Restrict cpu_mmu_index_kernel() to TCG Philippe Mathieu-Daudé
2025-04-02 21:02 ` [PATCH-for-10.1 11/43] target/i386: Restrict SoftMMU mmu_index() " Philippe Mathieu-Daudé
2025-04-02 21:02 ` [PATCH-for-10.1 12/43] target/loongarch: " Philippe Mathieu-Daudé
2025-04-02 21:02 ` [PATCH-for-10.1 13/43] target/m68k: " Philippe Mathieu-Daudé
2025-04-02 21:02 ` [PATCH-for-10.1 14/43] target/microblaze: " Philippe Mathieu-Daudé
2025-04-02 21:03 ` [PATCH-for-10.1 15/43] target/mips: " Philippe Mathieu-Daudé
2025-04-02 21:03 ` [PATCH-for-10.1 16/43] target/openrisc: " Philippe Mathieu-Daudé
2025-04-02 21:03 ` [PATCH-for-10.1 17/43] target/ppc: " Philippe Mathieu-Daudé
2025-04-02 23:08 ` Philippe Mathieu-Daudé
2025-04-02 21:03 ` [PATCH-for-10.1 18/43] target/riscv: " Philippe Mathieu-Daudé
2025-04-02 21:03 ` [PATCH-for-10.1 19/43] target/rx: Fix copy/paste typo (riscv -> rx) Philippe Mathieu-Daudé
2025-04-02 21:03 ` [PATCH-for-10.1 20/43] target/rx: Restrict SoftMMU mmu_index() to TCG Philippe Mathieu-Daudé
2025-04-02 21:03 ` [PATCH-for-10.1 21/43] target/s390x: " Philippe Mathieu-Daudé
2025-04-02 23:11 ` Philippe Mathieu-Daudé
2025-04-02 21:03 ` [PATCH-for-10.1 22/43] target/sh4: " Philippe Mathieu-Daudé
2025-04-02 21:03 ` [PATCH-for-10.1 23/43] target/sparc: " Philippe Mathieu-Daudé
2025-04-02 21:03 ` [PATCH-for-10.1 24/43] target/tricore: " Philippe Mathieu-Daudé
2025-04-02 21:03 ` [PATCH-for-10.1 25/43] target/xtensa: " Philippe Mathieu-Daudé
2025-04-02 21:03 ` [PATCH-for-10.1 26/43] hw/core/cpu: Remove CPUClass::mmu_index() Philippe Mathieu-Daudé
2025-04-02 21:03 ` [PATCH-for-10.1 27/43] exec: Restrict cpu-mmu-index.h to accel/tcg/ Philippe Mathieu-Daudé
2025-04-02 21:03 ` [PATCH-for-10.1 28/43] exec: Restrict 'cpu-ldst-common.h' " Philippe Mathieu-Daudé
2025-04-02 21:03 ` [PATCH-for-10.1 29/43] exec: Restrict 'cpu_ldst.h' " Philippe Mathieu-Daudé
2025-04-02 21:03 ` [PATCH-for-10.1 30/43] exec: Do not include 'accel/tcg/cpu-ldst.h' in 'exec-all.h' Philippe Mathieu-Daudé
2025-04-02 21:03 ` Philippe Mathieu-Daudé [this message]
2025-04-02 21:03 ` [PATCH-for-10.1 32/43] tcg: Simplify tcg_req_mo() macro Philippe Mathieu-Daudé
2025-04-02 21:03 ` [PATCH-for-10.1 33/43] tcg: Define guest_default_memory_order in TCGCPUOps Philippe Mathieu-Daudé
2025-04-02 21:03 ` [PATCH-for-10.1 34/43] tcg: Remove use of TCG_GUEST_DEFAULT_MO in tb_gen_code() Philippe Mathieu-Daudé
2025-04-02 21:03 ` [PATCH-for-10.1 35/43] tcg: Propagate CPUState argument to cpu_req_mo() Philippe Mathieu-Daudé
2025-04-02 21:03 ` [PATCH-for-10.1 36/43] tcg: Have tcg_req_mo() use TCGCPUOps::guest_default_memory_order Philippe Mathieu-Daudé
2025-04-02 21:03 ` [PATCH-for-10.1 37/43] tcg: Remove the TCG_GUEST_DEFAULT_MO definition globally Philippe Mathieu-Daudé
2025-04-02 21:03 ` [PATCH-for-10.1 38/43] tcg: Move cpu_req_mo() macro to target-agnostic 'backend-ldst.h' Philippe Mathieu-Daudé
2025-04-02 21:03 ` [PATCH-for-10.1 39/43] tcg: Move qemu_tcg_mttcg_enabled() to 'system/tcg.h' Philippe Mathieu-Daudé
2025-04-02 21:03 ` [PATCH-for-10.1 40/43] tcg: Convert TCGState::mttcg_enabled to TriState Philippe Mathieu-Daudé
2025-04-02 21:03 ` [PATCH-for-10.1 41/43] tcg: Factor mttcg_init() out Philippe Mathieu-Daudé
2025-04-02 21:03 ` [PATCH-for-10.1 42/43] tcg: Convert TARGET_SUPPORTS_MTTCG to TCGCPUOps::mttcg_supported field Philippe Mathieu-Daudé
2025-04-02 21:03 ` [PATCH-for-10.1 43/43] target/arm: Update comment around cpu_untagged_addr() Philippe Mathieu-Daudé
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