From: "Philippe Mathieu-Daudé" <philmd@linaro.org>
To: Richard Henderson <richard.henderson@linaro.org>, qemu-devel@nongnu.org
Subject: [PATCH-for-10.1 06/43] target/arm: Restrict SoftMMU mmu_index() to TCG
Date: Wed, 2 Apr 2025 23:02:51 +0200 [thread overview]
Message-ID: <20250402210328.52897-7-philmd@linaro.org> (raw)
In-Reply-To: <20250402210328.52897-1-philmd@linaro.org>
Move arm_cpu_mmu_index() within CONFIG_TCG #ifdef'ry
and expose its prototype in "target/arm/internals.h".
Convert CPUClass::mmu_index() to TCGCPUOps::mmu_index().
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
target/arm/internals.h | 1 +
target/arm/cpu.c | 13 +++++++------
target/arm/tcg/cpu-v7m.c | 1 +
3 files changed, 9 insertions(+), 6 deletions(-)
diff --git a/target/arm/internals.h b/target/arm/internals.h
index 895d60218e3..01408e40a34 100644
--- a/target/arm/internals.h
+++ b/target/arm/internals.h
@@ -374,6 +374,7 @@ void arm_cpu_synchronize_from_tb(CPUState *cs, const TranslationBlock *tb);
/* Our implementation of TCGCPUOps::cpu_exec_halt */
bool arm_cpu_exec_halt(CPUState *cs);
+int arm_cpu_mmu_index(CPUState *cs, bool ifetch);
#endif /* CONFIG_TCG */
typedef enum ARMFPRounding {
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index f29661938c4..c9e043bc9b5 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -122,6 +122,12 @@ void arm_restore_state_to_opc(CPUState *cs,
env->exception.syndrome = data[2] << ARM_INSN_START_WORD2_SHIFT;
}
}
+
+int arm_cpu_mmu_index(CPUState *cs, bool ifetch)
+{
+ return arm_env_mmu_index(cpu_env(cs));
+}
+
#endif /* CONFIG_TCG */
#ifndef CONFIG_USER_ONLY
@@ -145,11 +151,6 @@ static bool arm_cpu_has_work(CPUState *cs)
}
#endif /* !CONFIG_USER_ONLY */
-static int arm_cpu_mmu_index(CPUState *cs, bool ifetch)
-{
- return arm_env_mmu_index(cpu_env(cs));
-}
-
void arm_register_pre_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook,
void *opaque)
{
@@ -2675,6 +2676,7 @@ static const TCGCPUOps arm_tcg_ops = {
.synchronize_from_tb = arm_cpu_synchronize_from_tb,
.debug_excp_handler = arm_debug_excp_handler,
.restore_state_to_opc = arm_restore_state_to_opc,
+ .mmu_index = arm_cpu_mmu_index,
#ifdef CONFIG_USER_ONLY
.record_sigsegv = arm_cpu_record_sigsegv,
@@ -2709,7 +2711,6 @@ static void arm_cpu_class_init(ObjectClass *oc, void *data)
&acc->parent_phases);
cc->class_by_name = arm_cpu_class_by_name;
- cc->mmu_index = arm_cpu_mmu_index;
cc->dump_state = arm_cpu_dump_state;
cc->set_pc = arm_cpu_set_pc;
cc->get_pc = arm_cpu_get_pc;
diff --git a/target/arm/tcg/cpu-v7m.c b/target/arm/tcg/cpu-v7m.c
index c4dd3092726..1a913faa50f 100644
--- a/target/arm/tcg/cpu-v7m.c
+++ b/target/arm/tcg/cpu-v7m.c
@@ -237,6 +237,7 @@ static const TCGCPUOps arm_v7m_tcg_ops = {
.synchronize_from_tb = arm_cpu_synchronize_from_tb,
.debug_excp_handler = arm_debug_excp_handler,
.restore_state_to_opc = arm_restore_state_to_opc,
+ .mmu_index = arm_cpu_mmu_index,
#ifdef CONFIG_USER_ONLY
.record_sigsegv = arm_cpu_record_sigsegv,
--
2.47.1
next prev parent reply other threads:[~2025-04-02 21:06 UTC|newest]
Thread overview: 48+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-04-02 21:02 [PATCH-for-10.1 00/43] tcg: philmd's queue Philippe Mathieu-Daudé
2025-04-02 21:02 ` [PATCH-for-10.1 01/43] tcg: Declare TARGET_INSN_START_EXTRA_WORDS in 'cpu-param.h' Philippe Mathieu-Daudé
2025-04-03 21:29 ` Philippe Mathieu-Daudé
2025-04-03 21:43 ` Philippe Mathieu-Daudé
2025-04-02 21:02 ` [PATCH-for-10.1 02/43] tcg: Always define TARGET_INSN_START_EXTRA_WORDS Philippe Mathieu-Daudé
2025-04-02 21:02 ` [PATCH-for-10.1 03/43] hw/core/cpu: Update CPUClass::mmu_index docstring Philippe Mathieu-Daudé
2025-04-02 21:02 ` [PATCH-for-10.1 04/43] accel/tcg: Introduce TCGCPUOps::mmu_index() callback Philippe Mathieu-Daudé
2025-04-02 21:02 ` [PATCH-for-10.1 05/43] target/alpha: Restrict SoftMMU mmu_index() to TCG Philippe Mathieu-Daudé
2025-04-02 21:02 ` Philippe Mathieu-Daudé [this message]
2025-04-02 21:02 ` [PATCH-for-10.1 07/43] target/avr: " Philippe Mathieu-Daudé
2025-04-02 21:02 ` [PATCH-for-10.1 08/43] target/hppa: " Philippe Mathieu-Daudé
2025-04-02 21:02 ` [PATCH-for-10.1 09/43] target/i386: Remove unused cpu_(ldub, stb)_kernel macros Philippe Mathieu-Daudé
2025-04-02 21:02 ` [PATCH-for-10.1 10/43] target/i386: Restrict cpu_mmu_index_kernel() to TCG Philippe Mathieu-Daudé
2025-04-02 21:02 ` [PATCH-for-10.1 11/43] target/i386: Restrict SoftMMU mmu_index() " Philippe Mathieu-Daudé
2025-04-02 21:02 ` [PATCH-for-10.1 12/43] target/loongarch: " Philippe Mathieu-Daudé
2025-04-02 21:02 ` [PATCH-for-10.1 13/43] target/m68k: " Philippe Mathieu-Daudé
2025-04-02 21:02 ` [PATCH-for-10.1 14/43] target/microblaze: " Philippe Mathieu-Daudé
2025-04-02 21:03 ` [PATCH-for-10.1 15/43] target/mips: " Philippe Mathieu-Daudé
2025-04-02 21:03 ` [PATCH-for-10.1 16/43] target/openrisc: " Philippe Mathieu-Daudé
2025-04-02 21:03 ` [PATCH-for-10.1 17/43] target/ppc: " Philippe Mathieu-Daudé
2025-04-02 23:08 ` Philippe Mathieu-Daudé
2025-04-02 21:03 ` [PATCH-for-10.1 18/43] target/riscv: " Philippe Mathieu-Daudé
2025-04-02 21:03 ` [PATCH-for-10.1 19/43] target/rx: Fix copy/paste typo (riscv -> rx) Philippe Mathieu-Daudé
2025-04-02 21:03 ` [PATCH-for-10.1 20/43] target/rx: Restrict SoftMMU mmu_index() to TCG Philippe Mathieu-Daudé
2025-04-02 21:03 ` [PATCH-for-10.1 21/43] target/s390x: " Philippe Mathieu-Daudé
2025-04-02 23:11 ` Philippe Mathieu-Daudé
2025-04-02 21:03 ` [PATCH-for-10.1 22/43] target/sh4: " Philippe Mathieu-Daudé
2025-04-02 21:03 ` [PATCH-for-10.1 23/43] target/sparc: " Philippe Mathieu-Daudé
2025-04-02 21:03 ` [PATCH-for-10.1 24/43] target/tricore: " Philippe Mathieu-Daudé
2025-04-02 21:03 ` [PATCH-for-10.1 25/43] target/xtensa: " Philippe Mathieu-Daudé
2025-04-02 21:03 ` [PATCH-for-10.1 26/43] hw/core/cpu: Remove CPUClass::mmu_index() Philippe Mathieu-Daudé
2025-04-02 21:03 ` [PATCH-for-10.1 27/43] exec: Restrict cpu-mmu-index.h to accel/tcg/ Philippe Mathieu-Daudé
2025-04-02 21:03 ` [PATCH-for-10.1 28/43] exec: Restrict 'cpu-ldst-common.h' " Philippe Mathieu-Daudé
2025-04-02 21:03 ` [PATCH-for-10.1 29/43] exec: Restrict 'cpu_ldst.h' " Philippe Mathieu-Daudé
2025-04-02 21:03 ` [PATCH-for-10.1 30/43] exec: Do not include 'accel/tcg/cpu-ldst.h' in 'exec-all.h' Philippe Mathieu-Daudé
2025-04-02 21:03 ` [PATCH-for-10.1 31/43] tcg: Always define TCG_GUEST_DEFAULT_MO Philippe Mathieu-Daudé
2025-04-02 21:03 ` [PATCH-for-10.1 32/43] tcg: Simplify tcg_req_mo() macro Philippe Mathieu-Daudé
2025-04-02 21:03 ` [PATCH-for-10.1 33/43] tcg: Define guest_default_memory_order in TCGCPUOps Philippe Mathieu-Daudé
2025-04-02 21:03 ` [PATCH-for-10.1 34/43] tcg: Remove use of TCG_GUEST_DEFAULT_MO in tb_gen_code() Philippe Mathieu-Daudé
2025-04-02 21:03 ` [PATCH-for-10.1 35/43] tcg: Propagate CPUState argument to cpu_req_mo() Philippe Mathieu-Daudé
2025-04-02 21:03 ` [PATCH-for-10.1 36/43] tcg: Have tcg_req_mo() use TCGCPUOps::guest_default_memory_order Philippe Mathieu-Daudé
2025-04-02 21:03 ` [PATCH-for-10.1 37/43] tcg: Remove the TCG_GUEST_DEFAULT_MO definition globally Philippe Mathieu-Daudé
2025-04-02 21:03 ` [PATCH-for-10.1 38/43] tcg: Move cpu_req_mo() macro to target-agnostic 'backend-ldst.h' Philippe Mathieu-Daudé
2025-04-02 21:03 ` [PATCH-for-10.1 39/43] tcg: Move qemu_tcg_mttcg_enabled() to 'system/tcg.h' Philippe Mathieu-Daudé
2025-04-02 21:03 ` [PATCH-for-10.1 40/43] tcg: Convert TCGState::mttcg_enabled to TriState Philippe Mathieu-Daudé
2025-04-02 21:03 ` [PATCH-for-10.1 41/43] tcg: Factor mttcg_init() out Philippe Mathieu-Daudé
2025-04-02 21:03 ` [PATCH-for-10.1 42/43] tcg: Convert TARGET_SUPPORTS_MTTCG to TCGCPUOps::mttcg_supported field Philippe Mathieu-Daudé
2025-04-02 21:03 ` [PATCH-for-10.1 43/43] target/arm: Update comment around cpu_untagged_addr() Philippe Mathieu-Daudé
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