* [PATCH-for-10.1 v3 01/19] target/riscv: Do not expose rv128 CPU on user mode emulation
2025-04-03 22:04 [PATCH-for-10.1 v3 00/19] tcg: philmd's queue Philippe Mathieu-Daudé
@ 2025-04-03 22:04 ` Philippe Mathieu-Daudé
2025-04-03 22:04 ` [PATCH-for-10.1 v3 02/19] tcg: Include missing 'cpu.h' in translate-all.c Philippe Mathieu-Daudé
` (17 subsequent siblings)
18 siblings, 0 replies; 23+ messages in thread
From: Philippe Mathieu-Daudé @ 2025-04-03 22:04 UTC (permalink / raw)
To: qemu-devel; +Cc: Richard Henderson, Pierrick Bouvier
As Richard mentioned:
We should allow RV128 in user-mode at all until there's a
kernel abi for it.
Remove the experimental 'x-rv128' CPU on user emulation
(since it is experimental, no deprecation period is required).
Reported-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
target/riscv/cpu.c | 10 ++++------
target/riscv/tcg/tcg-cpu.c | 5 +++--
2 files changed, 7 insertions(+), 8 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 430b02d2a58..ad534cee51f 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -697,7 +697,7 @@ static void rv64_xiangshan_nanhu_cpu_init(Object *obj)
#endif
}
-#ifdef CONFIG_TCG
+#if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY)
static void rv128_base_cpu_init(Object *obj)
{
RISCVCPU *cpu = RISCV_CPU(obj);
@@ -708,11 +708,9 @@ static void rv128_base_cpu_init(Object *obj)
/* Set latest version of privileged specification */
env->priv_ver = PRIV_VERSION_LATEST;
-#ifndef CONFIG_USER_ONLY
set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV57);
-#endif
}
-#endif /* CONFIG_TCG */
+#endif /* CONFIG_TCG && !CONFIG_USER_ONLY */
static void rv64i_bare_cpu_init(Object *obj)
{
@@ -3255,9 +3253,9 @@ static const TypeInfo riscv_cpu_type_infos[] = {
DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_VEYRON_V1, MXL_RV64, rv64_veyron_v1_cpu_init),
DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_XIANGSHAN_NANHU,
MXL_RV64, rv64_xiangshan_nanhu_cpu_init),
-#ifdef CONFIG_TCG
+#if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY)
DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_BASE128, MXL_RV128, rv128_base_cpu_init),
-#endif /* CONFIG_TCG */
+#endif /* CONFIG_TCG && !CONFIG_USER_ONLY */
DEFINE_BARE_CPU(TYPE_RISCV_CPU_RV64I, MXL_RV64, rv64i_bare_cpu_init),
DEFINE_BARE_CPU(TYPE_RISCV_CPU_RV64E, MXL_RV64, rv64e_bare_cpu_init),
DEFINE_PROFILE_CPU(TYPE_RISCV_CPU_RVA22U64, MXL_RV64, rva22u64_profile_cpu_init),
diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
index 710449d17e8..5d0429b4d00 100644
--- a/target/riscv/tcg/tcg-cpu.c
+++ b/target/riscv/tcg/tcg-cpu.c
@@ -1046,7 +1046,6 @@ static bool riscv_cpu_is_generic(Object *cpu_obj)
static bool riscv_tcg_cpu_realize(CPUState *cs, Error **errp)
{
RISCVCPU *cpu = RISCV_CPU(cs);
- RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(cpu);
if (!riscv_cpu_tcg_compatible(cpu)) {
g_autofree char *name = riscv_cpu_get_name(cpu);
@@ -1055,6 +1054,9 @@ static bool riscv_tcg_cpu_realize(CPUState *cs, Error **errp)
return false;
}
+#ifndef CONFIG_USER_ONLY
+ RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(cpu);
+
if (mcc->misa_mxl_max >= MXL_RV128 && qemu_tcg_mttcg_enabled()) {
/* Missing 128-bit aligned atomics */
error_setg(errp,
@@ -1063,7 +1065,6 @@ static bool riscv_tcg_cpu_realize(CPUState *cs, Error **errp)
return false;
}
-#ifndef CONFIG_USER_ONLY
CPURISCVState *env = &cpu->env;
tcg_cflags_set(CPU(cs), CF_PCREL);
--
2.47.1
^ permalink raw reply related [flat|nested] 23+ messages in thread* [PATCH-for-10.1 v3 02/19] tcg: Include missing 'cpu.h' in translate-all.c
2025-04-03 22:04 [PATCH-for-10.1 v3 00/19] tcg: philmd's queue Philippe Mathieu-Daudé
2025-04-03 22:04 ` [PATCH-for-10.1 v3 01/19] target/riscv: Do not expose rv128 CPU on user mode emulation Philippe Mathieu-Daudé
@ 2025-04-03 22:04 ` Philippe Mathieu-Daudé
2025-04-03 22:04 ` [PATCH-for-10.1 v3 03/19] tcg: Declare TARGET_INSN_START_EXTRA_WORDS in 'cpu-param.h' Philippe Mathieu-Daudé
` (16 subsequent siblings)
18 siblings, 0 replies; 23+ messages in thread
From: Philippe Mathieu-Daudé @ 2025-04-03 22:04 UTC (permalink / raw)
To: qemu-devel; +Cc: Richard Henderson, Pierrick Bouvier
tb_check_watchpoint() calls cpu_get_tb_cpu_state(),
which is declared in each "cpu.h" header. It is indirectly
included via "tcg/insn-start-words.h". Since we want to
rework "tcg/insn-start-words.h", removing "cpu.h" in the
next commit, add the missing header now, otherwise we'd
get:
accel/tcg/translate-all.c:598:9: error: call to undeclared function 'cpu_get_tb_cpu_state' [-Wimplicit-function-declaration]
598 | cpu_get_tb_cpu_state(env, &pc, &cs_base, &flags);
| ^
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
accel/tcg/translate-all.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c
index ed41fc5d0cc..c5590eb6955 100644
--- a/accel/tcg/translate-all.c
+++ b/accel/tcg/translate-all.c
@@ -69,6 +69,7 @@
#include "internal-target.h"
#include "tcg/perf.h"
#include "tcg/insn-start-words.h"
+#include "cpu.h"
TBContext tb_ctx;
--
2.47.1
^ permalink raw reply related [flat|nested] 23+ messages in thread* [PATCH-for-10.1 v3 03/19] tcg: Declare TARGET_INSN_START_EXTRA_WORDS in 'cpu-param.h'
2025-04-03 22:04 [PATCH-for-10.1 v3 00/19] tcg: philmd's queue Philippe Mathieu-Daudé
2025-04-03 22:04 ` [PATCH-for-10.1 v3 01/19] target/riscv: Do not expose rv128 CPU on user mode emulation Philippe Mathieu-Daudé
2025-04-03 22:04 ` [PATCH-for-10.1 v3 02/19] tcg: Include missing 'cpu.h' in translate-all.c Philippe Mathieu-Daudé
@ 2025-04-03 22:04 ` Philippe Mathieu-Daudé
2025-04-03 22:04 ` [PATCH-for-10.1 v3 04/19] tcg: Always define TARGET_INSN_START_EXTRA_WORDS Philippe Mathieu-Daudé
` (15 subsequent siblings)
18 siblings, 0 replies; 23+ messages in thread
From: Philippe Mathieu-Daudé @ 2025-04-03 22:04 UTC (permalink / raw)
To: qemu-devel; +Cc: Richard Henderson, Pierrick Bouvier
To avoid including the huge "cpu.h" for a simple definition,
move TARGET_INSN_START_EXTRA_WORDS to "cpu-param.h".
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
include/tcg/insn-start-words.h | 2 +-
target/arm/cpu-param.h | 7 +++++++
target/arm/cpu.h | 6 ------
target/hppa/cpu-param.h | 2 ++
target/hppa/cpu.h | 2 --
target/i386/cpu-param.h | 2 ++
target/i386/cpu.h | 2 --
target/m68k/cpu-param.h | 2 ++
target/m68k/cpu.h | 2 --
target/microblaze/cpu-param.h | 2 ++
target/microblaze/cpu.h | 2 --
target/mips/cpu-param.h | 2 ++
target/mips/cpu.h | 2 --
target/openrisc/cpu-param.h | 2 ++
target/openrisc/cpu.h | 2 --
target/riscv/cpu-param.h | 8 ++++++++
target/riscv/cpu.h | 6 ------
target/s390x/cpu-param.h | 2 ++
target/s390x/cpu.h | 2 --
target/sh4/cpu-param.h | 2 ++
target/sh4/cpu.h | 2 --
target/sparc/cpu-param.h | 2 ++
target/sparc/cpu.h | 1 -
23 files changed, 34 insertions(+), 30 deletions(-)
diff --git a/include/tcg/insn-start-words.h b/include/tcg/insn-start-words.h
index 50c18bd326d..c439c09f2fe 100644
--- a/include/tcg/insn-start-words.h
+++ b/include/tcg/insn-start-words.h
@@ -6,7 +6,7 @@
#ifndef TARGET_INSN_START_WORDS
-#include "cpu.h"
+#include "cpu-param.h"
#ifndef TARGET_INSN_START_EXTRA_WORDS
# define TARGET_INSN_START_WORDS 1
diff --git a/target/arm/cpu-param.h b/target/arm/cpu-param.h
index a7ae42d17dc..2cee4be6938 100644
--- a/target/arm/cpu-param.h
+++ b/target/arm/cpu-param.h
@@ -37,6 +37,13 @@
# define TARGET_PAGE_BITS_LEGACY 10
#endif /* !CONFIG_USER_ONLY */
+/*
+ * ARM-specific extra insn start words:
+ * 1: Conditional execution bits
+ * 2: Partial exception syndrome for data aborts
+ */
+#define TARGET_INSN_START_EXTRA_WORDS 2
+
/* ARM processors have a weak memory model */
#define TCG_GUEST_DEFAULT_MO (0)
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index c1a0faed3ad..3705b34285b 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -98,12 +98,6 @@
#define offsetofhigh32(S, M) (offsetof(S, M) + sizeof(uint32_t))
#endif
-/* ARM-specific extra insn start words:
- * 1: Conditional execution bits
- * 2: Partial exception syndrome for data aborts
- */
-#define TARGET_INSN_START_EXTRA_WORDS 2
-
/* The 2nd extra word holding syndrome info for data aborts does not use
* the upper 6 bits nor the lower 13 bits. We mask and shift it down to
* help the sleb128 encoder do a better job.
diff --git a/target/hppa/cpu-param.h b/target/hppa/cpu-param.h
index 7ed6b5741e7..68ed84e84af 100644
--- a/target/hppa/cpu-param.h
+++ b/target/hppa/cpu-param.h
@@ -19,6 +19,8 @@
#define TARGET_PAGE_BITS 12
+#define TARGET_INSN_START_EXTRA_WORDS 2
+
/* PA-RISC 1.x processors have a strong memory model. */
/*
* ??? While we do not yet implement PA-RISC 2.0, those processors have
diff --git a/target/hppa/cpu.h b/target/hppa/cpu.h
index 2269d1c1064..1c8b610647b 100644
--- a/target/hppa/cpu.h
+++ b/target/hppa/cpu.h
@@ -48,8 +48,6 @@
#define PRIV_KERNEL 0
#define PRIV_USER 3
-#define TARGET_INSN_START_EXTRA_WORDS 2
-
/* No need to flush MMU_ABS*_IDX */
#define HPPA_MMU_FLUSH_MASK \
(1 << MMU_KERNEL_IDX | 1 << MMU_KERNEL_P_IDX | \
diff --git a/target/i386/cpu-param.h b/target/i386/cpu-param.h
index b0e884c5d70..0c8efce8619 100644
--- a/target/i386/cpu-param.h
+++ b/target/i386/cpu-param.h
@@ -22,6 +22,8 @@
#endif
#define TARGET_PAGE_BITS 12
+#define TARGET_INSN_START_EXTRA_WORDS 1
+
/* The x86 has a strong memory model with some store-after-load re-ordering */
#define TCG_GUEST_DEFAULT_MO (TCG_MO_ALL & ~TCG_MO_ST_LD)
diff --git a/target/i386/cpu.h b/target/i386/cpu.h
index 35c16302bdc..16d76df34b2 100644
--- a/target/i386/cpu.h
+++ b/target/i386/cpu.h
@@ -1610,8 +1610,6 @@ typedef struct {
#define MAX_FIXED_COUNTERS 3
#define MAX_GP_COUNTERS (MSR_IA32_PERF_STATUS - MSR_P6_EVNTSEL0)
-#define TARGET_INSN_START_EXTRA_WORDS 1
-
#define NB_OPMASK_REGS 8
/* CPU can't have 0xFFFFFFFF APIC ID, use that value to distinguish
diff --git a/target/m68k/cpu-param.h b/target/m68k/cpu-param.h
index 7afbf6d302d..256a2b5f8b2 100644
--- a/target/m68k/cpu-param.h
+++ b/target/m68k/cpu-param.h
@@ -17,4 +17,6 @@
#define TARGET_PHYS_ADDR_SPACE_BITS 32
#define TARGET_VIRT_ADDR_SPACE_BITS 32
+#define TARGET_INSN_START_EXTRA_WORDS 1
+
#endif
diff --git a/target/m68k/cpu.h b/target/m68k/cpu.h
index 0b70e8c6ab6..39d0b9d6d73 100644
--- a/target/m68k/cpu.h
+++ b/target/m68k/cpu.h
@@ -78,8 +78,6 @@
#define M68K_MAX_TTR 2
#define TTR(type, index) ttr[((type & ACCESS_CODE) == ACCESS_CODE) * 2 + index]
-#define TARGET_INSN_START_EXTRA_WORDS 1
-
typedef CPU_LDoubleU FPReg;
typedef struct CPUArchState {
diff --git a/target/microblaze/cpu-param.h b/target/microblaze/cpu-param.h
index c866ec6c149..5d55e0e3c4a 100644
--- a/target/microblaze/cpu-param.h
+++ b/target/microblaze/cpu-param.h
@@ -27,6 +27,8 @@
/* FIXME: MB uses variable pages down to 1K but linux only uses 4k. */
#define TARGET_PAGE_BITS 12
+#define TARGET_INSN_START_EXTRA_WORDS 1
+
/* MicroBlaze is always in-order. */
#define TCG_GUEST_DEFAULT_MO TCG_MO_ALL
diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h
index 2bfa396c96d..d511f22a559 100644
--- a/target/microblaze/cpu.h
+++ b/target/microblaze/cpu.h
@@ -233,8 +233,6 @@ typedef struct CPUArchState CPUMBState;
#define STREAM_CONTROL (1 << 3)
#define STREAM_NONBLOCK (1 << 4)
-#define TARGET_INSN_START_EXTRA_WORDS 1
-
/* use-non-secure property masks */
#define USE_NON_SECURE_M_AXI_DP_MASK 0x1
#define USE_NON_SECURE_M_AXI_IP_MASK 0x2
diff --git a/target/mips/cpu-param.h b/target/mips/cpu-param.h
index 8fcb1b4f5f2..99ca8d1684c 100644
--- a/target/mips/cpu-param.h
+++ b/target/mips/cpu-param.h
@@ -20,6 +20,8 @@
#endif
#define TARGET_PAGE_BITS 12
+#define TARGET_INSN_START_EXTRA_WORDS 2
+
#define TCG_GUEST_DEFAULT_MO (0)
#endif
diff --git a/target/mips/cpu.h b/target/mips/cpu.h
index 20f31370bcb..d16f9a7220e 100644
--- a/target/mips/cpu.h
+++ b/target/mips/cpu.h
@@ -100,8 +100,6 @@ struct CPUMIPSFPUContext {
#define FP_UNIMPLEMENTED 32
};
-#define TARGET_INSN_START_EXTRA_WORDS 2
-
typedef struct CPUMIPSMVPContext CPUMIPSMVPContext;
struct CPUMIPSMVPContext {
int32_t CP0_MVPControl;
diff --git a/target/openrisc/cpu-param.h b/target/openrisc/cpu-param.h
index 37627f2c394..7ea0ecb55a6 100644
--- a/target/openrisc/cpu-param.h
+++ b/target/openrisc/cpu-param.h
@@ -12,6 +12,8 @@
#define TARGET_PHYS_ADDR_SPACE_BITS 32
#define TARGET_VIRT_ADDR_SPACE_BITS 32
+#define TARGET_INSN_START_EXTRA_WORDS 1
+
#define TCG_GUEST_DEFAULT_MO (0)
#endif
diff --git a/target/openrisc/cpu.h b/target/openrisc/cpu.h
index 19ee85ff5a0..569819bfb0b 100644
--- a/target/openrisc/cpu.h
+++ b/target/openrisc/cpu.h
@@ -40,8 +40,6 @@ struct OpenRISCCPUClass {
ResettablePhases parent_phases;
};
-#define TARGET_INSN_START_EXTRA_WORDS 1
-
enum {
MMU_NOMMU_IDX = 0,
MMU_SUPERVISOR_IDX = 1,
diff --git a/target/riscv/cpu-param.h b/target/riscv/cpu-param.h
index fba30e966a8..ff4ba81965a 100644
--- a/target/riscv/cpu-param.h
+++ b/target/riscv/cpu-param.h
@@ -16,6 +16,14 @@
# define TARGET_VIRT_ADDR_SPACE_BITS 32 /* sv32 */
#endif
#define TARGET_PAGE_BITS 12 /* 4 KiB Pages */
+
+/*
+ * RISC-V-specific extra insn start words:
+ * 1: Original instruction opcode
+ * 2: more information about instruction
+ */
+#define TARGET_INSN_START_EXTRA_WORDS 2
+
/*
* The current MMU Modes are:
* - U mode 0b000
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 867e539b53a..167909c89bc 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -45,12 +45,6 @@ typedef struct CPUArchState CPURISCVState;
# define TYPE_RISCV_CPU_BASE TYPE_RISCV_CPU_BASE64
#endif
-/*
- * RISC-V-specific extra insn start words:
- * 1: Original instruction opcode
- * 2: more information about instruction
- */
-#define TARGET_INSN_START_EXTRA_WORDS 2
/*
* b0: Whether a instruction always raise a store AMO or not.
*/
diff --git a/target/s390x/cpu-param.h b/target/s390x/cpu-param.h
index 5c331ec424c..a8a4377f4ff 100644
--- a/target/s390x/cpu-param.h
+++ b/target/s390x/cpu-param.h
@@ -12,6 +12,8 @@
#define TARGET_PHYS_ADDR_SPACE_BITS 64
#define TARGET_VIRT_ADDR_SPACE_BITS 64
+#define TARGET_INSN_START_EXTRA_WORDS 2
+
/*
* The z/Architecture has a strong memory model with some
* store-after-load re-ordering.
diff --git a/target/s390x/cpu.h b/target/s390x/cpu.h
index 940eda8dd12..90f64ee20cc 100644
--- a/target/s390x/cpu.h
+++ b/target/s390x/cpu.h
@@ -37,8 +37,6 @@
#define TARGET_HAS_PRECISE_SMC
-#define TARGET_INSN_START_EXTRA_WORDS 2
-
#define MMU_USER_IDX 0
#define S390_MAX_CPUS 248
diff --git a/target/sh4/cpu-param.h b/target/sh4/cpu-param.h
index 2b6e11dd0ac..f328715ee86 100644
--- a/target/sh4/cpu-param.h
+++ b/target/sh4/cpu-param.h
@@ -16,4 +16,6 @@
# define TARGET_VIRT_ADDR_SPACE_BITS 32
#endif
+#define TARGET_INSN_START_EXTRA_WORDS 1
+
#endif
diff --git a/target/sh4/cpu.h b/target/sh4/cpu.h
index 7752a0c2e1a..906f99ddf00 100644
--- a/target/sh4/cpu.h
+++ b/target/sh4/cpu.h
@@ -127,8 +127,6 @@ typedef struct tlb_t {
#define UTLB_SIZE 64
#define ITLB_SIZE 4
-#define TARGET_INSN_START_EXTRA_WORDS 1
-
enum sh_features {
SH_FEATURE_SH4A = 1,
SH_FEATURE_BCR3_AND_BCR4 = 2,
diff --git a/target/sparc/cpu-param.h b/target/sparc/cpu-param.h
index 6952ee2b826..62d47b804bb 100644
--- a/target/sparc/cpu-param.h
+++ b/target/sparc/cpu-param.h
@@ -21,6 +21,8 @@
# define TARGET_VIRT_ADDR_SPACE_BITS 32
#endif
+#define TARGET_INSN_START_EXTRA_WORDS 1
+
/*
* From Oracle SPARC Architecture 2015:
*
diff --git a/target/sparc/cpu.h b/target/sparc/cpu.h
index 734dfdb1d3d..83ac818933b 100644
--- a/target/sparc/cpu.h
+++ b/target/sparc/cpu.h
@@ -223,7 +223,6 @@ typedef struct trap_state {
uint32_t tt;
} trap_state;
#endif
-#define TARGET_INSN_START_EXTRA_WORDS 1
typedef struct sparc_def_t {
const char *name;
--
2.47.1
^ permalink raw reply related [flat|nested] 23+ messages in thread* [PATCH-for-10.1 v3 04/19] tcg: Always define TARGET_INSN_START_EXTRA_WORDS
2025-04-03 22:04 [PATCH-for-10.1 v3 00/19] tcg: philmd's queue Philippe Mathieu-Daudé
` (2 preceding siblings ...)
2025-04-03 22:04 ` [PATCH-for-10.1 v3 03/19] tcg: Declare TARGET_INSN_START_EXTRA_WORDS in 'cpu-param.h' Philippe Mathieu-Daudé
@ 2025-04-03 22:04 ` Philippe Mathieu-Daudé
2025-04-03 22:04 ` [PATCH-for-10.1 v3 05/19] exec: Restrict 'cpu-ldst-common.h' to accel/tcg/ Philippe Mathieu-Daudé
` (14 subsequent siblings)
18 siblings, 0 replies; 23+ messages in thread
From: Philippe Mathieu-Daudé @ 2025-04-03 22:04 UTC (permalink / raw)
To: qemu-devel; +Cc: Richard Henderson, Pierrick Bouvier
Do not define TARGET_INSN_START_EXTRA_WORDS under the
hood, have each target explicitly define it.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
include/tcg/insn-start-words.h | 4 ----
include/tcg/tcg-op.h | 2 +-
target/alpha/cpu-param.h | 2 ++
target/avr/cpu-param.h | 2 ++
target/hexagon/cpu-param.h | 2 ++
target/loongarch/cpu-param.h | 2 ++
target/ppc/cpu-param.h | 2 ++
target/rx/cpu-param.h | 2 ++
target/tricore/cpu-param.h | 2 ++
target/xtensa/cpu-param.h | 2 ++
10 files changed, 17 insertions(+), 5 deletions(-)
diff --git a/include/tcg/insn-start-words.h b/include/tcg/insn-start-words.h
index c439c09f2fe..d416d19bcf9 100644
--- a/include/tcg/insn-start-words.h
+++ b/include/tcg/insn-start-words.h
@@ -8,10 +8,6 @@
#include "cpu-param.h"
-#ifndef TARGET_INSN_START_EXTRA_WORDS
-# define TARGET_INSN_START_WORDS 1
-#else
# define TARGET_INSN_START_WORDS (1 + TARGET_INSN_START_EXTRA_WORDS)
-#endif
#endif /* TARGET_INSN_START_WORDS */
diff --git a/include/tcg/tcg-op.h b/include/tcg/tcg-op.h
index bc46b5570c4..cded92a4479 100644
--- a/include/tcg/tcg-op.h
+++ b/include/tcg/tcg-op.h
@@ -23,7 +23,7 @@
# error
#endif
-#ifndef TARGET_INSN_START_EXTRA_WORDS
+#if TARGET_INSN_START_EXTRA_WORDS == 0
static inline void tcg_gen_insn_start(target_ulong pc)
{
TCGOp *op = tcg_emit_op(INDEX_op_insn_start, 64 / TCG_TARGET_REG_BITS);
diff --git a/target/alpha/cpu-param.h b/target/alpha/cpu-param.h
index 63989e71c06..dd44feb1793 100644
--- a/target/alpha/cpu-param.h
+++ b/target/alpha/cpu-param.h
@@ -24,6 +24,8 @@
# define TARGET_VIRT_ADDR_SPACE_BITS (30 + TARGET_PAGE_BITS)
#endif
+#define TARGET_INSN_START_EXTRA_WORDS 0
+
/* Alpha processors have a weak memory model */
#define TCG_GUEST_DEFAULT_MO (0)
diff --git a/target/avr/cpu-param.h b/target/avr/cpu-param.h
index f5248ce9e79..9d37848d97d 100644
--- a/target/avr/cpu-param.h
+++ b/target/avr/cpu-param.h
@@ -25,6 +25,8 @@
#define TARGET_PHYS_ADDR_SPACE_BITS 24
#define TARGET_VIRT_ADDR_SPACE_BITS 24
+#define TARGET_INSN_START_EXTRA_WORDS 0
+
#define TCG_GUEST_DEFAULT_MO 0
#endif
diff --git a/target/hexagon/cpu-param.h b/target/hexagon/cpu-param.h
index 45ee7b46409..635d509e743 100644
--- a/target/hexagon/cpu-param.h
+++ b/target/hexagon/cpu-param.h
@@ -23,4 +23,6 @@
#define TARGET_PHYS_ADDR_SPACE_BITS 36
#define TARGET_VIRT_ADDR_SPACE_BITS 32
+#define TARGET_INSN_START_EXTRA_WORDS 0
+
#endif
diff --git a/target/loongarch/cpu-param.h b/target/loongarch/cpu-param.h
index 52437946e56..dbe414bb35a 100644
--- a/target/loongarch/cpu-param.h
+++ b/target/loongarch/cpu-param.h
@@ -13,6 +13,8 @@
#define TARGET_PAGE_BITS 12
+#define TARGET_INSN_START_EXTRA_WORDS 0
+
#define TCG_GUEST_DEFAULT_MO (0)
#endif
diff --git a/target/ppc/cpu-param.h b/target/ppc/cpu-param.h
index 553ad2f4c6a..d0651d2ac89 100644
--- a/target/ppc/cpu-param.h
+++ b/target/ppc/cpu-param.h
@@ -37,6 +37,8 @@
# define TARGET_PAGE_BITS 12
#endif
+#define TARGET_INSN_START_EXTRA_WORDS 0
+
#define TCG_GUEST_DEFAULT_MO 0
#endif
diff --git a/target/rx/cpu-param.h b/target/rx/cpu-param.h
index ef1970a09e9..84934f3bcaf 100644
--- a/target/rx/cpu-param.h
+++ b/target/rx/cpu-param.h
@@ -24,4 +24,6 @@
#define TARGET_PHYS_ADDR_SPACE_BITS 32
#define TARGET_VIRT_ADDR_SPACE_BITS 32
+#define TARGET_INSN_START_EXTRA_WORDS 0
+
#endif
diff --git a/target/tricore/cpu-param.h b/target/tricore/cpu-param.h
index 790242ef3d2..eb33a67c419 100644
--- a/target/tricore/cpu-param.h
+++ b/target/tricore/cpu-param.h
@@ -12,4 +12,6 @@
#define TARGET_PHYS_ADDR_SPACE_BITS 32
#define TARGET_VIRT_ADDR_SPACE_BITS 32
+#define TARGET_INSN_START_EXTRA_WORDS 0
+
#endif
diff --git a/target/xtensa/cpu-param.h b/target/xtensa/cpu-param.h
index 5e4848ad059..e7cb747aaae 100644
--- a/target/xtensa/cpu-param.h
+++ b/target/xtensa/cpu-param.h
@@ -16,6 +16,8 @@
#define TARGET_VIRT_ADDR_SPACE_BITS 32
#endif
+#define TARGET_INSN_START_EXTRA_WORDS 0
+
/* Xtensa processors have a weak memory model */
#define TCG_GUEST_DEFAULT_MO (0)
--
2.47.1
^ permalink raw reply related [flat|nested] 23+ messages in thread* [PATCH-for-10.1 v3 05/19] exec: Restrict 'cpu-ldst-common.h' to accel/tcg/
2025-04-03 22:04 [PATCH-for-10.1 v3 00/19] tcg: philmd's queue Philippe Mathieu-Daudé
` (3 preceding siblings ...)
2025-04-03 22:04 ` [PATCH-for-10.1 v3 04/19] tcg: Always define TARGET_INSN_START_EXTRA_WORDS Philippe Mathieu-Daudé
@ 2025-04-03 22:04 ` Philippe Mathieu-Daudé
2025-04-03 22:04 ` [PATCH-for-10.1 v3 06/19] exec: Restrict 'cpu_ldst.h' " Philippe Mathieu-Daudé
` (13 subsequent siblings)
18 siblings, 0 replies; 23+ messages in thread
From: Philippe Mathieu-Daudé @ 2025-04-03 22:04 UTC (permalink / raw)
To: qemu-devel; +Cc: Richard Henderson, Pierrick Bouvier
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
include/{exec => accel/tcg}/cpu-ldst-common.h | 6 +++---
include/exec/cpu_ldst.h | 2 +-
accel/tcg/translator.c | 2 +-
3 files changed, 5 insertions(+), 5 deletions(-)
rename include/{exec => accel/tcg}/cpu-ldst-common.h (97%)
diff --git a/include/exec/cpu-ldst-common.h b/include/accel/tcg/cpu-ldst-common.h
similarity index 97%
rename from include/exec/cpu-ldst-common.h
rename to include/accel/tcg/cpu-ldst-common.h
index c46a6ade5db..8bf17c2fab0 100644
--- a/include/exec/cpu-ldst-common.h
+++ b/include/accel/tcg/cpu-ldst-common.h
@@ -4,8 +4,8 @@
* SPDX-License-Identifier: LGPL-2.1-or-later
*/
-#ifndef CPU_LDST_COMMON_H
-#define CPU_LDST_COMMON_H
+#ifndef ACCEL_TCG_CPU_LDST_COMMON_H
+#define ACCEL_TCG_CPU_LDST_COMMON_H
#ifndef CONFIG_TCG
#error Can only include this header with TCG
@@ -119,4 +119,4 @@ uint32_t cpu_ldl_code_mmu(CPUArchState *env, vaddr addr,
uint64_t cpu_ldq_code_mmu(CPUArchState *env, vaddr addr,
MemOpIdx oi, uintptr_t ra);
-#endif /* CPU_LDST_COMMON_H */
+#endif /* ACCEL_TCG_CPU_LDST_COMMON_H */
diff --git a/include/exec/cpu_ldst.h b/include/exec/cpu_ldst.h
index 63847f6e618..74761ba5f30 100644
--- a/include/exec/cpu_ldst.h
+++ b/include/exec/cpu_ldst.h
@@ -67,7 +67,7 @@
#endif
#include "exec/cpu-common.h"
-#include "exec/cpu-ldst-common.h"
+#include "accel/tcg/cpu-ldst-common.h"
#include "accel/tcg/cpu-mmu-index.h"
#include "exec/abi_ptr.h"
diff --git a/accel/tcg/translator.c b/accel/tcg/translator.c
index c53bbdef99f..034f2f359ef 100644
--- a/accel/tcg/translator.c
+++ b/accel/tcg/translator.c
@@ -11,7 +11,7 @@
#include "qemu/bswap.h"
#include "qemu/log.h"
#include "qemu/error-report.h"
-#include "exec/cpu-ldst-common.h"
+#include "accel/tcg/cpu-ldst-common.h"
#include "accel/tcg/cpu-mmu-index.h"
#include "exec/target_page.h"
#include "exec/translator.h"
--
2.47.1
^ permalink raw reply related [flat|nested] 23+ messages in thread* [PATCH-for-10.1 v3 06/19] exec: Restrict 'cpu_ldst.h' to accel/tcg/
2025-04-03 22:04 [PATCH-for-10.1 v3 00/19] tcg: philmd's queue Philippe Mathieu-Daudé
` (4 preceding siblings ...)
2025-04-03 22:04 ` [PATCH-for-10.1 v3 05/19] exec: Restrict 'cpu-ldst-common.h' to accel/tcg/ Philippe Mathieu-Daudé
@ 2025-04-03 22:04 ` Philippe Mathieu-Daudé
2025-04-03 22:04 ` [PATCH-for-10.1 v3 07/19] exec: Do not include 'accel/tcg/cpu-ldst.h' in 'exec-all.h' Philippe Mathieu-Daudé
` (12 subsequent siblings)
18 siblings, 0 replies; 23+ messages in thread
From: Philippe Mathieu-Daudé @ 2025-04-03 22:04 UTC (permalink / raw)
To: qemu-devel; +Cc: Richard Henderson, Pierrick Bouvier
Mechanical change using:
$ sed -i -e 's,exec/cpu_ldst,accel/tcg/cpu-ldst,' \
$(git grep -l exec/cpu_ldst.h)
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
bsd-user/qemu.h | 2 +-
include/{exec/cpu_ldst.h => accel/tcg/cpu-ldst.h} | 6 +++---
include/exec/exec-all.h | 2 +-
linux-user/qemu.h | 2 +-
target/arm/tcg/sve_ldst_internal.h | 2 +-
accel/tcg/cputlb.c | 2 +-
accel/tcg/user-exec.c | 2 +-
target/alpha/mem_helper.c | 2 +-
target/arm/tcg/helper-a64.c | 2 +-
target/arm/tcg/m_helper.c | 2 +-
target/arm/tcg/mte_helper.c | 2 +-
target/arm/tcg/mve_helper.c | 2 +-
target/arm/tcg/op_helper.c | 2 +-
target/arm/tcg/pauth_helper.c | 2 +-
target/arm/tcg/sme_helper.c | 2 +-
target/avr/helper.c | 2 +-
target/hexagon/op_helper.c | 2 +-
target/hexagon/translate.c | 2 +-
target/hppa/op_helper.c | 2 +-
target/i386/tcg/access.c | 2 +-
target/i386/tcg/fpu_helper.c | 2 +-
target/i386/tcg/mem_helper.c | 2 +-
target/i386/tcg/mpx_helper.c | 2 +-
target/i386/tcg/seg_helper.c | 2 +-
target/i386/tcg/system/excp_helper.c | 2 +-
target/i386/tcg/system/misc_helper.c | 2 +-
target/i386/tcg/system/seg_helper.c | 2 +-
target/i386/tcg/system/svm_helper.c | 2 +-
target/i386/tcg/user/seg_helper.c | 2 +-
target/loongarch/cpu.c | 2 +-
target/loongarch/tcg/csr_helper.c | 2 +-
target/loongarch/tcg/fpu_helper.c | 2 +-
target/loongarch/tcg/iocsr_helper.c | 2 +-
target/loongarch/tcg/op_helper.c | 2 +-
target/loongarch/tcg/tlb_helper.c | 2 +-
target/m68k/fpu_helper.c | 2 +-
target/m68k/op_helper.c | 2 +-
target/microblaze/cpu.c | 2 +-
target/microblaze/op_helper.c | 2 +-
target/microblaze/translate.c | 2 +-
target/mips/tcg/ldst_helper.c | 2 +-
target/mips/tcg/msa_helper.c | 2 +-
target/mips/tcg/system/tlb_helper.c | 2 +-
target/ppc/mem_helper.c | 2 +-
target/ppc/mmu_helper.c | 2 +-
target/ppc/tcg-excp_helper.c | 2 +-
target/riscv/op_helper.c | 2 +-
target/riscv/vector_helper.c | 2 +-
target/riscv/zce_helper.c | 2 +-
target/rx/helper.c | 2 +-
target/rx/op_helper.c | 2 +-
target/s390x/tcg/crypto_helper.c | 2 +-
target/s390x/tcg/int_helper.c | 2 +-
target/s390x/tcg/mem_helper.c | 2 +-
target/s390x/tcg/misc_helper.c | 2 +-
target/s390x/tcg/vec_helper.c | 2 +-
target/sh4/op_helper.c | 2 +-
target/sparc/int32_helper.c | 2 +-
target/sparc/ldst_helper.c | 2 +-
target/tricore/op_helper.c | 2 +-
target/tricore/translate.c | 2 +-
61 files changed, 63 insertions(+), 63 deletions(-)
rename include/{exec/cpu_ldst.h => accel/tcg/cpu-ldst.h} (99%)
diff --git a/bsd-user/qemu.h b/bsd-user/qemu.h
index c1c508281a8..244670dd24d 100644
--- a/bsd-user/qemu.h
+++ b/bsd-user/qemu.h
@@ -22,7 +22,7 @@
#include "qemu/int128.h"
#include "cpu.h"
#include "qemu/units.h"
-#include "exec/cpu_ldst.h"
+#include "accel/tcg/cpu-ldst.h"
#include "exec/exec-all.h"
#include "user/abitypes.h"
diff --git a/include/exec/cpu_ldst.h b/include/accel/tcg/cpu-ldst.h
similarity index 99%
rename from include/exec/cpu_ldst.h
rename to include/accel/tcg/cpu-ldst.h
index 74761ba5f30..f97a730703e 100644
--- a/include/exec/cpu_ldst.h
+++ b/include/accel/tcg/cpu-ldst.h
@@ -59,8 +59,8 @@
* The "mmu" suffix carries the full MemOpIdx, with both mmu_idx and the
* MemOp including alignment requirements. The alignment will be enforced.
*/
-#ifndef CPU_LDST_H
-#define CPU_LDST_H
+#ifndef ACCEL_TCG_CPU_LDST_H
+#define ACCEL_TCG_CPU_LDST_H
#ifndef CONFIG_TCG
#error Can only include this header with TCG
@@ -560,4 +560,4 @@ static inline void clear_helper_retaddr(void)
#define clear_helper_retaddr() do { } while (0)
#endif
-#endif /* CPU_LDST_H */
+#endif /* ACCEL_TCG_CPU_LDST_H */
diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h
index f52a680f42b..70608a11b60 100644
--- a/include/exec/exec-all.h
+++ b/include/exec/exec-all.h
@@ -21,7 +21,7 @@
#define EXEC_ALL_H
#if defined(CONFIG_USER_ONLY)
-#include "exec/cpu_ldst.h"
+#include "accel/tcg/cpu-ldst.h"
#endif
#include "exec/mmu-access-type.h"
#include "exec/translation-block.h"
diff --git a/linux-user/qemu.h b/linux-user/qemu.h
index 948de8431a5..0b19fa43e65 100644
--- a/linux-user/qemu.h
+++ b/linux-user/qemu.h
@@ -2,7 +2,7 @@
#define QEMU_H
#include "cpu.h"
-#include "exec/cpu_ldst.h"
+#include "accel/tcg/cpu-ldst.h"
#include "user/abitypes.h"
#include "user/page-protection.h"
diff --git a/target/arm/tcg/sve_ldst_internal.h b/target/arm/tcg/sve_ldst_internal.h
index 4f159ec4adf..f2243daf370 100644
--- a/target/arm/tcg/sve_ldst_internal.h
+++ b/target/arm/tcg/sve_ldst_internal.h
@@ -20,7 +20,7 @@
#ifndef TARGET_ARM_SVE_LDST_INTERNAL_H
#define TARGET_ARM_SVE_LDST_INTERNAL_H
-#include "exec/cpu_ldst.h"
+#include "accel/tcg/cpu-ldst.h"
/*
* Load one element into @vd + @reg_off from @host.
diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c
index 0de46903dd9..2cafd38d2af 100644
--- a/accel/tcg/cputlb.c
+++ b/accel/tcg/cputlb.c
@@ -23,7 +23,7 @@
#include "exec/exec-all.h"
#include "exec/page-protection.h"
#include "system/memory.h"
-#include "exec/cpu_ldst.h"
+#include "accel/tcg/cpu-ldst.h"
#include "exec/cputlb.h"
#include "exec/tb-flush.h"
#include "system/ram_addr.h"
diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c
index 7f57d8f1aff..1b878ead7a7 100644
--- a/accel/tcg/user-exec.c
+++ b/accel/tcg/user-exec.c
@@ -26,7 +26,7 @@
#include "tcg/tcg.h"
#include "qemu/bitops.h"
#include "qemu/rcu.h"
-#include "exec/cpu_ldst.h"
+#include "accel/tcg/cpu-ldst.h"
#include "user/cpu_loop.h"
#include "qemu/main-loop.h"
#include "user/page-protection.h"
diff --git a/target/alpha/mem_helper.c b/target/alpha/mem_helper.c
index 872955f5e74..a4d5adb40c6 100644
--- a/target/alpha/mem_helper.c
+++ b/target/alpha/mem_helper.c
@@ -21,7 +21,7 @@
#include "cpu.h"
#include "exec/helper-proto.h"
#include "exec/exec-all.h"
-#include "exec/cpu_ldst.h"
+#include "accel/tcg/cpu-ldst.h"
static void do_unaligned_access(CPUAlphaState *env, vaddr addr, uintptr_t retaddr)
{
diff --git a/target/arm/tcg/helper-a64.c b/target/arm/tcg/helper-a64.c
index 507dbc1a440..08d8f63ffea 100644
--- a/target/arm/tcg/helper-a64.c
+++ b/target/arm/tcg/helper-a64.c
@@ -30,7 +30,7 @@
#include "qemu/crc32c.h"
#include "exec/cpu-common.h"
#include "exec/exec-all.h"
-#include "exec/cpu_ldst.h"
+#include "accel/tcg/cpu-ldst.h"
#include "exec/target_page.h"
#include "exec/tlb-flags.h"
#include "qemu/int128.h"
diff --git a/target/arm/tcg/m_helper.c b/target/arm/tcg/m_helper.c
index f7354f3c6e0..37dc98dc35c 100644
--- a/target/arm/tcg/m_helper.c
+++ b/target/arm/tcg/m_helper.c
@@ -18,7 +18,7 @@
#include "exec/exec-all.h"
#include "exec/page-protection.h"
#ifdef CONFIG_TCG
-#include "exec/cpu_ldst.h"
+#include "accel/tcg/cpu-ldst.h"
#include "semihosting/common-semi.h"
#endif
#if !defined(CONFIG_USER_ONLY)
diff --git a/target/arm/tcg/mte_helper.c b/target/arm/tcg/mte_helper.c
index 888c6707547..7dc5fb776b3 100644
--- a/target/arm/tcg/mte_helper.c
+++ b/target/arm/tcg/mte_helper.c
@@ -29,7 +29,7 @@
#else
#include "system/ram_addr.h"
#endif
-#include "exec/cpu_ldst.h"
+#include "accel/tcg/cpu-ldst.h"
#include "exec/helper-proto.h"
#include "exec/tlb-flags.h"
#include "accel/tcg/cpu-ops.h"
diff --git a/target/arm/tcg/mve_helper.c b/target/arm/tcg/mve_helper.c
index 274003e2e5b..f9f67d1f88e 100644
--- a/target/arm/tcg/mve_helper.c
+++ b/target/arm/tcg/mve_helper.c
@@ -22,7 +22,7 @@
#include "internals.h"
#include "vec_internal.h"
#include "exec/helper-proto.h"
-#include "exec/cpu_ldst.h"
+#include "accel/tcg/cpu-ldst.h"
#include "exec/exec-all.h"
#include "tcg/tcg.h"
#include "fpu/softfloat.h"
diff --git a/target/arm/tcg/op_helper.c b/target/arm/tcg/op_helper.c
index 71ba406782f..38d49cbb9d8 100644
--- a/target/arm/tcg/op_helper.c
+++ b/target/arm/tcg/op_helper.c
@@ -24,7 +24,7 @@
#include "internals.h"
#include "cpu-features.h"
#include "exec/exec-all.h"
-#include "exec/cpu_ldst.h"
+#include "accel/tcg/cpu-ldst.h"
#include "cpregs.h"
#define SIGNBIT (uint32_t)0x80000000
diff --git a/target/arm/tcg/pauth_helper.c b/target/arm/tcg/pauth_helper.c
index c4b143024f3..59bf27541dc 100644
--- a/target/arm/tcg/pauth_helper.c
+++ b/target/arm/tcg/pauth_helper.c
@@ -22,7 +22,7 @@
#include "internals.h"
#include "cpu-features.h"
#include "exec/exec-all.h"
-#include "exec/cpu_ldst.h"
+#include "accel/tcg/cpu-ldst.h"
#include "exec/helper-proto.h"
#include "tcg/tcg-gvec-desc.h"
#include "qemu/xxhash.h"
diff --git a/target/arm/tcg/sme_helper.c b/target/arm/tcg/sme_helper.c
index dcc48e43db3..96b84c37a2d 100644
--- a/target/arm/tcg/sme_helper.c
+++ b/target/arm/tcg/sme_helper.c
@@ -22,7 +22,7 @@
#include "internals.h"
#include "tcg/tcg-gvec-desc.h"
#include "exec/helper-proto.h"
-#include "exec/cpu_ldst.h"
+#include "accel/tcg/cpu-ldst.h"
#include "exec/exec-all.h"
#include "qemu/int128.h"
#include "fpu/softfloat.h"
diff --git a/target/avr/helper.c b/target/avr/helper.c
index 32cbf179195..afa591470fe 100644
--- a/target/avr/helper.c
+++ b/target/avr/helper.c
@@ -27,7 +27,7 @@
#include "exec/cputlb.h"
#include "exec/page-protection.h"
#include "exec/target_page.h"
-#include "exec/cpu_ldst.h"
+#include "accel/tcg/cpu-ldst.h"
#include "exec/helper-proto.h"
bool avr_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
diff --git a/target/hexagon/op_helper.c b/target/hexagon/op_helper.c
index 6da8db8ea5c..3f3d86db2b2 100644
--- a/target/hexagon/op_helper.c
+++ b/target/hexagon/op_helper.c
@@ -18,7 +18,7 @@
#include "qemu/osdep.h"
#include "qemu/log.h"
#include "exec/exec-all.h"
-#include "exec/cpu_ldst.h"
+#include "accel/tcg/cpu-ldst.h"
#include "exec/helper-proto.h"
#include "fpu/softfloat.h"
#include "cpu.h"
diff --git a/target/hexagon/translate.c b/target/hexagon/translate.c
index fe7858703c8..dd26801e647 100644
--- a/target/hexagon/translate.c
+++ b/target/hexagon/translate.c
@@ -23,7 +23,7 @@
#include "exec/helper-gen.h"
#include "exec/helper-proto.h"
#include "exec/translation-block.h"
-#include "exec/cpu_ldst.h"
+#include "accel/tcg/cpu-ldst.h"
#include "exec/log.h"
#include "internal.h"
#include "attribs.h"
diff --git a/target/hppa/op_helper.c b/target/hppa/op_helper.c
index beb8f88799e..2398ce2c648 100644
--- a/target/hppa/op_helper.c
+++ b/target/hppa/op_helper.c
@@ -22,7 +22,7 @@
#include "cpu.h"
#include "exec/exec-all.h"
#include "exec/helper-proto.h"
-#include "exec/cpu_ldst.h"
+#include "accel/tcg/cpu-ldst.h"
#include "qemu/timer.h"
#include "trace.h"
#ifdef CONFIG_USER_ONLY
diff --git a/target/i386/tcg/access.c b/target/i386/tcg/access.c
index 5a4721dcee1..0fdd587eddf 100644
--- a/target/i386/tcg/access.c
+++ b/target/i386/tcg/access.c
@@ -3,7 +3,7 @@
#include "qemu/osdep.h"
#include "cpu.h"
-#include "exec/cpu_ldst.h"
+#include "accel/tcg/cpu-ldst.h"
#include "exec/exec-all.h"
#include "exec/target_page.h"
#include "access.h"
diff --git a/target/i386/tcg/fpu_helper.c b/target/i386/tcg/fpu_helper.c
index c1184ca2198..1cbadb14533 100644
--- a/target/i386/tcg/fpu_helper.c
+++ b/target/i386/tcg/fpu_helper.c
@@ -22,7 +22,7 @@
#include "cpu.h"
#include "tcg-cpu.h"
#include "exec/cputlb.h"
-#include "exec/cpu_ldst.h"
+#include "accel/tcg/cpu-ldst.h"
#include "exec/helper-proto.h"
#include "fpu/softfloat.h"
#include "fpu/softfloat-macros.h"
diff --git a/target/i386/tcg/mem_helper.c b/target/i386/tcg/mem_helper.c
index 3ef84e90d94..84a08152171 100644
--- a/target/i386/tcg/mem_helper.c
+++ b/target/i386/tcg/mem_helper.c
@@ -21,7 +21,7 @@
#include "cpu.h"
#include "exec/helper-proto.h"
#include "exec/exec-all.h"
-#include "exec/cpu_ldst.h"
+#include "accel/tcg/cpu-ldst.h"
#include "qemu/int128.h"
#include "qemu/atomic128.h"
#include "tcg/tcg.h"
diff --git a/target/i386/tcg/mpx_helper.c b/target/i386/tcg/mpx_helper.c
index b942665adcf..a0f816dfae0 100644
--- a/target/i386/tcg/mpx_helper.c
+++ b/target/i386/tcg/mpx_helper.c
@@ -20,7 +20,7 @@
#include "qemu/osdep.h"
#include "cpu.h"
#include "exec/helper-proto.h"
-#include "exec/cpu_ldst.h"
+#include "accel/tcg/cpu-ldst.h"
#include "exec/exec-all.h"
#include "exec/target_page.h"
#include "helper-tcg.h"
diff --git a/target/i386/tcg/seg_helper.c b/target/i386/tcg/seg_helper.c
index 9dfbc4208cd..3af902e0ec5 100644
--- a/target/i386/tcg/seg_helper.c
+++ b/target/i386/tcg/seg_helper.c
@@ -23,7 +23,7 @@
#include "qemu/log.h"
#include "exec/helper-proto.h"
#include "exec/exec-all.h"
-#include "exec/cpu_ldst.h"
+#include "accel/tcg/cpu-ldst.h"
#include "exec/log.h"
#include "helper-tcg.h"
#include "seg_helper.h"
diff --git a/target/i386/tcg/system/excp_helper.c b/target/i386/tcg/system/excp_helper.c
index a563c9b35ea..93614aa3e54 100644
--- a/target/i386/tcg/system/excp_helper.c
+++ b/target/i386/tcg/system/excp_helper.c
@@ -19,7 +19,7 @@
#include "qemu/osdep.h"
#include "cpu.h"
-#include "exec/cpu_ldst.h"
+#include "accel/tcg/cpu-ldst.h"
#include "exec/cputlb.h"
#include "exec/page-protection.h"
#include "exec/target_page.h"
diff --git a/target/i386/tcg/system/misc_helper.c b/target/i386/tcg/system/misc_helper.c
index 67896c8c875..9c3f5cc99b3 100644
--- a/target/i386/tcg/system/misc_helper.c
+++ b/target/i386/tcg/system/misc_helper.c
@@ -21,7 +21,7 @@
#include "qemu/main-loop.h"
#include "cpu.h"
#include "exec/helper-proto.h"
-#include "exec/cpu_ldst.h"
+#include "accel/tcg/cpu-ldst.h"
#include "system/address-spaces.h"
#include "system/memory.h"
#include "exec/cputlb.h"
diff --git a/target/i386/tcg/system/seg_helper.c b/target/i386/tcg/system/seg_helper.c
index b07cc9f9b12..d4ea890c124 100644
--- a/target/i386/tcg/system/seg_helper.c
+++ b/target/i386/tcg/system/seg_helper.c
@@ -23,7 +23,7 @@
#include "qemu/main-loop.h"
#include "cpu.h"
#include "exec/helper-proto.h"
-#include "exec/cpu_ldst.h"
+#include "accel/tcg/cpu-ldst.h"
#include "tcg/helper-tcg.h"
#include "../seg_helper.h"
diff --git a/target/i386/tcg/system/svm_helper.c b/target/i386/tcg/system/svm_helper.c
index f9982b72d17..b27049b9ed1 100644
--- a/target/i386/tcg/system/svm_helper.c
+++ b/target/i386/tcg/system/svm_helper.c
@@ -22,7 +22,7 @@
#include "cpu.h"
#include "exec/helper-proto.h"
#include "exec/cputlb.h"
-#include "exec/cpu_ldst.h"
+#include "accel/tcg/cpu-ldst.h"
#include "tcg/helper-tcg.h"
/* Secure Virtual Machine helpers */
diff --git a/target/i386/tcg/user/seg_helper.c b/target/i386/tcg/user/seg_helper.c
index c45f2ac2ba6..5692dd51953 100644
--- a/target/i386/tcg/user/seg_helper.c
+++ b/target/i386/tcg/user/seg_helper.c
@@ -22,7 +22,7 @@
#include "cpu.h"
#include "exec/helper-proto.h"
#include "exec/exec-all.h"
-#include "exec/cpu_ldst.h"
+#include "accel/tcg/cpu-ldst.h"
#include "tcg/helper-tcg.h"
#include "tcg/seg_helper.h"
diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c
index cb96b17911a..4cc8e02f70b 100644
--- a/target/loongarch/cpu.c
+++ b/target/loongarch/cpu.c
@@ -29,7 +29,7 @@
#include <linux/kvm.h>
#endif
#ifdef CONFIG_TCG
-#include "exec/cpu_ldst.h"
+#include "accel/tcg/cpu-ldst.h"
#include "tcg/tcg.h"
#endif
diff --git a/target/loongarch/tcg/csr_helper.c b/target/loongarch/tcg/csr_helper.c
index 6a7a65c860b..2942d7feb81 100644
--- a/target/loongarch/tcg/csr_helper.c
+++ b/target/loongarch/tcg/csr_helper.c
@@ -13,7 +13,7 @@
#include "qemu/host-utils.h"
#include "exec/helper-proto.h"
#include "exec/cputlb.h"
-#include "exec/cpu_ldst.h"
+#include "accel/tcg/cpu-ldst.h"
#include "hw/irq.h"
#include "cpu-csr.h"
diff --git a/target/loongarch/tcg/fpu_helper.c b/target/loongarch/tcg/fpu_helper.c
index a83acf64b08..fc3fd0561e3 100644
--- a/target/loongarch/tcg/fpu_helper.c
+++ b/target/loongarch/tcg/fpu_helper.c
@@ -9,7 +9,7 @@
#include "cpu.h"
#include "exec/helper-proto.h"
#include "exec/exec-all.h"
-#include "exec/cpu_ldst.h"
+#include "accel/tcg/cpu-ldst.h"
#include "fpu/softfloat.h"
#include "internals.h"
diff --git a/target/loongarch/tcg/iocsr_helper.c b/target/loongarch/tcg/iocsr_helper.c
index b6916f53d20..e62170de3ce 100644
--- a/target/loongarch/tcg/iocsr_helper.c
+++ b/target/loongarch/tcg/iocsr_helper.c
@@ -10,7 +10,7 @@
#include "qemu/host-utils.h"
#include "exec/helper-proto.h"
#include "exec/exec-all.h"
-#include "exec/cpu_ldst.h"
+#include "accel/tcg/cpu-ldst.h"
#define GET_MEMTXATTRS(cas) \
((MemTxAttrs){.requester_id = env_cpu(cas)->cpu_index})
diff --git a/target/loongarch/tcg/op_helper.c b/target/loongarch/tcg/op_helper.c
index b17208e5b96..94e3b28016a 100644
--- a/target/loongarch/tcg/op_helper.c
+++ b/target/loongarch/tcg/op_helper.c
@@ -11,7 +11,7 @@
#include "qemu/host-utils.h"
#include "exec/helper-proto.h"
#include "exec/exec-all.h"
-#include "exec/cpu_ldst.h"
+#include "accel/tcg/cpu-ldst.h"
#include "internals.h"
#include "qemu/crc32c.h"
#include <zlib.h> /* for crc32 */
diff --git a/target/loongarch/tcg/tlb_helper.c b/target/loongarch/tcg/tlb_helper.c
index 0d6c9844a6f..9a76a2a205f 100644
--- a/target/loongarch/tcg/tlb_helper.c
+++ b/target/loongarch/tcg/tlb_helper.c
@@ -16,7 +16,7 @@
#include "exec/exec-all.h"
#include "exec/page-protection.h"
#include "exec/target_page.h"
-#include "exec/cpu_ldst.h"
+#include "accel/tcg/cpu-ldst.h"
#include "exec/log.h"
#include "cpu-csr.h"
diff --git a/target/m68k/fpu_helper.c b/target/m68k/fpu_helper.c
index eb1cb8c6872..ac4a0d85be5 100644
--- a/target/m68k/fpu_helper.c
+++ b/target/m68k/fpu_helper.c
@@ -22,7 +22,7 @@
#include "cpu.h"
#include "exec/helper-proto.h"
#include "exec/exec-all.h"
-#include "exec/cpu_ldst.h"
+#include "accel/tcg/cpu-ldst.h"
#include "softfloat.h"
/*
diff --git a/target/m68k/op_helper.c b/target/m68k/op_helper.c
index 15bad5dd465..242aecccbbc 100644
--- a/target/m68k/op_helper.c
+++ b/target/m68k/op_helper.c
@@ -21,7 +21,7 @@
#include "cpu.h"
#include "exec/helper-proto.h"
#include "exec/exec-all.h"
-#include "exec/cpu_ldst.h"
+#include "accel/tcg/cpu-ldst.h"
#include "semihosting/semihost.h"
#if !defined(CONFIG_USER_ONLY)
diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c
index 88baeb6807a..d10ae0702ad 100644
--- a/target/microblaze/cpu.c
+++ b/target/microblaze/cpu.c
@@ -28,7 +28,7 @@
#include "qemu/module.h"
#include "hw/qdev-properties.h"
#include "exec/exec-all.h"
-#include "exec/cpu_ldst.h"
+#include "accel/tcg/cpu-ldst.h"
#include "exec/gdbstub.h"
#include "exec/translation-block.h"
#include "fpu/softfloat-helpers.h"
diff --git a/target/microblaze/op_helper.c b/target/microblaze/op_helper.c
index f6378030b7a..4624ce5b672 100644
--- a/target/microblaze/op_helper.c
+++ b/target/microblaze/op_helper.c
@@ -24,7 +24,7 @@
#include "exec/helper-proto.h"
#include "qemu/host-utils.h"
#include "exec/exec-all.h"
-#include "exec/cpu_ldst.h"
+#include "accel/tcg/cpu-ldst.h"
#include "fpu/softfloat.h"
void helper_put(uint32_t id, uint32_t ctrl, uint32_t data)
diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c
index 4bb867c9695..7dcad6cf0d7 100644
--- a/target/microblaze/translate.c
+++ b/target/microblaze/translate.c
@@ -21,7 +21,7 @@
#include "qemu/osdep.h"
#include "cpu.h"
#include "exec/exec-all.h"
-#include "exec/cpu_ldst.h"
+#include "accel/tcg/cpu-ldst.h"
#include "tcg/tcg-op.h"
#include "exec/helper-proto.h"
#include "exec/helper-gen.h"
diff --git a/target/mips/tcg/ldst_helper.c b/target/mips/tcg/ldst_helper.c
index f92a923d7ad..2fb879fcbcc 100644
--- a/target/mips/tcg/ldst_helper.c
+++ b/target/mips/tcg/ldst_helper.c
@@ -24,7 +24,7 @@
#include "cpu.h"
#include "exec/helper-proto.h"
#include "exec/exec-all.h"
-#include "exec/cpu_ldst.h"
+#include "accel/tcg/cpu-ldst.h"
#include "exec/memop.h"
#include "internal.h"
diff --git a/target/mips/tcg/msa_helper.c b/target/mips/tcg/msa_helper.c
index 969dd34b3e6..14de4a71ff6 100644
--- a/target/mips/tcg/msa_helper.c
+++ b/target/mips/tcg/msa_helper.c
@@ -22,7 +22,7 @@
#include "internal.h"
#include "tcg/tcg.h"
#include "exec/exec-all.h"
-#include "exec/cpu_ldst.h"
+#include "accel/tcg/cpu-ldst.h"
#include "exec/helper-proto.h"
#include "exec/memop.h"
#include "exec/target_page.h"
diff --git a/target/mips/tcg/system/tlb_helper.c b/target/mips/tcg/system/tlb_helper.c
index d239fa93536..e477ef812ae 100644
--- a/target/mips/tcg/system/tlb_helper.c
+++ b/target/mips/tcg/system/tlb_helper.c
@@ -25,7 +25,7 @@
#include "exec/exec-all.h"
#include "exec/page-protection.h"
#include "exec/target_page.h"
-#include "exec/cpu_ldst.h"
+#include "accel/tcg/cpu-ldst.h"
#include "exec/log.h"
#include "exec/helper-proto.h"
diff --git a/target/ppc/mem_helper.c b/target/ppc/mem_helper.c
index 0967624afee..d7e8d678f4b 100644
--- a/target/ppc/mem_helper.c
+++ b/target/ppc/mem_helper.c
@@ -24,7 +24,7 @@
#include "qemu/host-utils.h"
#include "exec/helper-proto.h"
#include "helper_regs.h"
-#include "exec/cpu_ldst.h"
+#include "accel/tcg/cpu-ldst.h"
#include "internal.h"
#include "qemu/atomic128.h"
diff --git a/target/ppc/mmu_helper.c b/target/ppc/mmu_helper.c
index c90ceb7d60d..2138666122b 100644
--- a/target/ppc/mmu_helper.c
+++ b/target/ppc/mmu_helper.c
@@ -37,7 +37,7 @@
#include "mmu-radix64.h"
#include "mmu-booke.h"
#include "exec/helper-proto.h"
-#include "exec/cpu_ldst.h"
+#include "accel/tcg/cpu-ldst.h"
/* #define FLUSH_ALL_TLBS */
diff --git a/target/ppc/tcg-excp_helper.c b/target/ppc/tcg-excp_helper.c
index c422648cfdd..2b15e5f2f07 100644
--- a/target/ppc/tcg-excp_helper.c
+++ b/target/ppc/tcg-excp_helper.c
@@ -20,7 +20,7 @@
#include "qemu/main-loop.h"
#include "qemu/log.h"
#include "target/ppc/cpu.h"
-#include "exec/cpu_ldst.h"
+#include "accel/tcg/cpu-ldst.h"
#include "exec/exec-all.h"
#include "exec/helper-proto.h"
#include "system/runstate.h"
diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c
index f3d26b6b957..5b0db2c45ab 100644
--- a/target/riscv/op_helper.c
+++ b/target/riscv/op_helper.c
@@ -23,7 +23,7 @@
#include "internals.h"
#include "exec/exec-all.h"
#include "exec/cputlb.h"
-#include "exec/cpu_ldst.h"
+#include "accel/tcg/cpu-ldst.h"
#include "exec/helper-proto.h"
#include "exec/tlb-flags.h"
#include "trace.h"
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index 7de6cbae5cc..b8ae7044578 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -22,7 +22,7 @@
#include "cpu.h"
#include "exec/memop.h"
#include "exec/exec-all.h"
-#include "exec/cpu_ldst.h"
+#include "accel/tcg/cpu-ldst.h"
#include "exec/page-protection.h"
#include "exec/helper-proto.h"
#include "exec/tlb-flags.h"
diff --git a/target/riscv/zce_helper.c b/target/riscv/zce_helper.c
index b433bda16dc..50d65f386c7 100644
--- a/target/riscv/zce_helper.c
+++ b/target/riscv/zce_helper.c
@@ -20,7 +20,7 @@
#include "cpu.h"
#include "exec/exec-all.h"
#include "exec/helper-proto.h"
-#include "exec/cpu_ldst.h"
+#include "accel/tcg/cpu-ldst.h"
target_ulong HELPER(cm_jalt)(CPURISCVState *env, uint32_t index)
{
diff --git a/target/rx/helper.c b/target/rx/helper.c
index e8aabf40ffb..0640ab322b5 100644
--- a/target/rx/helper.c
+++ b/target/rx/helper.c
@@ -20,7 +20,7 @@
#include "qemu/bitops.h"
#include "cpu.h"
#include "exec/log.h"
-#include "exec/cpu_ldst.h"
+#include "accel/tcg/cpu-ldst.h"
#include "hw/irq.h"
void rx_cpu_unpack_psw(CPURXState *env, uint32_t psw, int rte)
diff --git a/target/rx/op_helper.c b/target/rx/op_helper.c
index b3ed822dd11..a2f1f3824d9 100644
--- a/target/rx/op_helper.c
+++ b/target/rx/op_helper.c
@@ -21,7 +21,7 @@
#include "cpu.h"
#include "exec/exec-all.h"
#include "exec/helper-proto.h"
-#include "exec/cpu_ldst.h"
+#include "accel/tcg/cpu-ldst.h"
#include "fpu/softfloat.h"
#include "tcg/debug-assert.h"
diff --git a/target/s390x/tcg/crypto_helper.c b/target/s390x/tcg/crypto_helper.c
index 93aabd236f4..642c1b18c4c 100644
--- a/target/s390x/tcg/crypto_helper.c
+++ b/target/s390x/tcg/crypto_helper.c
@@ -18,7 +18,7 @@
#include "tcg_s390x.h"
#include "exec/helper-proto.h"
#include "exec/exec-all.h"
-#include "exec/cpu_ldst.h"
+#include "accel/tcg/cpu-ldst.h"
static uint64_t R(uint64_t x, int c)
{
diff --git a/target/s390x/tcg/int_helper.c b/target/s390x/tcg/int_helper.c
index 2af970f2c8b..253c0364157 100644
--- a/target/s390x/tcg/int_helper.c
+++ b/target/s390x/tcg/int_helper.c
@@ -25,7 +25,7 @@
#include "exec/exec-all.h"
#include "qemu/host-utils.h"
#include "exec/helper-proto.h"
-#include "exec/cpu_ldst.h"
+#include "accel/tcg/cpu-ldst.h"
/* #define DEBUG_HELPER */
#ifdef DEBUG_HELPER
diff --git a/target/s390x/tcg/mem_helper.c b/target/s390x/tcg/mem_helper.c
index d5eece4384b..0cdfd380ce4 100644
--- a/target/s390x/tcg/mem_helper.c
+++ b/target/s390x/tcg/mem_helper.c
@@ -28,7 +28,7 @@
#include "exec/exec-all.h"
#include "exec/cputlb.h"
#include "exec/page-protection.h"
-#include "exec/cpu_ldst.h"
+#include "accel/tcg/cpu-ldst.h"
#include "exec/target_page.h"
#include "exec/tlb-flags.h"
#include "accel/tcg/cpu-ops.h"
diff --git a/target/s390x/tcg/misc_helper.c b/target/s390x/tcg/misc_helper.c
index e02f4438508..d5088493ead 100644
--- a/target/s390x/tcg/misc_helper.c
+++ b/target/s390x/tcg/misc_helper.c
@@ -28,7 +28,7 @@
#include "qemu/timer.h"
#include "exec/exec-all.h"
#include "exec/cputlb.h"
-#include "exec/cpu_ldst.h"
+#include "accel/tcg/cpu-ldst.h"
#include "exec/target_page.h"
#include "qapi/error.h"
#include "tcg_s390x.h"
diff --git a/target/s390x/tcg/vec_helper.c b/target/s390x/tcg/vec_helper.c
index dafc4c3582c..781ccc565bd 100644
--- a/target/s390x/tcg/vec_helper.c
+++ b/target/s390x/tcg/vec_helper.c
@@ -16,7 +16,7 @@
#include "tcg/tcg.h"
#include "tcg/tcg-gvec-desc.h"
#include "exec/helper-proto.h"
-#include "exec/cpu_ldst.h"
+#include "accel/tcg/cpu-ldst.h"
#include "exec/exec-all.h"
void HELPER(gvec_vbperm)(void *v1, const void *v2, const void *v3,
diff --git a/target/sh4/op_helper.c b/target/sh4/op_helper.c
index 99394b714c9..e7fcad3c1b7 100644
--- a/target/sh4/op_helper.c
+++ b/target/sh4/op_helper.c
@@ -20,7 +20,7 @@
#include "cpu.h"
#include "exec/helper-proto.h"
#include "exec/exec-all.h"
-#include "exec/cpu_ldst.h"
+#include "accel/tcg/cpu-ldst.h"
#include "fpu/softfloat.h"
#ifndef CONFIG_USER_ONLY
diff --git a/target/sparc/int32_helper.c b/target/sparc/int32_helper.c
index f0266061023..39db4ffa70a 100644
--- a/target/sparc/int32_helper.c
+++ b/target/sparc/int32_helper.c
@@ -21,7 +21,7 @@
#include "qemu/main-loop.h"
#include "cpu.h"
#include "trace.h"
-#include "exec/cpu_ldst.h"
+#include "accel/tcg/cpu-ldst.h"
#include "exec/log.h"
#include "system/runstate.h"
diff --git a/target/sparc/ldst_helper.c b/target/sparc/ldst_helper.c
index 10cc6f7835d..ca5a4d38ac2 100644
--- a/target/sparc/ldst_helper.c
+++ b/target/sparc/ldst_helper.c
@@ -27,7 +27,7 @@
#include "exec/cputlb.h"
#include "exec/page-protection.h"
#include "exec/target_page.h"
-#include "exec/cpu_ldst.h"
+#include "accel/tcg/cpu-ldst.h"
#include "system/memory.h"
#ifdef CONFIG_USER_ONLY
#include "user/page-protection.h"
diff --git a/target/tricore/op_helper.c b/target/tricore/op_helper.c
index a0d5a0da1df..ae559b69220 100644
--- a/target/tricore/op_helper.c
+++ b/target/tricore/op_helper.c
@@ -19,7 +19,7 @@
#include "qemu/host-utils.h"
#include "exec/helper-proto.h"
#include "exec/exec-all.h"
-#include "exec/cpu_ldst.h"
+#include "accel/tcg/cpu-ldst.h"
#include <zlib.h> /* for crc32 */
diff --git a/target/tricore/translate.c b/target/tricore/translate.c
index 5c7ed395caa..7cd26d8eaba 100644
--- a/target/tricore/translate.c
+++ b/target/tricore/translate.c
@@ -22,7 +22,7 @@
#include "cpu.h"
#include "exec/exec-all.h"
#include "tcg/tcg-op.h"
-#include "exec/cpu_ldst.h"
+#include "accel/tcg/cpu-ldst.h"
#include "qemu/qemu-print.h"
#include "exec/helper-proto.h"
--
2.47.1
^ permalink raw reply related [flat|nested] 23+ messages in thread* [PATCH-for-10.1 v3 07/19] exec: Do not include 'accel/tcg/cpu-ldst.h' in 'exec-all.h'
2025-04-03 22:04 [PATCH-for-10.1 v3 00/19] tcg: philmd's queue Philippe Mathieu-Daudé
` (5 preceding siblings ...)
2025-04-03 22:04 ` [PATCH-for-10.1 v3 06/19] exec: Restrict 'cpu_ldst.h' " Philippe Mathieu-Daudé
@ 2025-04-03 22:04 ` Philippe Mathieu-Daudé
2025-04-03 22:04 ` [PATCH-for-10.1 v3 08/19] tcg: Always define TCG_GUEST_DEFAULT_MO Philippe Mathieu-Daudé
` (11 subsequent siblings)
18 siblings, 0 replies; 23+ messages in thread
From: Philippe Mathieu-Daudé @ 2025-04-03 22:04 UTC (permalink / raw)
To: qemu-devel; +Cc: Richard Henderson, Pierrick Bouvier
Only 2 files requiring "accel/tcg/cpu-ldst.h" API do not
include it:
- accel/tcg/cpu-exec.c
- target/arm/tcg/sve_helper.c
Include it there and remove it from "exec/exec-all.h".
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
include/exec/exec-all.h | 3 ---
accel/tcg/cpu-exec.c | 1 +
target/arm/tcg/sve_helper.c | 1 +
3 files changed, 2 insertions(+), 3 deletions(-)
diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h
index 70608a11b60..944b579d91c 100644
--- a/include/exec/exec-all.h
+++ b/include/exec/exec-all.h
@@ -20,9 +20,6 @@
#ifndef EXEC_ALL_H
#define EXEC_ALL_H
-#if defined(CONFIG_USER_ONLY)
-#include "accel/tcg/cpu-ldst.h"
-#endif
#include "exec/mmu-access-type.h"
#include "exec/translation-block.h"
diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c
index 5ced3879ac4..b00f046b29f 100644
--- a/accel/tcg/cpu-exec.c
+++ b/accel/tcg/cpu-exec.c
@@ -22,6 +22,7 @@
#include "qapi/error.h"
#include "qapi/type-helpers.h"
#include "hw/core/cpu.h"
+#include "accel/tcg/cpu-ldst.h"
#include "accel/tcg/cpu-ops.h"
#include "trace.h"
#include "disas/disas.h"
diff --git a/target/arm/tcg/sve_helper.c b/target/arm/tcg/sve_helper.c
index 9b0d40c9e18..87b6b4b3e64 100644
--- a/target/arm/tcg/sve_helper.c
+++ b/target/arm/tcg/sve_helper.c
@@ -30,6 +30,7 @@
#include "tcg/tcg.h"
#include "vec_internal.h"
#include "sve_ldst_internal.h"
+#include "accel/tcg/cpu-ldst.h"
#include "accel/tcg/cpu-ops.h"
#ifdef CONFIG_USER_ONLY
#include "user/page-protection.h"
--
2.47.1
^ permalink raw reply related [flat|nested] 23+ messages in thread* [PATCH-for-10.1 v3 08/19] tcg: Always define TCG_GUEST_DEFAULT_MO
2025-04-03 22:04 [PATCH-for-10.1 v3 00/19] tcg: philmd's queue Philippe Mathieu-Daudé
` (6 preceding siblings ...)
2025-04-03 22:04 ` [PATCH-for-10.1 v3 07/19] exec: Do not include 'accel/tcg/cpu-ldst.h' in 'exec-all.h' Philippe Mathieu-Daudé
@ 2025-04-03 22:04 ` Philippe Mathieu-Daudé
2025-04-03 22:04 ` [PATCH-for-10.1 v3 09/19] tcg: Simplify tcg_req_mo() macro Philippe Mathieu-Daudé
` (10 subsequent siblings)
18 siblings, 0 replies; 23+ messages in thread
From: Philippe Mathieu-Daudé @ 2025-04-03 22:04 UTC (permalink / raw)
To: qemu-devel; +Cc: Richard Henderson, Pierrick Bouvier
We only require the TCG_GUEST_DEFAULT_MO for MTTCG-enabled
frontends, otherwise we use a default value of TCG_MO_ALL.
In order to simplify, require the definition for all targets,
defining it for hexagon, m68k, rx, sh4 and tricore.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Anton Johansson <anjo@rev.ng>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
---
target/hexagon/cpu-param.h | 3 +++
target/m68k/cpu-param.h | 3 +++
target/rx/cpu-param.h | 3 +++
target/sh4/cpu-param.h | 3 +++
target/tricore/cpu-param.h | 3 +++
accel/tcg/translate-all.c | 4 ----
6 files changed, 15 insertions(+), 4 deletions(-)
diff --git a/target/hexagon/cpu-param.h b/target/hexagon/cpu-param.h
index 635d509e743..7cc63a01d4b 100644
--- a/target/hexagon/cpu-param.h
+++ b/target/hexagon/cpu-param.h
@@ -25,4 +25,7 @@
#define TARGET_INSN_START_EXTRA_WORDS 0
+/* MTTCG not yet supported: require strict ordering */
+#define TCG_GUEST_DEFAULT_MO TCG_MO_ALL
+
#endif
diff --git a/target/m68k/cpu-param.h b/target/m68k/cpu-param.h
index 256a2b5f8b2..10a8d74bfa9 100644
--- a/target/m68k/cpu-param.h
+++ b/target/m68k/cpu-param.h
@@ -19,4 +19,7 @@
#define TARGET_INSN_START_EXTRA_WORDS 1
+/* MTTCG not yet supported: require strict ordering */
+#define TCG_GUEST_DEFAULT_MO TCG_MO_ALL
+
#endif
diff --git a/target/rx/cpu-param.h b/target/rx/cpu-param.h
index 84934f3bcaf..fe39a77ca38 100644
--- a/target/rx/cpu-param.h
+++ b/target/rx/cpu-param.h
@@ -26,4 +26,7 @@
#define TARGET_INSN_START_EXTRA_WORDS 0
+/* MTTCG not yet supported: require strict ordering */
+#define TCG_GUEST_DEFAULT_MO TCG_MO_ALL
+
#endif
diff --git a/target/sh4/cpu-param.h b/target/sh4/cpu-param.h
index f328715ee86..acdf2397495 100644
--- a/target/sh4/cpu-param.h
+++ b/target/sh4/cpu-param.h
@@ -18,4 +18,7 @@
#define TARGET_INSN_START_EXTRA_WORDS 1
+/* MTTCG not yet supported: require strict ordering */
+#define TCG_GUEST_DEFAULT_MO TCG_MO_ALL
+
#endif
diff --git a/target/tricore/cpu-param.h b/target/tricore/cpu-param.h
index eb33a67c419..45fde756b6a 100644
--- a/target/tricore/cpu-param.h
+++ b/target/tricore/cpu-param.h
@@ -14,4 +14,7 @@
#define TARGET_INSN_START_EXTRA_WORDS 0
+/* MTTCG not yet supported: require strict ordering */
+#define TCG_GUEST_DEFAULT_MO TCG_MO_ALL
+
#endif
diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c
index c5590eb6955..7467255f6e4 100644
--- a/accel/tcg/translate-all.c
+++ b/accel/tcg/translate-all.c
@@ -353,11 +353,7 @@ TranslationBlock *tb_gen_code(CPUState *cpu,
tcg_ctx->tlb_dyn_max_bits = CPU_TLB_DYN_MAX_BITS;
#endif
tcg_ctx->insn_start_words = TARGET_INSN_START_WORDS;
-#ifdef TCG_GUEST_DEFAULT_MO
tcg_ctx->guest_mo = TCG_GUEST_DEFAULT_MO;
-#else
- tcg_ctx->guest_mo = TCG_MO_ALL;
-#endif
restart_translate:
trace_translate_block(tb, pc, tb->tc.ptr);
--
2.47.1
^ permalink raw reply related [flat|nested] 23+ messages in thread* [PATCH-for-10.1 v3 09/19] tcg: Simplify tcg_req_mo() macro
2025-04-03 22:04 [PATCH-for-10.1 v3 00/19] tcg: philmd's queue Philippe Mathieu-Daudé
` (7 preceding siblings ...)
2025-04-03 22:04 ` [PATCH-for-10.1 v3 08/19] tcg: Always define TCG_GUEST_DEFAULT_MO Philippe Mathieu-Daudé
@ 2025-04-03 22:04 ` Philippe Mathieu-Daudé
2025-04-03 22:04 ` [PATCH-for-10.1 v3 10/19] tcg: Define guest_default_memory_order in TCGCPUOps Philippe Mathieu-Daudé
` (9 subsequent siblings)
18 siblings, 0 replies; 23+ messages in thread
From: Philippe Mathieu-Daudé @ 2025-04-03 22:04 UTC (permalink / raw)
To: qemu-devel; +Cc: Richard Henderson, Pierrick Bouvier
Now that TCG_GUEST_DEFAULT_MO is always defined,
simplify the tcg_req_mo() macro.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Anton Johansson <anjo@rev.ng>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
---
accel/tcg/internal-target.h | 9 +--------
accel/tcg/tcg-all.c | 3 ---
2 files changed, 1 insertion(+), 11 deletions(-)
diff --git a/accel/tcg/internal-target.h b/accel/tcg/internal-target.h
index 05abaeb8e0e..1a46a7c87dc 100644
--- a/accel/tcg/internal-target.h
+++ b/accel/tcg/internal-target.h
@@ -52,17 +52,10 @@ G_NORETURN void cpu_io_recompile(CPUState *cpu, uintptr_t retaddr);
* memory ordering vs the host memory ordering. A non-zero
* result indicates that some barrier is required.
*
- * If TCG_GUEST_DEFAULT_MO is not defined, assume that the
- * guest requires strict ordering.
- *
* This is a macro so that it's constant even without optimization.
*/
-#ifdef TCG_GUEST_DEFAULT_MO
-# define tcg_req_mo(type) \
+#define tcg_req_mo(type) \
((type) & TCG_GUEST_DEFAULT_MO & ~TCG_TARGET_DEFAULT_MO)
-#else
-# define tcg_req_mo(type) ((type) & ~TCG_TARGET_DEFAULT_MO)
-#endif
/**
* cpu_req_mo:
diff --git a/accel/tcg/tcg-all.c b/accel/tcg/tcg-all.c
index 7a5b810b88c..a5a1fd6a11e 100644
--- a/accel/tcg/tcg-all.c
+++ b/accel/tcg/tcg-all.c
@@ -77,9 +77,6 @@ static bool default_mttcg_enabled(void)
return false;
}
#ifdef TARGET_SUPPORTS_MTTCG
-# ifndef TCG_GUEST_DEFAULT_MO
-# error "TARGET_SUPPORTS_MTTCG without TCG_GUEST_DEFAULT_MO"
-# endif
return true;
#else
return false;
--
2.47.1
^ permalink raw reply related [flat|nested] 23+ messages in thread* [PATCH-for-10.1 v3 10/19] tcg: Define guest_default_memory_order in TCGCPUOps
2025-04-03 22:04 [PATCH-for-10.1 v3 00/19] tcg: philmd's queue Philippe Mathieu-Daudé
` (8 preceding siblings ...)
2025-04-03 22:04 ` [PATCH-for-10.1 v3 09/19] tcg: Simplify tcg_req_mo() macro Philippe Mathieu-Daudé
@ 2025-04-03 22:04 ` Philippe Mathieu-Daudé
2025-04-03 22:04 ` [PATCH-for-10.1 v3 11/19] tcg: Remove use of TCG_GUEST_DEFAULT_MO in tb_gen_code() Philippe Mathieu-Daudé
` (8 subsequent siblings)
18 siblings, 0 replies; 23+ messages in thread
From: Philippe Mathieu-Daudé @ 2025-04-03 22:04 UTC (permalink / raw)
To: qemu-devel; +Cc: Richard Henderson, Pierrick Bouvier
Add the TCGCPUOps::guest_default_memory_order field and have
each target initialize it.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Anton Johansson <anjo@rev.ng>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
---
include/accel/tcg/cpu-ops.h | 8 ++++++++
target/alpha/cpu.c | 2 ++
target/arm/cpu.c | 2 ++
target/arm/tcg/cpu-v7m.c | 2 ++
target/avr/cpu.c | 1 +
target/hexagon/cpu.c | 1 +
target/hppa/cpu.c | 2 ++
target/i386/tcg/tcg-cpu.c | 1 +
target/loongarch/cpu.c | 2 ++
target/m68k/cpu.c | 2 ++
target/microblaze/cpu.c | 2 ++
target/mips/cpu.c | 2 ++
target/openrisc/cpu.c | 2 ++
target/ppc/cpu_init.c | 1 +
target/riscv/tcg/tcg-cpu.c | 2 ++
target/rx/cpu.c | 2 ++
target/s390x/cpu.c | 2 ++
target/sh4/cpu.c | 2 ++
target/sparc/cpu.c | 2 ++
target/tricore/cpu.c | 1 +
target/xtensa/cpu.c | 2 ++
21 files changed, 43 insertions(+)
diff --git a/include/accel/tcg/cpu-ops.h b/include/accel/tcg/cpu-ops.h
index 106a0688da8..a4932fc5d7c 100644
--- a/include/accel/tcg/cpu-ops.h
+++ b/include/accel/tcg/cpu-ops.h
@@ -16,8 +16,16 @@
#include "exec/memop.h"
#include "exec/mmu-access-type.h"
#include "exec/vaddr.h"
+#include "tcg/tcg-mo.h"
struct TCGCPUOps {
+
+ /**
+ * @guest_default_memory_order: default barrier that is required
+ * for the guest memory ordering.
+ */
+ TCGBar guest_default_memory_order;
+
/**
* @initialize: Initialize TCG state
*
diff --git a/target/alpha/cpu.c b/target/alpha/cpu.c
index 99d839a2792..6f931117a25 100644
--- a/target/alpha/cpu.c
+++ b/target/alpha/cpu.c
@@ -235,6 +235,8 @@ static const struct SysemuCPUOps alpha_sysemu_ops = {
#include "accel/tcg/cpu-ops.h"
static const TCGCPUOps alpha_tcg_ops = {
+ .guest_default_memory_order = TCG_GUEST_DEFAULT_MO,
+
.initialize = alpha_translate_init,
.translate_code = alpha_translate_code,
.synchronize_from_tb = alpha_cpu_synchronize_from_tb,
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index c9e043bc9b5..3f20e258fd0 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -2671,6 +2671,8 @@ static const struct SysemuCPUOps arm_sysemu_ops = {
#ifdef CONFIG_TCG
static const TCGCPUOps arm_tcg_ops = {
+ .guest_default_memory_order = TCG_GUEST_DEFAULT_MO,
+
.initialize = arm_translate_init,
.translate_code = arm_translate_code,
.synchronize_from_tb = arm_cpu_synchronize_from_tb,
diff --git a/target/arm/tcg/cpu-v7m.c b/target/arm/tcg/cpu-v7m.c
index 1a913faa50f..4553fe9de07 100644
--- a/target/arm/tcg/cpu-v7m.c
+++ b/target/arm/tcg/cpu-v7m.c
@@ -232,6 +232,8 @@ static void cortex_m55_initfn(Object *obj)
}
static const TCGCPUOps arm_v7m_tcg_ops = {
+ .guest_default_memory_order = TCG_GUEST_DEFAULT_MO,
+
.initialize = arm_translate_init,
.translate_code = arm_translate_code,
.synchronize_from_tb = arm_cpu_synchronize_from_tb,
diff --git a/target/avr/cpu.c b/target/avr/cpu.c
index feb73e722b3..67918684faf 100644
--- a/target/avr/cpu.c
+++ b/target/avr/cpu.c
@@ -224,6 +224,7 @@ static const struct SysemuCPUOps avr_sysemu_ops = {
#include "accel/tcg/cpu-ops.h"
static const TCGCPUOps avr_tcg_ops = {
+ .guest_default_memory_order = TCG_GUEST_DEFAULT_MO,
.initialize = avr_cpu_tcg_init,
.translate_code = avr_cpu_translate_code,
.synchronize_from_tb = avr_cpu_synchronize_from_tb,
diff --git a/target/hexagon/cpu.c b/target/hexagon/cpu.c
index ad1f303fbcf..b12e0dccd09 100644
--- a/target/hexagon/cpu.c
+++ b/target/hexagon/cpu.c
@@ -325,6 +325,7 @@ static void hexagon_cpu_init(Object *obj)
#include "accel/tcg/cpu-ops.h"
static const TCGCPUOps hexagon_tcg_ops = {
+ .guest_default_memory_order = TCG_GUEST_DEFAULT_MO,
.initialize = hexagon_translate_init,
.translate_code = hexagon_translate_code,
.synchronize_from_tb = hexagon_cpu_synchronize_from_tb,
diff --git a/target/hppa/cpu.c b/target/hppa/cpu.c
index 51bff0c5d62..ac4560febea 100644
--- a/target/hppa/cpu.c
+++ b/target/hppa/cpu.c
@@ -253,6 +253,8 @@ static const struct SysemuCPUOps hppa_sysemu_ops = {
#include "accel/tcg/cpu-ops.h"
static const TCGCPUOps hppa_tcg_ops = {
+ .guest_default_memory_order = TCG_GUEST_DEFAULT_MO,
+
.initialize = hppa_translate_init,
.translate_code = hppa_translate_code,
.synchronize_from_tb = hppa_cpu_synchronize_from_tb,
diff --git a/target/i386/tcg/tcg-cpu.c b/target/i386/tcg/tcg-cpu.c
index 35b17f2b183..3e1b315340c 100644
--- a/target/i386/tcg/tcg-cpu.c
+++ b/target/i386/tcg/tcg-cpu.c
@@ -125,6 +125,7 @@ static bool x86_debug_check_breakpoint(CPUState *cs)
#include "accel/tcg/cpu-ops.h"
static const TCGCPUOps x86_tcg_ops = {
+ .guest_default_memory_order = TCG_GUEST_DEFAULT_MO,
.initialize = tcg_x86_init,
.translate_code = x86_translate_code,
.synchronize_from_tb = x86_cpu_synchronize_from_tb,
diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c
index 4cc8e02f70b..ee74509a664 100644
--- a/target/loongarch/cpu.c
+++ b/target/loongarch/cpu.c
@@ -864,6 +864,8 @@ static void loongarch_cpu_dump_state(CPUState *cs, FILE *f, int flags)
#include "accel/tcg/cpu-ops.h"
static const TCGCPUOps loongarch_tcg_ops = {
+ .guest_default_memory_order = TCG_GUEST_DEFAULT_MO,
+
.initialize = loongarch_translate_init,
.translate_code = loongarch_translate_code,
.synchronize_from_tb = loongarch_cpu_synchronize_from_tb,
diff --git a/target/m68k/cpu.c b/target/m68k/cpu.c
index 4409d8941ce..bfde9b85948 100644
--- a/target/m68k/cpu.c
+++ b/target/m68k/cpu.c
@@ -589,6 +589,8 @@ static const struct SysemuCPUOps m68k_sysemu_ops = {
#include "accel/tcg/cpu-ops.h"
static const TCGCPUOps m68k_tcg_ops = {
+ .guest_default_memory_order = TCG_GUEST_DEFAULT_MO,
+
.initialize = m68k_tcg_init,
.translate_code = m68k_translate_code,
.restore_state_to_opc = m68k_restore_state_to_opc,
diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c
index d10ae0702ad..e46863574c6 100644
--- a/target/microblaze/cpu.c
+++ b/target/microblaze/cpu.c
@@ -427,6 +427,8 @@ static const struct SysemuCPUOps mb_sysemu_ops = {
#include "accel/tcg/cpu-ops.h"
static const TCGCPUOps mb_tcg_ops = {
+ .guest_default_memory_order = TCG_GUEST_DEFAULT_MO,
+
.initialize = mb_tcg_init,
.translate_code = mb_translate_code,
.synchronize_from_tb = mb_cpu_synchronize_from_tb,
diff --git a/target/mips/cpu.c b/target/mips/cpu.c
index 269d3d69bd5..860ec398229 100644
--- a/target/mips/cpu.c
+++ b/target/mips/cpu.c
@@ -550,6 +550,8 @@ static const Property mips_cpu_properties[] = {
#ifdef CONFIG_TCG
#include "accel/tcg/cpu-ops.h"
static const TCGCPUOps mips_tcg_ops = {
+ .guest_default_memory_order = TCG_GUEST_DEFAULT_MO,
+
.initialize = mips_tcg_init,
.translate_code = mips_translate_code,
.synchronize_from_tb = mips_cpu_synchronize_from_tb,
diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c
index dc55594a7de..e62c698a407 100644
--- a/target/openrisc/cpu.c
+++ b/target/openrisc/cpu.c
@@ -243,6 +243,8 @@ static const struct SysemuCPUOps openrisc_sysemu_ops = {
#include "accel/tcg/cpu-ops.h"
static const TCGCPUOps openrisc_tcg_ops = {
+ .guest_default_memory_order = TCG_GUEST_DEFAULT_MO,
+
.initialize = openrisc_translate_init,
.translate_code = openrisc_translate_code,
.synchronize_from_tb = openrisc_cpu_synchronize_from_tb,
diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c
index 740d8b92c0b..57565c9a2f2 100644
--- a/target/ppc/cpu_init.c
+++ b/target/ppc/cpu_init.c
@@ -7478,6 +7478,7 @@ static const struct SysemuCPUOps ppc_sysemu_ops = {
#include "accel/tcg/cpu-ops.h"
static const TCGCPUOps ppc_tcg_ops = {
+ .guest_default_memory_order = TCG_GUEST_DEFAULT_MO,
.initialize = ppc_translate_init,
.translate_code = ppc_translate_code,
.restore_state_to_opc = ppc_restore_state_to_opc,
diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
index 5d0429b4d00..ded2d68ad78 100644
--- a/target/riscv/tcg/tcg-cpu.c
+++ b/target/riscv/tcg/tcg-cpu.c
@@ -140,6 +140,8 @@ static void riscv_restore_state_to_opc(CPUState *cs,
}
static const TCGCPUOps riscv_tcg_ops = {
+ .guest_default_memory_order = TCG_GUEST_DEFAULT_MO,
+
.initialize = riscv_translate_init,
.translate_code = riscv_translate_code,
.synchronize_from_tb = riscv_cpu_synchronize_from_tb,
diff --git a/target/rx/cpu.c b/target/rx/cpu.c
index e14d9cbef93..d7eac551fd4 100644
--- a/target/rx/cpu.c
+++ b/target/rx/cpu.c
@@ -204,6 +204,8 @@ static const struct SysemuCPUOps rx_sysemu_ops = {
#include "accel/tcg/cpu-ops.h"
static const TCGCPUOps rx_tcg_ops = {
+ .guest_default_memory_order = TCG_GUEST_DEFAULT_MO,
+
.initialize = rx_translate_init,
.translate_code = rx_translate_code,
.synchronize_from_tb = rx_cpu_synchronize_from_tb,
diff --git a/target/s390x/cpu.c b/target/s390x/cpu.c
index d15b1943e0e..f232d82fa34 100644
--- a/target/s390x/cpu.c
+++ b/target/s390x/cpu.c
@@ -345,6 +345,8 @@ void cpu_get_tb_cpu_state(CPUS390XState *env, vaddr *pc,
}
static const TCGCPUOps s390_tcg_ops = {
+ .guest_default_memory_order = TCG_GUEST_DEFAULT_MO,
+
.initialize = s390x_translate_init,
.translate_code = s390x_translate_code,
.restore_state_to_opc = s390x_restore_state_to_opc,
diff --git a/target/sh4/cpu.c b/target/sh4/cpu.c
index df093988cb1..29f4be7ba9c 100644
--- a/target/sh4/cpu.c
+++ b/target/sh4/cpu.c
@@ -262,6 +262,8 @@ static const struct SysemuCPUOps sh4_sysemu_ops = {
#include "accel/tcg/cpu-ops.h"
static const TCGCPUOps superh_tcg_ops = {
+ .guest_default_memory_order = TCG_GUEST_DEFAULT_MO,
+
.initialize = sh4_translate_init,
.translate_code = sh4_translate_code,
.synchronize_from_tb = superh_cpu_synchronize_from_tb,
diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c
index af3cec43e78..ef04efcb183 100644
--- a/target/sparc/cpu.c
+++ b/target/sparc/cpu.c
@@ -1001,6 +1001,8 @@ static const struct SysemuCPUOps sparc_sysemu_ops = {
#include "accel/tcg/cpu-ops.h"
static const TCGCPUOps sparc_tcg_ops = {
+ .guest_default_memory_order = TCG_GUEST_DEFAULT_MO,
+
.initialize = sparc_tcg_init,
.translate_code = sparc_translate_code,
.synchronize_from_tb = sparc_cpu_synchronize_from_tb,
diff --git a/target/tricore/cpu.c b/target/tricore/cpu.c
index 833a93d37af..3bf399335ac 100644
--- a/target/tricore/cpu.c
+++ b/target/tricore/cpu.c
@@ -172,6 +172,7 @@ static const struct SysemuCPUOps tricore_sysemu_ops = {
#include "accel/tcg/cpu-ops.h"
static const TCGCPUOps tricore_tcg_ops = {
+ .guest_default_memory_order = TCG_GUEST_DEFAULT_MO,
.initialize = tricore_tcg_init,
.translate_code = tricore_translate_code,
.synchronize_from_tb = tricore_cpu_synchronize_from_tb,
diff --git a/target/xtensa/cpu.c b/target/xtensa/cpu.c
index 51f9ee9e89a..23471064957 100644
--- a/target/xtensa/cpu.c
+++ b/target/xtensa/cpu.c
@@ -232,6 +232,8 @@ static const struct SysemuCPUOps xtensa_sysemu_ops = {
#include "accel/tcg/cpu-ops.h"
static const TCGCPUOps xtensa_tcg_ops = {
+ .guest_default_memory_order = TCG_GUEST_DEFAULT_MO,
+
.initialize = xtensa_translate_init,
.translate_code = xtensa_translate_code,
.debug_excp_handler = xtensa_breakpoint_handler,
--
2.47.1
^ permalink raw reply related [flat|nested] 23+ messages in thread* [PATCH-for-10.1 v3 11/19] tcg: Remove use of TCG_GUEST_DEFAULT_MO in tb_gen_code()
2025-04-03 22:04 [PATCH-for-10.1 v3 00/19] tcg: philmd's queue Philippe Mathieu-Daudé
` (9 preceding siblings ...)
2025-04-03 22:04 ` [PATCH-for-10.1 v3 10/19] tcg: Define guest_default_memory_order in TCGCPUOps Philippe Mathieu-Daudé
@ 2025-04-03 22:04 ` Philippe Mathieu-Daudé
2025-04-03 22:04 ` [PATCH-for-10.1 v3 12/19] tcg: Propagate CPUState argument to cpu_req_mo() Philippe Mathieu-Daudé
` (7 subsequent siblings)
18 siblings, 0 replies; 23+ messages in thread
From: Philippe Mathieu-Daudé @ 2025-04-03 22:04 UTC (permalink / raw)
To: qemu-devel; +Cc: Richard Henderson, Pierrick Bouvier
Use TCGCPUOps::guest_default_memory_order to set TCGContext::guest_mo.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
accel/tcg/translate-all.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c
index 7467255f6e4..c007b9a1902 100644
--- a/accel/tcg/translate-all.c
+++ b/accel/tcg/translate-all.c
@@ -353,7 +353,7 @@ TranslationBlock *tb_gen_code(CPUState *cpu,
tcg_ctx->tlb_dyn_max_bits = CPU_TLB_DYN_MAX_BITS;
#endif
tcg_ctx->insn_start_words = TARGET_INSN_START_WORDS;
- tcg_ctx->guest_mo = TCG_GUEST_DEFAULT_MO;
+ tcg_ctx->guest_mo = cpu->cc->tcg_ops->guest_default_memory_order;
restart_translate:
trace_translate_block(tb, pc, tb->tc.ptr);
--
2.47.1
^ permalink raw reply related [flat|nested] 23+ messages in thread* [PATCH-for-10.1 v3 12/19] tcg: Propagate CPUState argument to cpu_req_mo()
2025-04-03 22:04 [PATCH-for-10.1 v3 00/19] tcg: philmd's queue Philippe Mathieu-Daudé
` (10 preceding siblings ...)
2025-04-03 22:04 ` [PATCH-for-10.1 v3 11/19] tcg: Remove use of TCG_GUEST_DEFAULT_MO in tb_gen_code() Philippe Mathieu-Daudé
@ 2025-04-03 22:04 ` Philippe Mathieu-Daudé
2025-04-03 22:04 ` [PATCH-for-10.1 v3 13/19] tcg: Have tcg_req_mo() use TCGCPUOps::guest_default_memory_order Philippe Mathieu-Daudé
` (6 subsequent siblings)
18 siblings, 0 replies; 23+ messages in thread
From: Philippe Mathieu-Daudé @ 2025-04-03 22:04 UTC (permalink / raw)
To: qemu-devel; +Cc: Richard Henderson, Pierrick Bouvier
In preparation of having tcg_req_mo() access CPUState in
the next commit, pass it to cpu_req_mo(), its single caller.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
accel/tcg/internal-target.h | 3 ++-
accel/tcg/cputlb.c | 20 ++++++++++----------
accel/tcg/user-exec.c | 20 ++++++++++----------
3 files changed, 22 insertions(+), 21 deletions(-)
diff --git a/accel/tcg/internal-target.h b/accel/tcg/internal-target.h
index 1a46a7c87dc..23aac39b572 100644
--- a/accel/tcg/internal-target.h
+++ b/accel/tcg/internal-target.h
@@ -59,12 +59,13 @@ G_NORETURN void cpu_io_recompile(CPUState *cpu, uintptr_t retaddr);
/**
* cpu_req_mo:
+ * @cpu: CPUState
* @type: TCGBar
*
* If tcg_req_mo indicates a barrier for @type is required
* for the guest memory model, issue a host memory barrier.
*/
-#define cpu_req_mo(type) \
+#define cpu_req_mo(cpu, type) \
do { \
if (tcg_req_mo(type)) { \
smp_mb(); \
diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c
index 2cafd38d2af..35b1ff03a51 100644
--- a/accel/tcg/cputlb.c
+++ b/accel/tcg/cputlb.c
@@ -2324,7 +2324,7 @@ static uint8_t do_ld1_mmu(CPUState *cpu, vaddr addr, MemOpIdx oi,
MMULookupLocals l;
bool crosspage;
- cpu_req_mo(TCG_MO_LD_LD | TCG_MO_ST_LD);
+ cpu_req_mo(cpu, TCG_MO_LD_LD | TCG_MO_ST_LD);
crosspage = mmu_lookup(cpu, addr, oi, ra, access_type, &l);
tcg_debug_assert(!crosspage);
@@ -2339,7 +2339,7 @@ static uint16_t do_ld2_mmu(CPUState *cpu, vaddr addr, MemOpIdx oi,
uint16_t ret;
uint8_t a, b;
- cpu_req_mo(TCG_MO_LD_LD | TCG_MO_ST_LD);
+ cpu_req_mo(cpu, TCG_MO_LD_LD | TCG_MO_ST_LD);
crosspage = mmu_lookup(cpu, addr, oi, ra, access_type, &l);
if (likely(!crosspage)) {
return do_ld_2(cpu, &l.page[0], l.mmu_idx, access_type, l.memop, ra);
@@ -2363,7 +2363,7 @@ static uint32_t do_ld4_mmu(CPUState *cpu, vaddr addr, MemOpIdx oi,
bool crosspage;
uint32_t ret;
- cpu_req_mo(TCG_MO_LD_LD | TCG_MO_ST_LD);
+ cpu_req_mo(cpu, TCG_MO_LD_LD | TCG_MO_ST_LD);
crosspage = mmu_lookup(cpu, addr, oi, ra, access_type, &l);
if (likely(!crosspage)) {
return do_ld_4(cpu, &l.page[0], l.mmu_idx, access_type, l.memop, ra);
@@ -2384,7 +2384,7 @@ static uint64_t do_ld8_mmu(CPUState *cpu, vaddr addr, MemOpIdx oi,
bool crosspage;
uint64_t ret;
- cpu_req_mo(TCG_MO_LD_LD | TCG_MO_ST_LD);
+ cpu_req_mo(cpu, TCG_MO_LD_LD | TCG_MO_ST_LD);
crosspage = mmu_lookup(cpu, addr, oi, ra, access_type, &l);
if (likely(!crosspage)) {
return do_ld_8(cpu, &l.page[0], l.mmu_idx, access_type, l.memop, ra);
@@ -2407,7 +2407,7 @@ static Int128 do_ld16_mmu(CPUState *cpu, vaddr addr,
Int128 ret;
int first;
- cpu_req_mo(TCG_MO_LD_LD | TCG_MO_ST_LD);
+ cpu_req_mo(cpu, TCG_MO_LD_LD | TCG_MO_ST_LD);
crosspage = mmu_lookup(cpu, addr, oi, ra, MMU_DATA_LOAD, &l);
if (likely(!crosspage)) {
if (unlikely(l.page[0].flags & TLB_MMIO)) {
@@ -2735,7 +2735,7 @@ static void do_st1_mmu(CPUState *cpu, vaddr addr, uint8_t val,
MMULookupLocals l;
bool crosspage;
- cpu_req_mo(TCG_MO_LD_ST | TCG_MO_ST_ST);
+ cpu_req_mo(cpu, TCG_MO_LD_ST | TCG_MO_ST_ST);
crosspage = mmu_lookup(cpu, addr, oi, ra, MMU_DATA_STORE, &l);
tcg_debug_assert(!crosspage);
@@ -2749,7 +2749,7 @@ static void do_st2_mmu(CPUState *cpu, vaddr addr, uint16_t val,
bool crosspage;
uint8_t a, b;
- cpu_req_mo(TCG_MO_LD_ST | TCG_MO_ST_ST);
+ cpu_req_mo(cpu, TCG_MO_LD_ST | TCG_MO_ST_ST);
crosspage = mmu_lookup(cpu, addr, oi, ra, MMU_DATA_STORE, &l);
if (likely(!crosspage)) {
do_st_2(cpu, &l.page[0], val, l.mmu_idx, l.memop, ra);
@@ -2771,7 +2771,7 @@ static void do_st4_mmu(CPUState *cpu, vaddr addr, uint32_t val,
MMULookupLocals l;
bool crosspage;
- cpu_req_mo(TCG_MO_LD_ST | TCG_MO_ST_ST);
+ cpu_req_mo(cpu, TCG_MO_LD_ST | TCG_MO_ST_ST);
crosspage = mmu_lookup(cpu, addr, oi, ra, MMU_DATA_STORE, &l);
if (likely(!crosspage)) {
do_st_4(cpu, &l.page[0], val, l.mmu_idx, l.memop, ra);
@@ -2792,7 +2792,7 @@ static void do_st8_mmu(CPUState *cpu, vaddr addr, uint64_t val,
MMULookupLocals l;
bool crosspage;
- cpu_req_mo(TCG_MO_LD_ST | TCG_MO_ST_ST);
+ cpu_req_mo(cpu, TCG_MO_LD_ST | TCG_MO_ST_ST);
crosspage = mmu_lookup(cpu, addr, oi, ra, MMU_DATA_STORE, &l);
if (likely(!crosspage)) {
do_st_8(cpu, &l.page[0], val, l.mmu_idx, l.memop, ra);
@@ -2815,7 +2815,7 @@ static void do_st16_mmu(CPUState *cpu, vaddr addr, Int128 val,
uint64_t a, b;
int first;
- cpu_req_mo(TCG_MO_LD_ST | TCG_MO_ST_ST);
+ cpu_req_mo(cpu, TCG_MO_LD_ST | TCG_MO_ST_ST);
crosspage = mmu_lookup(cpu, addr, oi, ra, MMU_DATA_STORE, &l);
if (likely(!crosspage)) {
if (unlikely(l.page[0].flags & TLB_MMIO)) {
diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c
index 1b878ead7a7..3f4d6824460 100644
--- a/accel/tcg/user-exec.c
+++ b/accel/tcg/user-exec.c
@@ -1061,7 +1061,7 @@ static uint8_t do_ld1_mmu(CPUState *cpu, vaddr addr, MemOpIdx oi,
void *haddr;
uint8_t ret;
- cpu_req_mo(TCG_MO_LD_LD | TCG_MO_ST_LD);
+ cpu_req_mo(cpu, TCG_MO_LD_LD | TCG_MO_ST_LD);
haddr = cpu_mmu_lookup(cpu, addr, get_memop(oi), ra, access_type);
ret = ldub_p(haddr);
clear_helper_retaddr();
@@ -1075,7 +1075,7 @@ static uint16_t do_ld2_mmu(CPUState *cpu, vaddr addr, MemOpIdx oi,
uint16_t ret;
MemOp mop = get_memop(oi);
- cpu_req_mo(TCG_MO_LD_LD | TCG_MO_ST_LD);
+ cpu_req_mo(cpu, TCG_MO_LD_LD | TCG_MO_ST_LD);
haddr = cpu_mmu_lookup(cpu, addr, mop, ra, access_type);
ret = load_atom_2(cpu, ra, haddr, mop);
clear_helper_retaddr();
@@ -1093,7 +1093,7 @@ static uint32_t do_ld4_mmu(CPUState *cpu, vaddr addr, MemOpIdx oi,
uint32_t ret;
MemOp mop = get_memop(oi);
- cpu_req_mo(TCG_MO_LD_LD | TCG_MO_ST_LD);
+ cpu_req_mo(cpu, TCG_MO_LD_LD | TCG_MO_ST_LD);
haddr = cpu_mmu_lookup(cpu, addr, mop, ra, access_type);
ret = load_atom_4(cpu, ra, haddr, mop);
clear_helper_retaddr();
@@ -1111,7 +1111,7 @@ static uint64_t do_ld8_mmu(CPUState *cpu, vaddr addr, MemOpIdx oi,
uint64_t ret;
MemOp mop = get_memop(oi);
- cpu_req_mo(TCG_MO_LD_LD | TCG_MO_ST_LD);
+ cpu_req_mo(cpu, TCG_MO_LD_LD | TCG_MO_ST_LD);
haddr = cpu_mmu_lookup(cpu, addr, mop, ra, access_type);
ret = load_atom_8(cpu, ra, haddr, mop);
clear_helper_retaddr();
@@ -1130,7 +1130,7 @@ static Int128 do_ld16_mmu(CPUState *cpu, abi_ptr addr,
MemOp mop = get_memop(oi);
tcg_debug_assert((mop & MO_SIZE) == MO_128);
- cpu_req_mo(TCG_MO_LD_LD | TCG_MO_ST_LD);
+ cpu_req_mo(cpu, TCG_MO_LD_LD | TCG_MO_ST_LD);
haddr = cpu_mmu_lookup(cpu, addr, mop, ra, MMU_DATA_LOAD);
ret = load_atom_16(cpu, ra, haddr, mop);
clear_helper_retaddr();
@@ -1146,7 +1146,7 @@ static void do_st1_mmu(CPUState *cpu, vaddr addr, uint8_t val,
{
void *haddr;
- cpu_req_mo(TCG_MO_LD_ST | TCG_MO_ST_ST);
+ cpu_req_mo(cpu, TCG_MO_LD_ST | TCG_MO_ST_ST);
haddr = cpu_mmu_lookup(cpu, addr, get_memop(oi), ra, MMU_DATA_STORE);
stb_p(haddr, val);
clear_helper_retaddr();
@@ -1158,7 +1158,7 @@ static void do_st2_mmu(CPUState *cpu, vaddr addr, uint16_t val,
void *haddr;
MemOp mop = get_memop(oi);
- cpu_req_mo(TCG_MO_LD_ST | TCG_MO_ST_ST);
+ cpu_req_mo(cpu, TCG_MO_LD_ST | TCG_MO_ST_ST);
haddr = cpu_mmu_lookup(cpu, addr, mop, ra, MMU_DATA_STORE);
if (mop & MO_BSWAP) {
@@ -1174,7 +1174,7 @@ static void do_st4_mmu(CPUState *cpu, vaddr addr, uint32_t val,
void *haddr;
MemOp mop = get_memop(oi);
- cpu_req_mo(TCG_MO_LD_ST | TCG_MO_ST_ST);
+ cpu_req_mo(cpu, TCG_MO_LD_ST | TCG_MO_ST_ST);
haddr = cpu_mmu_lookup(cpu, addr, mop, ra, MMU_DATA_STORE);
if (mop & MO_BSWAP) {
@@ -1190,7 +1190,7 @@ static void do_st8_mmu(CPUState *cpu, vaddr addr, uint64_t val,
void *haddr;
MemOp mop = get_memop(oi);
- cpu_req_mo(TCG_MO_LD_ST | TCG_MO_ST_ST);
+ cpu_req_mo(cpu, TCG_MO_LD_ST | TCG_MO_ST_ST);
haddr = cpu_mmu_lookup(cpu, addr, mop, ra, MMU_DATA_STORE);
if (mop & MO_BSWAP) {
@@ -1206,7 +1206,7 @@ static void do_st16_mmu(CPUState *cpu, vaddr addr, Int128 val,
void *haddr;
MemOpIdx mop = get_memop(oi);
- cpu_req_mo(TCG_MO_LD_ST | TCG_MO_ST_ST);
+ cpu_req_mo(cpu, TCG_MO_LD_ST | TCG_MO_ST_ST);
haddr = cpu_mmu_lookup(cpu, addr, mop, ra, MMU_DATA_STORE);
if (mop & MO_BSWAP) {
--
2.47.1
^ permalink raw reply related [flat|nested] 23+ messages in thread* [PATCH-for-10.1 v3 13/19] tcg: Have tcg_req_mo() use TCGCPUOps::guest_default_memory_order
2025-04-03 22:04 [PATCH-for-10.1 v3 00/19] tcg: philmd's queue Philippe Mathieu-Daudé
` (11 preceding siblings ...)
2025-04-03 22:04 ` [PATCH-for-10.1 v3 12/19] tcg: Propagate CPUState argument to cpu_req_mo() Philippe Mathieu-Daudé
@ 2025-04-03 22:04 ` Philippe Mathieu-Daudé
2025-04-03 22:04 ` [PATCH-for-10.1 v3 14/19] tcg: Remove the TCG_GUEST_DEFAULT_MO definition globally Philippe Mathieu-Daudé
` (5 subsequent siblings)
18 siblings, 0 replies; 23+ messages in thread
From: Philippe Mathieu-Daudé @ 2025-04-03 22:04 UTC (permalink / raw)
To: qemu-devel; +Cc: Richard Henderson, Pierrick Bouvier
In order to use TCG with multiple targets, replace the
compile time use of TCG_GUEST_DEFAULT_MO by a runtime access
to TCGCPUOps::guest_default_memory_order via CPUState.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
accel/tcg/internal-target.h | 9 ++++-----
1 file changed, 4 insertions(+), 5 deletions(-)
diff --git a/accel/tcg/internal-target.h b/accel/tcg/internal-target.h
index 23aac39b572..f5a3fd7e402 100644
--- a/accel/tcg/internal-target.h
+++ b/accel/tcg/internal-target.h
@@ -46,16 +46,15 @@ G_NORETURN void cpu_io_recompile(CPUState *cpu, uintptr_t retaddr);
/**
* tcg_req_mo:
+ * @guest_mo: Guest default memory order
* @type: TCGBar
*
* Filter @type to the barrier that is required for the guest
* memory ordering vs the host memory ordering. A non-zero
* result indicates that some barrier is required.
- *
- * This is a macro so that it's constant even without optimization.
*/
-#define tcg_req_mo(type) \
- ((type) & TCG_GUEST_DEFAULT_MO & ~TCG_TARGET_DEFAULT_MO)
+#define tcg_req_mo(guest_mo, type) \
+ ((type) & guest_mo & ~TCG_TARGET_DEFAULT_MO)
/**
* cpu_req_mo:
@@ -67,7 +66,7 @@ G_NORETURN void cpu_io_recompile(CPUState *cpu, uintptr_t retaddr);
*/
#define cpu_req_mo(cpu, type) \
do { \
- if (tcg_req_mo(type)) { \
+ if (tcg_req_mo(cpu->cc->tcg_ops->guest_default_memory_order, type)) { \
smp_mb(); \
} \
} while (0)
--
2.47.1
^ permalink raw reply related [flat|nested] 23+ messages in thread* [PATCH-for-10.1 v3 14/19] tcg: Remove the TCG_GUEST_DEFAULT_MO definition globally
2025-04-03 22:04 [PATCH-for-10.1 v3 00/19] tcg: philmd's queue Philippe Mathieu-Daudé
` (12 preceding siblings ...)
2025-04-03 22:04 ` [PATCH-for-10.1 v3 13/19] tcg: Have tcg_req_mo() use TCGCPUOps::guest_default_memory_order Philippe Mathieu-Daudé
@ 2025-04-03 22:04 ` Philippe Mathieu-Daudé
2025-04-04 23:48 ` Philippe Mathieu-Daudé
2025-04-03 22:04 ` [PATCH-for-10.1 v3 15/19] tcg: Move cpu_req_mo() macro to target-agnostic 'backend-ldst.h' Philippe Mathieu-Daudé
` (4 subsequent siblings)
18 siblings, 1 reply; 23+ messages in thread
From: Philippe Mathieu-Daudé @ 2025-04-03 22:04 UTC (permalink / raw)
To: qemu-devel; +Cc: Richard Henderson, Pierrick Bouvier
By directly using TCGCPUOps::guest_default_memory_order,
we don't need the TCG_GUEST_DEFAULT_MO definition anymore.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Anton Johansson <anjo@rev.ng>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
---
docs/devel/multi-thread-tcg.rst | 4 ++--
target/alpha/cpu-param.h | 3 ---
target/arm/cpu-param.h | 3 ---
target/avr/cpu-param.h | 2 --
target/hexagon/cpu-param.h | 3 ---
target/hppa/cpu-param.h | 8 --------
target/i386/cpu-param.h | 3 ---
target/loongarch/cpu-param.h | 2 --
target/m68k/cpu-param.h | 3 ---
target/microblaze/cpu-param.h | 3 ---
target/mips/cpu-param.h | 2 --
target/openrisc/cpu-param.h | 2 --
target/ppc/cpu-param.h | 2 --
target/riscv/cpu-param.h | 2 --
target/rx/cpu-param.h | 3 ---
target/s390x/cpu-param.h | 6 ------
target/sh4/cpu-param.h | 3 ---
target/sparc/cpu-param.h | 23 -----------------------
target/tricore/cpu-param.h | 3 ---
target/xtensa/cpu-param.h | 3 ---
target/alpha/cpu.c | 3 ++-
target/arm/cpu.c | 3 ++-
target/arm/tcg/cpu-v7m.c | 3 ++-
target/avr/cpu.c | 2 +-
target/hexagon/cpu.c | 3 ++-
target/hppa/cpu.c | 8 +++++++-
target/i386/tcg/tcg-cpu.c | 5 ++++-
target/loongarch/cpu.c | 2 +-
target/m68k/cpu.c | 3 ++-
target/microblaze/cpu.c | 3 ++-
target/mips/cpu.c | 2 +-
target/openrisc/cpu.c | 2 +-
target/ppc/cpu_init.c | 2 +-
target/riscv/tcg/tcg-cpu.c | 2 +-
target/rx/cpu.c | 3 ++-
target/s390x/cpu.c | 6 +++++-
target/sh4/cpu.c | 3 ++-
target/sparc/cpu.c | 23 ++++++++++++++++++++++-
target/tricore/cpu.c | 3 ++-
target/xtensa/cpu.c | 3 ++-
40 files changed, 66 insertions(+), 101 deletions(-)
diff --git a/docs/devel/multi-thread-tcg.rst b/docs/devel/multi-thread-tcg.rst
index b0f473961dd..14a2a9dc7b5 100644
--- a/docs/devel/multi-thread-tcg.rst
+++ b/docs/devel/multi-thread-tcg.rst
@@ -28,8 +28,8 @@ vCPU Scheduling
We introduce a new running mode where each vCPU will run on its own
user-space thread. This is enabled by default for all FE/BE
combinations where the host memory model is able to accommodate the
-guest (TCG_GUEST_DEFAULT_MO & ~TCG_TARGET_DEFAULT_MO is zero) and the
-guest has had the required work done to support this safely
+guest (TCGCPUOps::guest_default_memory_order & ~TCG_TARGET_DEFAULT_MO is zero)
+and the guest has had the required work done to support this safely
(TARGET_SUPPORTS_MTTCG).
System emulation will fall back to the original round robin approach
diff --git a/target/alpha/cpu-param.h b/target/alpha/cpu-param.h
index dd44feb1793..a799f42db31 100644
--- a/target/alpha/cpu-param.h
+++ b/target/alpha/cpu-param.h
@@ -26,7 +26,4 @@
#define TARGET_INSN_START_EXTRA_WORDS 0
-/* Alpha processors have a weak memory model */
-#define TCG_GUEST_DEFAULT_MO (0)
-
#endif
diff --git a/target/arm/cpu-param.h b/target/arm/cpu-param.h
index 2cee4be6938..5c5bc8a009e 100644
--- a/target/arm/cpu-param.h
+++ b/target/arm/cpu-param.h
@@ -44,7 +44,4 @@
*/
#define TARGET_INSN_START_EXTRA_WORDS 2
-/* ARM processors have a weak memory model */
-#define TCG_GUEST_DEFAULT_MO (0)
-
#endif
diff --git a/target/avr/cpu-param.h b/target/avr/cpu-param.h
index 9d37848d97d..f74bfc25804 100644
--- a/target/avr/cpu-param.h
+++ b/target/avr/cpu-param.h
@@ -27,6 +27,4 @@
#define TARGET_INSN_START_EXTRA_WORDS 0
-#define TCG_GUEST_DEFAULT_MO 0
-
#endif
diff --git a/target/hexagon/cpu-param.h b/target/hexagon/cpu-param.h
index 7cc63a01d4b..635d509e743 100644
--- a/target/hexagon/cpu-param.h
+++ b/target/hexagon/cpu-param.h
@@ -25,7 +25,4 @@
#define TARGET_INSN_START_EXTRA_WORDS 0
-/* MTTCG not yet supported: require strict ordering */
-#define TCG_GUEST_DEFAULT_MO TCG_MO_ALL
-
#endif
diff --git a/target/hppa/cpu-param.h b/target/hppa/cpu-param.h
index 68ed84e84af..9bf7ac76d0c 100644
--- a/target/hppa/cpu-param.h
+++ b/target/hppa/cpu-param.h
@@ -21,12 +21,4 @@
#define TARGET_INSN_START_EXTRA_WORDS 2
-/* PA-RISC 1.x processors have a strong memory model. */
-/*
- * ??? While we do not yet implement PA-RISC 2.0, those processors have
- * a weak memory model, but with TLB bits that force ordering on a per-page
- * basis. It's probably easier to fall back to a strong memory model.
- */
-#define TCG_GUEST_DEFAULT_MO TCG_MO_ALL
-
#endif
diff --git a/target/i386/cpu-param.h b/target/i386/cpu-param.h
index 0c8efce8619..ebb844bcc83 100644
--- a/target/i386/cpu-param.h
+++ b/target/i386/cpu-param.h
@@ -24,7 +24,4 @@
#define TARGET_INSN_START_EXTRA_WORDS 1
-/* The x86 has a strong memory model with some store-after-load re-ordering */
-#define TCG_GUEST_DEFAULT_MO (TCG_MO_ALL & ~TCG_MO_ST_LD)
-
#endif
diff --git a/target/loongarch/cpu-param.h b/target/loongarch/cpu-param.h
index dbe414bb35a..58cc45a377e 100644
--- a/target/loongarch/cpu-param.h
+++ b/target/loongarch/cpu-param.h
@@ -15,6 +15,4 @@
#define TARGET_INSN_START_EXTRA_WORDS 0
-#define TCG_GUEST_DEFAULT_MO (0)
-
#endif
diff --git a/target/m68k/cpu-param.h b/target/m68k/cpu-param.h
index 10a8d74bfa9..256a2b5f8b2 100644
--- a/target/m68k/cpu-param.h
+++ b/target/m68k/cpu-param.h
@@ -19,7 +19,4 @@
#define TARGET_INSN_START_EXTRA_WORDS 1
-/* MTTCG not yet supported: require strict ordering */
-#define TCG_GUEST_DEFAULT_MO TCG_MO_ALL
-
#endif
diff --git a/target/microblaze/cpu-param.h b/target/microblaze/cpu-param.h
index 5d55e0e3c4a..e0a37945136 100644
--- a/target/microblaze/cpu-param.h
+++ b/target/microblaze/cpu-param.h
@@ -29,7 +29,4 @@
#define TARGET_INSN_START_EXTRA_WORDS 1
-/* MicroBlaze is always in-order. */
-#define TCG_GUEST_DEFAULT_MO TCG_MO_ALL
-
#endif
diff --git a/target/mips/cpu-param.h b/target/mips/cpu-param.h
index 99ca8d1684c..58f450827f7 100644
--- a/target/mips/cpu-param.h
+++ b/target/mips/cpu-param.h
@@ -22,6 +22,4 @@
#define TARGET_INSN_START_EXTRA_WORDS 2
-#define TCG_GUEST_DEFAULT_MO (0)
-
#endif
diff --git a/target/openrisc/cpu-param.h b/target/openrisc/cpu-param.h
index 7ea0ecb55a6..b4f57bbe692 100644
--- a/target/openrisc/cpu-param.h
+++ b/target/openrisc/cpu-param.h
@@ -14,6 +14,4 @@
#define TARGET_INSN_START_EXTRA_WORDS 1
-#define TCG_GUEST_DEFAULT_MO (0)
-
#endif
diff --git a/target/ppc/cpu-param.h b/target/ppc/cpu-param.h
index d0651d2ac89..e4ed9080ee9 100644
--- a/target/ppc/cpu-param.h
+++ b/target/ppc/cpu-param.h
@@ -39,6 +39,4 @@
#define TARGET_INSN_START_EXTRA_WORDS 0
-#define TCG_GUEST_DEFAULT_MO 0
-
#endif
diff --git a/target/riscv/cpu-param.h b/target/riscv/cpu-param.h
index ff4ba81965a..cfdc67c258c 100644
--- a/target/riscv/cpu-param.h
+++ b/target/riscv/cpu-param.h
@@ -34,6 +34,4 @@
* - M mode HLV/HLVX/HSV 0b111
*/
-#define TCG_GUEST_DEFAULT_MO 0
-
#endif
diff --git a/target/rx/cpu-param.h b/target/rx/cpu-param.h
index fe39a77ca38..84934f3bcaf 100644
--- a/target/rx/cpu-param.h
+++ b/target/rx/cpu-param.h
@@ -26,7 +26,4 @@
#define TARGET_INSN_START_EXTRA_WORDS 0
-/* MTTCG not yet supported: require strict ordering */
-#define TCG_GUEST_DEFAULT_MO TCG_MO_ALL
-
#endif
diff --git a/target/s390x/cpu-param.h b/target/s390x/cpu-param.h
index a8a4377f4ff..abfae3bedfb 100644
--- a/target/s390x/cpu-param.h
+++ b/target/s390x/cpu-param.h
@@ -14,10 +14,4 @@
#define TARGET_INSN_START_EXTRA_WORDS 2
-/*
- * The z/Architecture has a strong memory model with some
- * store-after-load re-ordering.
- */
-#define TCG_GUEST_DEFAULT_MO (TCG_MO_ALL & ~TCG_MO_ST_LD)
-
#endif
diff --git a/target/sh4/cpu-param.h b/target/sh4/cpu-param.h
index acdf2397495..f328715ee86 100644
--- a/target/sh4/cpu-param.h
+++ b/target/sh4/cpu-param.h
@@ -18,7 +18,4 @@
#define TARGET_INSN_START_EXTRA_WORDS 1
-/* MTTCG not yet supported: require strict ordering */
-#define TCG_GUEST_DEFAULT_MO TCG_MO_ALL
-
#endif
diff --git a/target/sparc/cpu-param.h b/target/sparc/cpu-param.h
index 62d47b804bb..45eea9d6bac 100644
--- a/target/sparc/cpu-param.h
+++ b/target/sparc/cpu-param.h
@@ -23,27 +23,4 @@
#define TARGET_INSN_START_EXTRA_WORDS 1
-/*
- * From Oracle SPARC Architecture 2015:
- *
- * Compatibility notes: The PSO memory model described in SPARC V8 and
- * SPARC V9 compatibility architecture specifications was never implemented
- * in a SPARC V9 implementation and is not included in the Oracle SPARC
- * Architecture specification.
- *
- * The RMO memory model described in the SPARC V9 specification was
- * implemented in some non-Sun SPARC V9 implementations, but is not
- * directly supported in Oracle SPARC Architecture 2015 implementations.
- *
- * Therefore always use TSO in QEMU.
- *
- * D.5 Specification of Partial Store Order (PSO)
- * ... [loads] are followed by an implied MEMBAR #LoadLoad | #LoadStore.
- *
- * D.6 Specification of Total Store Order (TSO)
- * ... PSO with the additional requirement that all [stores] are followed
- * by an implied MEMBAR #StoreStore.
- */
-#define TCG_GUEST_DEFAULT_MO (TCG_MO_LD_LD | TCG_MO_LD_ST | TCG_MO_ST_ST)
-
#endif
diff --git a/target/tricore/cpu-param.h b/target/tricore/cpu-param.h
index 45fde756b6a..eb33a67c419 100644
--- a/target/tricore/cpu-param.h
+++ b/target/tricore/cpu-param.h
@@ -14,7 +14,4 @@
#define TARGET_INSN_START_EXTRA_WORDS 0
-/* MTTCG not yet supported: require strict ordering */
-#define TCG_GUEST_DEFAULT_MO TCG_MO_ALL
-
#endif
diff --git a/target/xtensa/cpu-param.h b/target/xtensa/cpu-param.h
index e7cb747aaae..7a0c22c9005 100644
--- a/target/xtensa/cpu-param.h
+++ b/target/xtensa/cpu-param.h
@@ -18,7 +18,4 @@
#define TARGET_INSN_START_EXTRA_WORDS 0
-/* Xtensa processors have a weak memory model */
-#define TCG_GUEST_DEFAULT_MO (0)
-
#endif
diff --git a/target/alpha/cpu.c b/target/alpha/cpu.c
index 6f931117a25..eeaf3a81c1a 100644
--- a/target/alpha/cpu.c
+++ b/target/alpha/cpu.c
@@ -235,7 +235,8 @@ static const struct SysemuCPUOps alpha_sysemu_ops = {
#include "accel/tcg/cpu-ops.h"
static const TCGCPUOps alpha_tcg_ops = {
- .guest_default_memory_order = TCG_GUEST_DEFAULT_MO,
+ /* Alpha processors have a weak memory model */
+ .guest_default_memory_order = 0,
.initialize = alpha_translate_init,
.translate_code = alpha_translate_code,
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index 3f20e258fd0..3e9760b5518 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -2671,7 +2671,8 @@ static const struct SysemuCPUOps arm_sysemu_ops = {
#ifdef CONFIG_TCG
static const TCGCPUOps arm_tcg_ops = {
- .guest_default_memory_order = TCG_GUEST_DEFAULT_MO,
+ /* ARM processors have a weak memory model */
+ .guest_default_memory_order = 0,
.initialize = arm_translate_init,
.translate_code = arm_translate_code,
diff --git a/target/arm/tcg/cpu-v7m.c b/target/arm/tcg/cpu-v7m.c
index 4553fe9de07..89d4e4b4a2f 100644
--- a/target/arm/tcg/cpu-v7m.c
+++ b/target/arm/tcg/cpu-v7m.c
@@ -232,7 +232,8 @@ static void cortex_m55_initfn(Object *obj)
}
static const TCGCPUOps arm_v7m_tcg_ops = {
- .guest_default_memory_order = TCG_GUEST_DEFAULT_MO,
+ /* ARM processors have a weak memory model */
+ .guest_default_memory_order = 0,
.initialize = arm_translate_init,
.translate_code = arm_translate_code,
diff --git a/target/avr/cpu.c b/target/avr/cpu.c
index 67918684faf..8f79cf4c08b 100644
--- a/target/avr/cpu.c
+++ b/target/avr/cpu.c
@@ -224,7 +224,7 @@ static const struct SysemuCPUOps avr_sysemu_ops = {
#include "accel/tcg/cpu-ops.h"
static const TCGCPUOps avr_tcg_ops = {
- .guest_default_memory_order = TCG_GUEST_DEFAULT_MO,
+ .guest_default_memory_order = 0,
.initialize = avr_cpu_tcg_init,
.translate_code = avr_cpu_translate_code,
.synchronize_from_tb = avr_cpu_synchronize_from_tb,
diff --git a/target/hexagon/cpu.c b/target/hexagon/cpu.c
index b12e0dccd09..3d14e5cc6a0 100644
--- a/target/hexagon/cpu.c
+++ b/target/hexagon/cpu.c
@@ -325,7 +325,8 @@ static void hexagon_cpu_init(Object *obj)
#include "accel/tcg/cpu-ops.h"
static const TCGCPUOps hexagon_tcg_ops = {
- .guest_default_memory_order = TCG_GUEST_DEFAULT_MO,
+ /* MTTCG not yet supported: require strict ordering */
+ .guest_default_memory_order = TCG_MO_ALL,
.initialize = hexagon_translate_init,
.translate_code = hexagon_translate_code,
.synchronize_from_tb = hexagon_cpu_synchronize_from_tb,
diff --git a/target/hppa/cpu.c b/target/hppa/cpu.c
index ac4560febea..dfbd9330565 100644
--- a/target/hppa/cpu.c
+++ b/target/hppa/cpu.c
@@ -253,7 +253,13 @@ static const struct SysemuCPUOps hppa_sysemu_ops = {
#include "accel/tcg/cpu-ops.h"
static const TCGCPUOps hppa_tcg_ops = {
- .guest_default_memory_order = TCG_GUEST_DEFAULT_MO,
+ /* PA-RISC 1.x processors have a strong memory model. */
+ /*
+ * ??? While we do not yet implement PA-RISC 2.0, those processors have
+ * a weak memory model, but with TLB bits that force ordering on a per-page
+ * basis. It's probably easier to fall back to a strong memory model.
+ */
+ .guest_default_memory_order = TCG_MO_ALL,
.initialize = hppa_translate_init,
.translate_code = hppa_translate_code,
diff --git a/target/i386/tcg/tcg-cpu.c b/target/i386/tcg/tcg-cpu.c
index 3e1b315340c..d941df09560 100644
--- a/target/i386/tcg/tcg-cpu.c
+++ b/target/i386/tcg/tcg-cpu.c
@@ -125,7 +125,10 @@ static bool x86_debug_check_breakpoint(CPUState *cs)
#include "accel/tcg/cpu-ops.h"
static const TCGCPUOps x86_tcg_ops = {
- .guest_default_memory_order = TCG_GUEST_DEFAULT_MO,
+ /*
+ * The x86 has a strong memory model with some store-after-load re-ordering
+ */
+ .guest_default_memory_order = TCG_MO_ALL & ~TCG_MO_ST_LD,
.initialize = tcg_x86_init,
.translate_code = x86_translate_code,
.synchronize_from_tb = x86_cpu_synchronize_from_tb,
diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c
index ee74509a664..f5b8ef29ab0 100644
--- a/target/loongarch/cpu.c
+++ b/target/loongarch/cpu.c
@@ -864,7 +864,7 @@ static void loongarch_cpu_dump_state(CPUState *cs, FILE *f, int flags)
#include "accel/tcg/cpu-ops.h"
static const TCGCPUOps loongarch_tcg_ops = {
- .guest_default_memory_order = TCG_GUEST_DEFAULT_MO,
+ .guest_default_memory_order = 0,
.initialize = loongarch_translate_init,
.translate_code = loongarch_translate_code,
diff --git a/target/m68k/cpu.c b/target/m68k/cpu.c
index bfde9b85948..b2d8c8f1dea 100644
--- a/target/m68k/cpu.c
+++ b/target/m68k/cpu.c
@@ -589,7 +589,8 @@ static const struct SysemuCPUOps m68k_sysemu_ops = {
#include "accel/tcg/cpu-ops.h"
static const TCGCPUOps m68k_tcg_ops = {
- .guest_default_memory_order = TCG_GUEST_DEFAULT_MO,
+ /* MTTCG not yet supported: require strict ordering */
+ .guest_default_memory_order = TCG_MO_ALL,
.initialize = m68k_tcg_init,
.translate_code = m68k_translate_code,
diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c
index e46863574c6..4efba0dddb2 100644
--- a/target/microblaze/cpu.c
+++ b/target/microblaze/cpu.c
@@ -427,7 +427,8 @@ static const struct SysemuCPUOps mb_sysemu_ops = {
#include "accel/tcg/cpu-ops.h"
static const TCGCPUOps mb_tcg_ops = {
- .guest_default_memory_order = TCG_GUEST_DEFAULT_MO,
+ /* MicroBlaze is always in-order. */
+ .guest_default_memory_order = TCG_MO_ALL,
.initialize = mb_tcg_init,
.translate_code = mb_translate_code,
diff --git a/target/mips/cpu.c b/target/mips/cpu.c
index 860ec398229..010773405a8 100644
--- a/target/mips/cpu.c
+++ b/target/mips/cpu.c
@@ -550,7 +550,7 @@ static const Property mips_cpu_properties[] = {
#ifdef CONFIG_TCG
#include "accel/tcg/cpu-ops.h"
static const TCGCPUOps mips_tcg_ops = {
- .guest_default_memory_order = TCG_GUEST_DEFAULT_MO,
+ .guest_default_memory_order = 0,
.initialize = mips_tcg_init,
.translate_code = mips_translate_code,
diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c
index e62c698a407..87fe779042c 100644
--- a/target/openrisc/cpu.c
+++ b/target/openrisc/cpu.c
@@ -243,7 +243,7 @@ static const struct SysemuCPUOps openrisc_sysemu_ops = {
#include "accel/tcg/cpu-ops.h"
static const TCGCPUOps openrisc_tcg_ops = {
- .guest_default_memory_order = TCG_GUEST_DEFAULT_MO,
+ .guest_default_memory_order = 0,
.initialize = openrisc_translate_init,
.translate_code = openrisc_translate_code,
diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c
index 57565c9a2f2..8300fa5777e 100644
--- a/target/ppc/cpu_init.c
+++ b/target/ppc/cpu_init.c
@@ -7478,7 +7478,7 @@ static const struct SysemuCPUOps ppc_sysemu_ops = {
#include "accel/tcg/cpu-ops.h"
static const TCGCPUOps ppc_tcg_ops = {
- .guest_default_memory_order = TCG_GUEST_DEFAULT_MO,
+ .guest_default_memory_order = 0,
.initialize = ppc_translate_init,
.translate_code = ppc_translate_code,
.restore_state_to_opc = ppc_restore_state_to_opc,
diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
index ded2d68ad78..50e81b2e521 100644
--- a/target/riscv/tcg/tcg-cpu.c
+++ b/target/riscv/tcg/tcg-cpu.c
@@ -140,7 +140,7 @@ static void riscv_restore_state_to_opc(CPUState *cs,
}
static const TCGCPUOps riscv_tcg_ops = {
- .guest_default_memory_order = TCG_GUEST_DEFAULT_MO,
+ .guest_default_memory_order = 0,
.initialize = riscv_translate_init,
.translate_code = riscv_translate_code,
diff --git a/target/rx/cpu.c b/target/rx/cpu.c
index d7eac551fd4..f073fe8fc98 100644
--- a/target/rx/cpu.c
+++ b/target/rx/cpu.c
@@ -204,7 +204,8 @@ static const struct SysemuCPUOps rx_sysemu_ops = {
#include "accel/tcg/cpu-ops.h"
static const TCGCPUOps rx_tcg_ops = {
- .guest_default_memory_order = TCG_GUEST_DEFAULT_MO,
+ /* MTTCG not yet supported: require strict ordering */
+ .guest_default_memory_order = TCG_MO_ALL,
.initialize = rx_translate_init,
.translate_code = rx_translate_code,
diff --git a/target/s390x/cpu.c b/target/s390x/cpu.c
index f232d82fa34..1e101b5afeb 100644
--- a/target/s390x/cpu.c
+++ b/target/s390x/cpu.c
@@ -345,7 +345,11 @@ void cpu_get_tb_cpu_state(CPUS390XState *env, vaddr *pc,
}
static const TCGCPUOps s390_tcg_ops = {
- .guest_default_memory_order = TCG_GUEST_DEFAULT_MO,
+ /*
+ * The z/Architecture has a strong memory model with some
+ * store-after-load re-ordering.
+ */
+ .guest_default_memory_order = TCG_MO_ALL & ~TCG_MO_ST_LD,
.initialize = s390x_translate_init,
.translate_code = s390x_translate_code,
diff --git a/target/sh4/cpu.c b/target/sh4/cpu.c
index 29f4be7ba9c..7a05301c6ff 100644
--- a/target/sh4/cpu.c
+++ b/target/sh4/cpu.c
@@ -262,7 +262,8 @@ static const struct SysemuCPUOps sh4_sysemu_ops = {
#include "accel/tcg/cpu-ops.h"
static const TCGCPUOps superh_tcg_ops = {
- .guest_default_memory_order = TCG_GUEST_DEFAULT_MO,
+ /* MTTCG not yet supported: require strict ordering */
+ .guest_default_memory_order = TCG_MO_ALL,
.initialize = sh4_translate_init,
.translate_code = sh4_translate_code,
diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c
index ef04efcb183..56d9417ae3f 100644
--- a/target/sparc/cpu.c
+++ b/target/sparc/cpu.c
@@ -1001,7 +1001,28 @@ static const struct SysemuCPUOps sparc_sysemu_ops = {
#include "accel/tcg/cpu-ops.h"
static const TCGCPUOps sparc_tcg_ops = {
- .guest_default_memory_order = TCG_GUEST_DEFAULT_MO,
+ /*
+ * From Oracle SPARC Architecture 2015:
+ *
+ * Compatibility notes: The PSO memory model described in SPARC V8 and
+ * SPARC V9 compatibility architecture specifications was never
+ * implemented in a SPARC V9 implementation and is not included in the
+ * Oracle SPARC Architecture specification.
+ *
+ * The RMO memory model described in the SPARC V9 specification was
+ * implemented in some non-Sun SPARC V9 implementations, but is not
+ * directly supported in Oracle SPARC Architecture 2015 implementations.
+ *
+ * Therefore always use TSO in QEMU.
+ *
+ * D.5 Specification of Partial Store Order (PSO)
+ * ... [loads] are followed by an implied MEMBAR #LoadLoad | #LoadStore.
+ *
+ * D.6 Specification of Total Store Order (TSO)
+ * ... PSO with the additional requirement that all [stores] are followed
+ * by an implied MEMBAR #StoreStore.
+ */
+ .guest_default_memory_order = TCG_MO_LD_LD | TCG_MO_LD_ST | TCG_MO_ST_ST,
.initialize = sparc_tcg_init,
.translate_code = sparc_translate_code,
diff --git a/target/tricore/cpu.c b/target/tricore/cpu.c
index 3bf399335ac..c68954b4096 100644
--- a/target/tricore/cpu.c
+++ b/target/tricore/cpu.c
@@ -172,7 +172,8 @@ static const struct SysemuCPUOps tricore_sysemu_ops = {
#include "accel/tcg/cpu-ops.h"
static const TCGCPUOps tricore_tcg_ops = {
- .guest_default_memory_order = TCG_GUEST_DEFAULT_MO,
+ /* MTTCG not yet supported: require strict ordering */
+ .guest_default_memory_order = TCG_MO_ALL,
.initialize = tricore_tcg_init,
.translate_code = tricore_translate_code,
.synchronize_from_tb = tricore_cpu_synchronize_from_tb,
diff --git a/target/xtensa/cpu.c b/target/xtensa/cpu.c
index 23471064957..2cbf4e30108 100644
--- a/target/xtensa/cpu.c
+++ b/target/xtensa/cpu.c
@@ -232,7 +232,8 @@ static const struct SysemuCPUOps xtensa_sysemu_ops = {
#include "accel/tcg/cpu-ops.h"
static const TCGCPUOps xtensa_tcg_ops = {
- .guest_default_memory_order = TCG_GUEST_DEFAULT_MO,
+ /* Xtensa processors have a weak memory model */
+ .guest_default_memory_order = 0,
.initialize = xtensa_translate_init,
.translate_code = xtensa_translate_code,
--
2.47.1
^ permalink raw reply related [flat|nested] 23+ messages in thread* Re: [PATCH-for-10.1 v3 14/19] tcg: Remove the TCG_GUEST_DEFAULT_MO definition globally
2025-04-03 22:04 ` [PATCH-for-10.1 v3 14/19] tcg: Remove the TCG_GUEST_DEFAULT_MO definition globally Philippe Mathieu-Daudé
@ 2025-04-04 23:48 ` Philippe Mathieu-Daudé
0 siblings, 0 replies; 23+ messages in thread
From: Philippe Mathieu-Daudé @ 2025-04-04 23:48 UTC (permalink / raw)
To: Richard Henderson; +Cc: Pierrick Bouvier, qemu-devel
Hi Richard,
On 4/4/25 00:04, Philippe Mathieu-Daudé wrote:
> By directly using TCGCPUOps::guest_default_memory_order,
> we don't need the TCG_GUEST_DEFAULT_MO definition anymore.
>
> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
> Reviewed-by: Anton Johansson <anjo@rev.ng>
> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
> ---
> docs/devel/multi-thread-tcg.rst | 4 ++--
> target/alpha/cpu-param.h | 3 ---
> target/arm/cpu-param.h | 3 ---
> target/avr/cpu-param.h | 2 --
> target/hexagon/cpu-param.h | 3 ---
> target/hppa/cpu-param.h | 8 --------
> target/i386/cpu-param.h | 3 ---
> target/loongarch/cpu-param.h | 2 --
> target/m68k/cpu-param.h | 3 ---
> target/microblaze/cpu-param.h | 3 ---
> target/mips/cpu-param.h | 2 --
> target/openrisc/cpu-param.h | 2 --
> target/ppc/cpu-param.h | 2 --
> target/riscv/cpu-param.h | 2 --
> target/rx/cpu-param.h | 3 ---
> target/s390x/cpu-param.h | 6 ------
> target/sh4/cpu-param.h | 3 ---
> target/sparc/cpu-param.h | 23 -----------------------
> target/tricore/cpu-param.h | 3 ---
> target/xtensa/cpu-param.h | 3 ---
> target/alpha/cpu.c | 3 ++-
> target/arm/cpu.c | 3 ++-
> target/arm/tcg/cpu-v7m.c | 3 ++-
> target/avr/cpu.c | 2 +-
> target/hexagon/cpu.c | 3 ++-
> target/hppa/cpu.c | 8 +++++++-
> target/i386/tcg/tcg-cpu.c | 5 ++++-
> target/loongarch/cpu.c | 2 +-
> target/m68k/cpu.c | 3 ++-
> target/microblaze/cpu.c | 3 ++-
> target/mips/cpu.c | 2 +-
> target/openrisc/cpu.c | 2 +-
> target/ppc/cpu_init.c | 2 +-
> target/riscv/tcg/tcg-cpu.c | 2 +-
> target/rx/cpu.c | 3 ++-
> target/s390x/cpu.c | 6 +++++-
> target/sh4/cpu.c | 3 ++-
> target/sparc/cpu.c | 23 ++++++++++++++++++++++-
> target/tricore/cpu.c | 3 ++-
> target/xtensa/cpu.c | 3 ++-
> 40 files changed, 66 insertions(+), 101 deletions(-)
I forgot this:
-- >8 --
diff --git a/include/exec/poison.h b/include/exec/poison.h
index bc422719d80..413dfd16f24 100644
--- a/include/exec/poison.h
+++ b/include/exec/poison.h
@@ -38,3 +38,2 @@
#pragma GCC poison TARGET_BIG_ENDIAN
-#pragma GCC poison TCG_GUEST_DEFAULT_MO
#pragma GCC poison TARGET_HAS_PRECISE_SMC
---
Could you squash it in your tcg-next tree?
Thanks,
Phil.
^ permalink raw reply related [flat|nested] 23+ messages in thread
* [PATCH-for-10.1 v3 15/19] tcg: Move cpu_req_mo() macro to target-agnostic 'backend-ldst.h'
2025-04-03 22:04 [PATCH-for-10.1 v3 00/19] tcg: philmd's queue Philippe Mathieu-Daudé
` (13 preceding siblings ...)
2025-04-03 22:04 ` [PATCH-for-10.1 v3 14/19] tcg: Remove the TCG_GUEST_DEFAULT_MO definition globally Philippe Mathieu-Daudé
@ 2025-04-03 22:04 ` Philippe Mathieu-Daudé
2025-04-03 22:04 ` [PATCH-for-10.1 v3 16/19] tcg: Move qemu_tcg_mttcg_enabled() to 'system/tcg.h' Philippe Mathieu-Daudé
` (3 subsequent siblings)
18 siblings, 0 replies; 23+ messages in thread
From: Philippe Mathieu-Daudé @ 2025-04-03 22:04 UTC (permalink / raw)
To: qemu-devel; +Cc: Richard Henderson, Pierrick Bouvier
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
accel/tcg/backend-ldst.h | 41 +++++++++++++++++++++++++++++++++++++
accel/tcg/internal-target.h | 28 -------------------------
accel/tcg/cputlb.c | 1 +
accel/tcg/user-exec.c | 1 +
4 files changed, 43 insertions(+), 28 deletions(-)
create mode 100644 accel/tcg/backend-ldst.h
diff --git a/accel/tcg/backend-ldst.h b/accel/tcg/backend-ldst.h
new file mode 100644
index 00000000000..9c3a407a5af
--- /dev/null
+++ b/accel/tcg/backend-ldst.h
@@ -0,0 +1,41 @@
+/*
+ * Internal memory barrier helpers for QEMU (target agnostic)
+ *
+ * Copyright (c) 2003 Fabrice Bellard
+ *
+ * SPDX-License-Identifier: LGPL-2.1-or-later
+ */
+
+#ifndef ACCEL_TCG_BACKEND_LDST_H
+#define ACCEL_TCG_BACKEND_LDST_H
+
+#include "tcg-target-mo.h"
+
+/**
+ * tcg_req_mo:
+ * @guest_mo: Guest default memory order
+ * @type: TCGBar
+ *
+ * Filter @type to the barrier that is required for the guest
+ * memory ordering vs the host memory ordering. A non-zero
+ * result indicates that some barrier is required.
+ */
+#define tcg_req_mo(guest_mo, type) \
+ ((type) & guest_mo & ~TCG_TARGET_DEFAULT_MO)
+
+/**
+ * cpu_req_mo:
+ * @cpu: CPUState
+ * @type: TCGBar
+ *
+ * If tcg_req_mo indicates a barrier for @type is required
+ * for the guest memory model, issue a host memory barrier.
+ */
+#define cpu_req_mo(cpu, type) \
+ do { \
+ if (tcg_req_mo(cpu->cc->tcg_ops->guest_default_memory_order, type)) { \
+ smp_mb(); \
+ } \
+ } while (0)
+
+#endif
diff --git a/accel/tcg/internal-target.h b/accel/tcg/internal-target.h
index f5a3fd7e402..9a9cef31406 100644
--- a/accel/tcg/internal-target.h
+++ b/accel/tcg/internal-target.h
@@ -13,7 +13,6 @@
#include "exec/exec-all.h"
#include "exec/translation-block.h"
#include "tb-internal.h"
-#include "tcg-target-mo.h"
#include "exec/mmap-lock.h"
/*
@@ -44,31 +43,4 @@ void page_table_config_init(void);
G_NORETURN void cpu_io_recompile(CPUState *cpu, uintptr_t retaddr);
#endif /* CONFIG_USER_ONLY */
-/**
- * tcg_req_mo:
- * @guest_mo: Guest default memory order
- * @type: TCGBar
- *
- * Filter @type to the barrier that is required for the guest
- * memory ordering vs the host memory ordering. A non-zero
- * result indicates that some barrier is required.
- */
-#define tcg_req_mo(guest_mo, type) \
- ((type) & guest_mo & ~TCG_TARGET_DEFAULT_MO)
-
-/**
- * cpu_req_mo:
- * @cpu: CPUState
- * @type: TCGBar
- *
- * If tcg_req_mo indicates a barrier for @type is required
- * for the guest memory model, issue a host memory barrier.
- */
-#define cpu_req_mo(cpu, type) \
- do { \
- if (tcg_req_mo(cpu->cc->tcg_ops->guest_default_memory_order, type)) { \
- smp_mb(); \
- } \
- } while (0)
-
#endif /* ACCEL_TCG_INTERNAL_H */
diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c
index 35b1ff03a51..d9fb68d7198 100644
--- a/accel/tcg/cputlb.c
+++ b/accel/tcg/cputlb.c
@@ -48,6 +48,7 @@
#include "qemu/plugin-memory.h"
#endif
#include "tcg/tcg-ldst.h"
+#include "backend-ldst.h"
/* DEBUG defines, enable DEBUG_TLB_LOG to log to the CPU_LOG_MMU target */
diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c
index 3f4d6824460..5eef8e7f186 100644
--- a/accel/tcg/user-exec.c
+++ b/accel/tcg/user-exec.c
@@ -37,6 +37,7 @@
#include "qemu/int128.h"
#include "trace.h"
#include "tcg/tcg-ldst.h"
+#include "backend-ldst.h"
#include "internal-common.h"
#include "internal-target.h"
#include "tb-internal.h"
--
2.47.1
^ permalink raw reply related [flat|nested] 23+ messages in thread* [PATCH-for-10.1 v3 16/19] tcg: Move qemu_tcg_mttcg_enabled() to 'system/tcg.h'
2025-04-03 22:04 [PATCH-for-10.1 v3 00/19] tcg: philmd's queue Philippe Mathieu-Daudé
` (14 preceding siblings ...)
2025-04-03 22:04 ` [PATCH-for-10.1 v3 15/19] tcg: Move cpu_req_mo() macro to target-agnostic 'backend-ldst.h' Philippe Mathieu-Daudé
@ 2025-04-03 22:04 ` Philippe Mathieu-Daudé
2025-04-03 22:04 ` [PATCH-for-10.1 v3 17/19] tcg: Convert TCGState::mttcg_enabled to TriState Philippe Mathieu-Daudé
` (2 subsequent siblings)
18 siblings, 0 replies; 23+ messages in thread
From: Philippe Mathieu-Daudé @ 2025-04-03 22:04 UTC (permalink / raw)
To: qemu-devel; +Cc: Richard Henderson, Pierrick Bouvier
qemu_tcg_mttcg_enabled() is specific to 1/ TCG and
2/ system emulation. Move the prototype declaration
to "system/tcg.h", reducing 'mttcg_enabled' variable
scope.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
include/hw/core/cpu.h | 9 ---------
include/system/tcg.h | 8 ++++++++
accel/tcg/tcg-all.c | 16 ++++++++++++++--
target/riscv/tcg/tcg-cpu.c | 1 +
tcg/region.c | 4 +++-
5 files changed, 26 insertions(+), 12 deletions(-)
diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h
index 10b6b25b344..c8d6abff19a 100644
--- a/include/hw/core/cpu.h
+++ b/include/hw/core/cpu.h
@@ -594,15 +594,6 @@ extern CPUTailQ cpus_queue;
extern __thread CPUState *current_cpu;
-/**
- * qemu_tcg_mttcg_enabled:
- * Check whether we are running MultiThread TCG or not.
- *
- * Returns: %true if we are in MTTCG mode %false otherwise.
- */
-extern bool mttcg_enabled;
-#define qemu_tcg_mttcg_enabled() (mttcg_enabled)
-
/**
* cpu_paging_enabled:
* @cpu: The CPU whose state is to be inspected.
diff --git a/include/system/tcg.h b/include/system/tcg.h
index 73229648c63..7622dcea302 100644
--- a/include/system/tcg.h
+++ b/include/system/tcg.h
@@ -17,4 +17,12 @@ extern bool tcg_allowed;
#define tcg_enabled() 0
#endif
+/**
+ * qemu_tcg_mttcg_enabled:
+ * Check whether we are running MultiThread TCG or not.
+ *
+ * Returns: %true if we are in MTTCG mode %false otherwise.
+ */
+bool qemu_tcg_mttcg_enabled(void);
+
#endif
diff --git a/accel/tcg/tcg-all.c b/accel/tcg/tcg-all.c
index a5a1fd6a11e..b8874430d30 100644
--- a/accel/tcg/tcg-all.c
+++ b/accel/tcg/tcg-all.c
@@ -38,6 +38,7 @@
#include "hw/qdev-core.h"
#else
#include "hw/boards.h"
+#include "system/tcg.h"
#endif
#include "internal-common.h"
#include "cpu-param.h"
@@ -58,6 +59,17 @@ typedef struct TCGState TCGState;
DECLARE_INSTANCE_CHECKER(TCGState, TCG_STATE,
TYPE_TCG_ACCEL)
+#ifndef CONFIG_USER_ONLY
+
+static bool mttcg_enabled;
+
+bool qemu_tcg_mttcg_enabled(void)
+{
+ return mttcg_enabled;
+}
+
+#endif /* !CONFIG_USER_ONLY */
+
/*
* We default to false if we know other options have been enabled
* which are currently incompatible with MTTCG. Otherwise when each
@@ -97,7 +109,6 @@ static void tcg_accel_instance_init(Object *obj)
#endif
}
-bool mttcg_enabled;
bool one_insn_per_tb;
static int tcg_init_machine(MachineState *ms)
@@ -107,10 +118,11 @@ static int tcg_init_machine(MachineState *ms)
unsigned max_cpus = 1;
#else
unsigned max_cpus = ms->smp.max_cpus;
+
+ mttcg_enabled = s->mttcg_enabled;
#endif
tcg_allowed = true;
- mttcg_enabled = s->mttcg_enabled;
page_init();
tb_htable_init();
diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
index 50e81b2e521..88f7cdb887c 100644
--- a/target/riscv/tcg/tcg-cpu.c
+++ b/target/riscv/tcg/tcg-cpu.c
@@ -36,6 +36,7 @@
#include "tcg/tcg.h"
#ifndef CONFIG_USER_ONLY
#include "hw/boards.h"
+#include "system/tcg.h"
#endif
/* Hash that stores user set extensions */
diff --git a/tcg/region.c b/tcg/region.c
index 478ec051c4b..56d2e988719 100644
--- a/tcg/region.c
+++ b/tcg/region.c
@@ -34,7 +34,9 @@
#include "exec/translation-block.h"
#include "tcg-internal.h"
#include "host/cpuinfo.h"
-
+#ifndef CONFIG_USER_ONLY
+#include "system/tcg.h"
+#endif
/*
* Local source-level compatibility with Unix.
--
2.47.1
^ permalink raw reply related [flat|nested] 23+ messages in thread* [PATCH-for-10.1 v3 17/19] tcg: Convert TCGState::mttcg_enabled to TriState
2025-04-03 22:04 [PATCH-for-10.1 v3 00/19] tcg: philmd's queue Philippe Mathieu-Daudé
` (15 preceding siblings ...)
2025-04-03 22:04 ` [PATCH-for-10.1 v3 16/19] tcg: Move qemu_tcg_mttcg_enabled() to 'system/tcg.h' Philippe Mathieu-Daudé
@ 2025-04-03 22:04 ` Philippe Mathieu-Daudé
2025-04-03 22:04 ` [PATCH-for-10.1 v3 18/19] tcg: Factor mttcg_init() out Philippe Mathieu-Daudé
2025-04-03 22:04 ` [PATCH-for-10.1 v3 19/19] tcg: Convert TARGET_SUPPORTS_MTTCG to TCGCPUOps::mttcg_supported field Philippe Mathieu-Daudé
18 siblings, 0 replies; 23+ messages in thread
From: Philippe Mathieu-Daudé @ 2025-04-03 22:04 UTC (permalink / raw)
To: qemu-devel; +Cc: Richard Henderson, Pierrick Bouvier
Use the OnOffAuto type as 3-state.
Since the TCGState instance is zero-initialized, the
mttcg_enabled is initialzed as AUTO (ON_OFF_AUTO_AUTO).
In tcg_init_machine(), if mttcg_enabled is still AUTO,
set a default value (effectively inlining the
default_mttcg_enabled() method content).
In the tcg_get_thread() getter, consider AUTO / OFF states
as "single", otherwise ON is "multi".
Reviewed-by: Anton Johansson <anjo@rev.ng>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
accel/tcg/tcg-all.c | 60 ++++++++++++++++++++++-----------------------
1 file changed, 29 insertions(+), 31 deletions(-)
diff --git a/accel/tcg/tcg-all.c b/accel/tcg/tcg-all.c
index b8874430d30..15d4e9232ae 100644
--- a/accel/tcg/tcg-all.c
+++ b/accel/tcg/tcg-all.c
@@ -32,6 +32,7 @@
#include "qemu/error-report.h"
#include "qemu/accel.h"
#include "qemu/atomic.h"
+#include "qapi/qapi-types-common.h"
#include "qapi/qapi-builtin-visit.h"
#include "qemu/units.h"
#if defined(CONFIG_USER_ONLY)
@@ -47,7 +48,7 @@
struct TCGState {
AccelState parent_obj;
- bool mttcg_enabled;
+ OnOffAuto mttcg_enabled;
bool one_insn_per_tb;
int splitwx_enabled;
unsigned long tb_size;
@@ -70,37 +71,10 @@ bool qemu_tcg_mttcg_enabled(void)
#endif /* !CONFIG_USER_ONLY */
-/*
- * We default to false if we know other options have been enabled
- * which are currently incompatible with MTTCG. Otherwise when each
- * guest (target) has been updated to support:
- * - atomic instructions
- * - memory ordering primitives (barriers)
- * they can set the appropriate CONFIG flags in ${target}-softmmu.mak
- *
- * Once a guest architecture has been converted to the new primitives
- * there is one remaining limitation to check:
- * - The guest can't be oversized (e.g. 64 bit guest on 32 bit host)
- */
-
-static bool default_mttcg_enabled(void)
-{
- if (icount_enabled()) {
- return false;
- }
-#ifdef TARGET_SUPPORTS_MTTCG
- return true;
-#else
- return false;
-#endif
-}
-
static void tcg_accel_instance_init(Object *obj)
{
TCGState *s = TCG_STATE(obj);
- s->mttcg_enabled = default_mttcg_enabled();
-
/* If debugging enabled, default "auto on", otherwise off. */
#if defined(CONFIG_DEBUG_TCG) && !defined(CONFIG_USER_ONLY)
s->splitwx_enabled = -1;
@@ -118,7 +92,31 @@ static int tcg_init_machine(MachineState *ms)
unsigned max_cpus = 1;
#else
unsigned max_cpus = ms->smp.max_cpus;
+#ifdef TARGET_SUPPORTS_MTTCG
+ bool mttcg_supported = true;
+#else
+ bool mttcg_supported = false;
+#endif
+ if (s->mttcg_enabled == ON_OFF_AUTO_AUTO) {
+ /*
+ * We default to false if we know other options have been enabled
+ * which are currently incompatible with MTTCG. Otherwise when each
+ * guest (target) has been updated to support:
+ * - atomic instructions
+ * - memory ordering primitives (barriers)
+ * they can set the appropriate CONFIG flags in ${target}-softmmu.mak
+ *
+ * Once a guest architecture has been converted to the new primitives
+ * there is one remaining limitation to check:
+ * - The guest can't be oversized (e.g. 64 bit guest on 32 bit host)
+ */
+ if (icount_enabled()) {
+ s->mttcg_enabled = ON_OFF_AUTO_OFF;
+ } else {
+ s->mttcg_enabled = mttcg_supported;
+ }
+ }
mttcg_enabled = s->mttcg_enabled;
#endif
@@ -147,7 +145,7 @@ static char *tcg_get_thread(Object *obj, Error **errp)
{
TCGState *s = TCG_STATE(obj);
- return g_strdup(s->mttcg_enabled ? "multi" : "single");
+ return g_strdup(s->mttcg_enabled == ON_OFF_AUTO_ON ? "multi" : "single");
}
static void tcg_set_thread(Object *obj, const char *value, Error **errp)
@@ -162,10 +160,10 @@ static void tcg_set_thread(Object *obj, const char *value, Error **errp)
warn_report("Guest not yet converted to MTTCG - "
"you may get unexpected results");
#endif
- s->mttcg_enabled = true;
+ s->mttcg_enabled = ON_OFF_AUTO_ON;
}
} else if (strcmp(value, "single") == 0) {
- s->mttcg_enabled = false;
+ s->mttcg_enabled = ON_OFF_AUTO_OFF;
} else {
error_setg(errp, "Invalid 'thread' setting %s", value);
}
--
2.47.1
^ permalink raw reply related [flat|nested] 23+ messages in thread* [PATCH-for-10.1 v3 18/19] tcg: Factor mttcg_init() out
2025-04-03 22:04 [PATCH-for-10.1 v3 00/19] tcg: philmd's queue Philippe Mathieu-Daudé
` (16 preceding siblings ...)
2025-04-03 22:04 ` [PATCH-for-10.1 v3 17/19] tcg: Convert TCGState::mttcg_enabled to TriState Philippe Mathieu-Daudé
@ 2025-04-03 22:04 ` Philippe Mathieu-Daudé
2025-04-03 22:04 ` [PATCH-for-10.1 v3 19/19] tcg: Convert TARGET_SUPPORTS_MTTCG to TCGCPUOps::mttcg_supported field Philippe Mathieu-Daudé
18 siblings, 0 replies; 23+ messages in thread
From: Philippe Mathieu-Daudé @ 2025-04-03 22:04 UTC (permalink / raw)
To: qemu-devel; +Cc: Richard Henderson, Pierrick Bouvier
Keep MTTCG initialization code out of tcg_init_machine().
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
accel/tcg/tcg-all.c | 50 +++++++++++++++++++++++++--------------------
1 file changed, 28 insertions(+), 22 deletions(-)
diff --git a/accel/tcg/tcg-all.c b/accel/tcg/tcg-all.c
index 15d4e9232ae..267830658ca 100644
--- a/accel/tcg/tcg-all.c
+++ b/accel/tcg/tcg-all.c
@@ -69,29 +69,8 @@ bool qemu_tcg_mttcg_enabled(void)
return mttcg_enabled;
}
-#endif /* !CONFIG_USER_ONLY */
-
-static void tcg_accel_instance_init(Object *obj)
+static void mttcg_init(TCGState *s)
{
- TCGState *s = TCG_STATE(obj);
-
- /* If debugging enabled, default "auto on", otherwise off. */
-#if defined(CONFIG_DEBUG_TCG) && !defined(CONFIG_USER_ONLY)
- s->splitwx_enabled = -1;
-#else
- s->splitwx_enabled = 0;
-#endif
-}
-
-bool one_insn_per_tb;
-
-static int tcg_init_machine(MachineState *ms)
-{
- TCGState *s = TCG_STATE(current_accel());
-#ifdef CONFIG_USER_ONLY
- unsigned max_cpus = 1;
-#else
- unsigned max_cpus = ms->smp.max_cpus;
#ifdef TARGET_SUPPORTS_MTTCG
bool mttcg_supported = true;
#else
@@ -118,6 +97,33 @@ static int tcg_init_machine(MachineState *ms)
}
}
mttcg_enabled = s->mttcg_enabled;
+}
+
+#endif /* !CONFIG_USER_ONLY */
+
+static void tcg_accel_instance_init(Object *obj)
+{
+ TCGState *s = TCG_STATE(obj);
+
+ /* If debugging enabled, default "auto on", otherwise off. */
+#if defined(CONFIG_DEBUG_TCG) && !defined(CONFIG_USER_ONLY)
+ s->splitwx_enabled = -1;
+#else
+ s->splitwx_enabled = 0;
+#endif
+}
+
+bool one_insn_per_tb;
+
+static int tcg_init_machine(MachineState *ms)
+{
+ TCGState *s = TCG_STATE(current_accel());
+#ifdef CONFIG_USER_ONLY
+ unsigned max_cpus = 1;
+#else
+ unsigned max_cpus = ms->smp.max_cpus;
+
+ mttcg_init(s);
#endif
tcg_allowed = true;
--
2.47.1
^ permalink raw reply related [flat|nested] 23+ messages in thread* [PATCH-for-10.1 v3 19/19] tcg: Convert TARGET_SUPPORTS_MTTCG to TCGCPUOps::mttcg_supported field
2025-04-03 22:04 [PATCH-for-10.1 v3 00/19] tcg: philmd's queue Philippe Mathieu-Daudé
` (17 preceding siblings ...)
2025-04-03 22:04 ` [PATCH-for-10.1 v3 18/19] tcg: Factor mttcg_init() out Philippe Mathieu-Daudé
@ 2025-04-03 22:04 ` Philippe Mathieu-Daudé
2025-04-05 11:29 ` Richard Henderson
18 siblings, 1 reply; 23+ messages in thread
From: Philippe Mathieu-Daudé @ 2025-04-03 22:04 UTC (permalink / raw)
To: qemu-devel; +Cc: Richard Henderson, Pierrick Bouvier
Instead of having a compile-time TARGET_SUPPORTS_MTTCG definition,
have each target set the 'mttcg_supported' field in the TCGCPUOps
structure.
Since so far we only emulate one target architecture at a time,
tcg_init_machine() gets whether MTTCG is supported via the
current CPU class (CPU_RESOLVING_TYPE).
Since TARGET_SUPPORTS_MTTCG isn't available anymore,
instead of emiting a warning when the 'thread' property
is set in tcg_set_thread(), emit it in tcg_init_machine()
where it is consumed.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Anton Johansson <anjo@rev.ng>
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
docs/devel/multi-thread-tcg.rst | 2 +-
configs/targets/aarch64-softmmu.mak | 1 -
configs/targets/alpha-softmmu.mak | 1 -
configs/targets/arm-softmmu.mak | 1 -
configs/targets/hppa-softmmu.mak | 1 -
configs/targets/i386-softmmu.mak | 1 -
configs/targets/loongarch64-softmmu.mak | 1 -
configs/targets/microblaze-softmmu.mak | 1 -
configs/targets/microblazeel-softmmu.mak | 1 -
configs/targets/mips-softmmu.mak | 1 -
configs/targets/mipsel-softmmu.mak | 1 -
configs/targets/or1k-softmmu.mak | 1 -
configs/targets/ppc64-softmmu.mak | 1 -
configs/targets/riscv32-softmmu.mak | 1 -
configs/targets/riscv64-softmmu.mak | 1 -
configs/targets/s390x-softmmu.mak | 1 -
configs/targets/sparc-softmmu.mak | 1 -
configs/targets/sparc64-softmmu.mak | 1 -
configs/targets/x86_64-softmmu.mak | 1 -
configs/targets/xtensa-softmmu.mak | 1 -
configs/targets/xtensaeb-softmmu.mak | 1 -
include/accel/tcg/cpu-ops.h | 8 ++++++++
include/exec/poison.h | 1 -
accel/tcg/tcg-all.c | 17 ++++++++---------
target/alpha/cpu.c | 1 +
target/arm/cpu.c | 1 +
target/arm/tcg/cpu-v7m.c | 1 +
target/avr/cpu.c | 1 +
target/hexagon/cpu.c | 1 +
target/hppa/cpu.c | 1 +
target/i386/tcg/tcg-cpu.c | 1 +
target/loongarch/cpu.c | 1 +
target/m68k/cpu.c | 1 +
target/microblaze/cpu.c | 1 +
target/mips/cpu.c | 1 +
target/openrisc/cpu.c | 1 +
target/ppc/cpu_init.c | 1 +
target/riscv/tcg/tcg-cpu.c | 1 +
target/rx/cpu.c | 1 +
target/s390x/cpu.c | 1 +
target/sh4/cpu.c | 1 +
target/sparc/cpu.c | 1 +
target/tricore/cpu.c | 1 +
target/xtensa/cpu.c | 1 +
44 files changed, 37 insertions(+), 31 deletions(-)
diff --git a/docs/devel/multi-thread-tcg.rst b/docs/devel/multi-thread-tcg.rst
index 14a2a9dc7b5..da9a1530c9f 100644
--- a/docs/devel/multi-thread-tcg.rst
+++ b/docs/devel/multi-thread-tcg.rst
@@ -30,7 +30,7 @@ user-space thread. This is enabled by default for all FE/BE
combinations where the host memory model is able to accommodate the
guest (TCGCPUOps::guest_default_memory_order & ~TCG_TARGET_DEFAULT_MO is zero)
and the guest has had the required work done to support this safely
-(TARGET_SUPPORTS_MTTCG).
+(TCGCPUOps::mttcg_supported).
System emulation will fall back to the original round robin approach
if:
diff --git a/configs/targets/aarch64-softmmu.mak b/configs/targets/aarch64-softmmu.mak
index 82cb72cb83d..5dfeb35af90 100644
--- a/configs/targets/aarch64-softmmu.mak
+++ b/configs/targets/aarch64-softmmu.mak
@@ -1,6 +1,5 @@
TARGET_ARCH=aarch64
TARGET_BASE_ARCH=arm
-TARGET_SUPPORTS_MTTCG=y
TARGET_KVM_HAVE_GUEST_DEBUG=y
TARGET_XML_FILES= gdb-xml/aarch64-core.xml gdb-xml/aarch64-fpu.xml gdb-xml/arm-core.xml gdb-xml/arm-vfp.xml gdb-xml/arm-vfp3.xml gdb-xml/arm-vfp-sysregs.xml gdb-xml/arm-neon.xml gdb-xml/arm-m-profile.xml gdb-xml/arm-m-profile-mve.xml gdb-xml/aarch64-pauth.xml
# needed by boot.c
diff --git a/configs/targets/alpha-softmmu.mak b/configs/targets/alpha-softmmu.mak
index 89f3517aca0..5275076e50d 100644
--- a/configs/targets/alpha-softmmu.mak
+++ b/configs/targets/alpha-softmmu.mak
@@ -1,3 +1,2 @@
TARGET_ARCH=alpha
-TARGET_SUPPORTS_MTTCG=y
TARGET_LONG_BITS=64
diff --git a/configs/targets/arm-softmmu.mak b/configs/targets/arm-softmmu.mak
index afc64f5927b..6a5a8eda949 100644
--- a/configs/targets/arm-softmmu.mak
+++ b/configs/targets/arm-softmmu.mak
@@ -1,5 +1,4 @@
TARGET_ARCH=arm
-TARGET_SUPPORTS_MTTCG=y
TARGET_XML_FILES= gdb-xml/arm-core.xml gdb-xml/arm-vfp.xml gdb-xml/arm-vfp3.xml gdb-xml/arm-vfp-sysregs.xml gdb-xml/arm-neon.xml gdb-xml/arm-m-profile.xml gdb-xml/arm-m-profile-mve.xml
# needed by boot.c
TARGET_NEED_FDT=y
diff --git a/configs/targets/hppa-softmmu.mak b/configs/targets/hppa-softmmu.mak
index 63ca74ed5e6..ea331107a08 100644
--- a/configs/targets/hppa-softmmu.mak
+++ b/configs/targets/hppa-softmmu.mak
@@ -1,4 +1,3 @@
TARGET_ARCH=hppa
TARGET_BIG_ENDIAN=y
-TARGET_SUPPORTS_MTTCG=y
TARGET_LONG_BITS=64
diff --git a/configs/targets/i386-softmmu.mak b/configs/targets/i386-softmmu.mak
index 5dd89217560..e9d89e8ab41 100644
--- a/configs/targets/i386-softmmu.mak
+++ b/configs/targets/i386-softmmu.mak
@@ -1,5 +1,4 @@
TARGET_ARCH=i386
-TARGET_SUPPORTS_MTTCG=y
TARGET_KVM_HAVE_GUEST_DEBUG=y
TARGET_KVM_HAVE_RESET_PARKED_VCPU=y
TARGET_XML_FILES= gdb-xml/i386-32bit.xml
diff --git a/configs/targets/loongarch64-softmmu.mak b/configs/targets/loongarch64-softmmu.mak
index 351341132f6..fc44c54233d 100644
--- a/configs/targets/loongarch64-softmmu.mak
+++ b/configs/targets/loongarch64-softmmu.mak
@@ -1,7 +1,6 @@
TARGET_ARCH=loongarch64
TARGET_BASE_ARCH=loongarch
TARGET_KVM_HAVE_GUEST_DEBUG=y
-TARGET_SUPPORTS_MTTCG=y
TARGET_XML_FILES= gdb-xml/loongarch-base32.xml gdb-xml/loongarch-base64.xml gdb-xml/loongarch-fpu.xml gdb-xml/loongarch-lsx.xml gdb-xml/loongarch-lasx.xml
# all boards require libfdt
TARGET_NEED_FDT=y
diff --git a/configs/targets/microblaze-softmmu.mak b/configs/targets/microblaze-softmmu.mak
index 99a33ed44a8..23457d0ae65 100644
--- a/configs/targets/microblaze-softmmu.mak
+++ b/configs/targets/microblaze-softmmu.mak
@@ -1,6 +1,5 @@
TARGET_ARCH=microblaze
TARGET_BIG_ENDIAN=y
-TARGET_SUPPORTS_MTTCG=y
# needed by boot.c
TARGET_NEED_FDT=y
TARGET_XML_FILES=gdb-xml/microblaze-core.xml gdb-xml/microblaze-stack-protect.xml
diff --git a/configs/targets/microblazeel-softmmu.mak b/configs/targets/microblazeel-softmmu.mak
index 52cdeae1a28..c82c509623d 100644
--- a/configs/targets/microblazeel-softmmu.mak
+++ b/configs/targets/microblazeel-softmmu.mak
@@ -1,5 +1,4 @@
TARGET_ARCH=microblaze
-TARGET_SUPPORTS_MTTCG=y
# needed by boot.c
TARGET_NEED_FDT=y
TARGET_XML_FILES=gdb-xml/microblaze-core.xml gdb-xml/microblaze-stack-protect.xml
diff --git a/configs/targets/mips-softmmu.mak b/configs/targets/mips-softmmu.mak
index b62a0882499..c9588066b8d 100644
--- a/configs/targets/mips-softmmu.mak
+++ b/configs/targets/mips-softmmu.mak
@@ -1,4 +1,3 @@
TARGET_ARCH=mips
TARGET_BIG_ENDIAN=y
-TARGET_SUPPORTS_MTTCG=y
TARGET_LONG_BITS=32
diff --git a/configs/targets/mipsel-softmmu.mak b/configs/targets/mipsel-softmmu.mak
index 620ec681785..90e09bdc3e5 100644
--- a/configs/targets/mipsel-softmmu.mak
+++ b/configs/targets/mipsel-softmmu.mak
@@ -1,3 +1,2 @@
TARGET_ARCH=mips
-TARGET_SUPPORTS_MTTCG=y
TARGET_LONG_BITS=32
diff --git a/configs/targets/or1k-softmmu.mak b/configs/targets/or1k-softmmu.mak
index adfddb1a8ac..0e47d9878b0 100644
--- a/configs/targets/or1k-softmmu.mak
+++ b/configs/targets/or1k-softmmu.mak
@@ -1,5 +1,4 @@
TARGET_ARCH=openrisc
-TARGET_SUPPORTS_MTTCG=y
TARGET_BIG_ENDIAN=y
# needed by boot.c and all boards
TARGET_NEED_FDT=y
diff --git a/configs/targets/ppc64-softmmu.mak b/configs/targets/ppc64-softmmu.mak
index 7cee0e97f43..74572864b36 100644
--- a/configs/targets/ppc64-softmmu.mak
+++ b/configs/targets/ppc64-softmmu.mak
@@ -1,7 +1,6 @@
TARGET_ARCH=ppc64
TARGET_BASE_ARCH=ppc
TARGET_BIG_ENDIAN=y
-TARGET_SUPPORTS_MTTCG=y
TARGET_KVM_HAVE_GUEST_DEBUG=y
TARGET_XML_FILES= gdb-xml/power64-core.xml gdb-xml/power-fpu.xml gdb-xml/power-altivec.xml gdb-xml/power-spe.xml gdb-xml/power-vsx.xml
# all boards require libfdt
diff --git a/configs/targets/riscv32-softmmu.mak b/configs/targets/riscv32-softmmu.mak
index c828066ce6b..db55275b868 100644
--- a/configs/targets/riscv32-softmmu.mak
+++ b/configs/targets/riscv32-softmmu.mak
@@ -1,6 +1,5 @@
TARGET_ARCH=riscv32
TARGET_BASE_ARCH=riscv
-TARGET_SUPPORTS_MTTCG=y
TARGET_XML_FILES= gdb-xml/riscv-32bit-cpu.xml gdb-xml/riscv-32bit-fpu.xml gdb-xml/riscv-64bit-fpu.xml gdb-xml/riscv-32bit-virtual.xml
# needed by boot.c
TARGET_NEED_FDT=y
diff --git a/configs/targets/riscv64-softmmu.mak b/configs/targets/riscv64-softmmu.mak
index 09f613d24a0..2bdd4a62cd2 100644
--- a/configs/targets/riscv64-softmmu.mak
+++ b/configs/targets/riscv64-softmmu.mak
@@ -1,6 +1,5 @@
TARGET_ARCH=riscv64
TARGET_BASE_ARCH=riscv
-TARGET_SUPPORTS_MTTCG=y
TARGET_KVM_HAVE_GUEST_DEBUG=y
TARGET_XML_FILES= gdb-xml/riscv-64bit-cpu.xml gdb-xml/riscv-32bit-fpu.xml gdb-xml/riscv-64bit-fpu.xml gdb-xml/riscv-64bit-virtual.xml gdb-xml/riscv-32bit-cpu.xml gdb-xml/riscv-32bit-virtual.xml
# needed by boot.c
diff --git a/configs/targets/s390x-softmmu.mak b/configs/targets/s390x-softmmu.mak
index 5242ebe7c2e..76dd5de6584 100644
--- a/configs/targets/s390x-softmmu.mak
+++ b/configs/targets/s390x-softmmu.mak
@@ -1,6 +1,5 @@
TARGET_ARCH=s390x
TARGET_BIG_ENDIAN=y
-TARGET_SUPPORTS_MTTCG=y
TARGET_KVM_HAVE_GUEST_DEBUG=y
TARGET_XML_FILES= gdb-xml/s390x-core64.xml gdb-xml/s390-acr.xml gdb-xml/s390-fpr.xml gdb-xml/s390-vx.xml gdb-xml/s390-cr.xml gdb-xml/s390-virt.xml gdb-xml/s390-virt-kvm.xml gdb-xml/s390-gs.xml
TARGET_LONG_BITS=64
diff --git a/configs/targets/sparc-softmmu.mak b/configs/targets/sparc-softmmu.mak
index 78c2e25bd13..57801faf1fc 100644
--- a/configs/targets/sparc-softmmu.mak
+++ b/configs/targets/sparc-softmmu.mak
@@ -1,4 +1,3 @@
TARGET_ARCH=sparc
TARGET_BIG_ENDIAN=y
-TARGET_SUPPORTS_MTTCG=y
TARGET_LONG_BITS=32
diff --git a/configs/targets/sparc64-softmmu.mak b/configs/targets/sparc64-softmmu.mak
index f7bab97a002..2504e31ae33 100644
--- a/configs/targets/sparc64-softmmu.mak
+++ b/configs/targets/sparc64-softmmu.mak
@@ -1,5 +1,4 @@
TARGET_ARCH=sparc64
TARGET_BASE_ARCH=sparc
TARGET_BIG_ENDIAN=y
-TARGET_SUPPORTS_MTTCG=y
TARGET_LONG_BITS=64
diff --git a/configs/targets/x86_64-softmmu.mak b/configs/targets/x86_64-softmmu.mak
index 1ceefde1313..5619b2bc686 100644
--- a/configs/targets/x86_64-softmmu.mak
+++ b/configs/targets/x86_64-softmmu.mak
@@ -1,6 +1,5 @@
TARGET_ARCH=x86_64
TARGET_BASE_ARCH=i386
-TARGET_SUPPORTS_MTTCG=y
TARGET_KVM_HAVE_GUEST_DEBUG=y
TARGET_KVM_HAVE_RESET_PARKED_VCPU=y
TARGET_XML_FILES= gdb-xml/i386-64bit.xml
diff --git a/configs/targets/xtensa-softmmu.mak b/configs/targets/xtensa-softmmu.mak
index 65845df4ffa..2a9797338a6 100644
--- a/configs/targets/xtensa-softmmu.mak
+++ b/configs/targets/xtensa-softmmu.mak
@@ -1,3 +1,2 @@
TARGET_ARCH=xtensa
-TARGET_SUPPORTS_MTTCG=y
TARGET_LONG_BITS=32
diff --git a/configs/targets/xtensaeb-softmmu.mak b/configs/targets/xtensaeb-softmmu.mak
index f1f789d6971..5204729af8b 100644
--- a/configs/targets/xtensaeb-softmmu.mak
+++ b/configs/targets/xtensaeb-softmmu.mak
@@ -1,4 +1,3 @@
TARGET_ARCH=xtensa
TARGET_BIG_ENDIAN=y
-TARGET_SUPPORTS_MTTCG=y
TARGET_LONG_BITS=32
diff --git a/include/accel/tcg/cpu-ops.h b/include/accel/tcg/cpu-ops.h
index a4932fc5d7c..0e4352513d1 100644
--- a/include/accel/tcg/cpu-ops.h
+++ b/include/accel/tcg/cpu-ops.h
@@ -19,6 +19,14 @@
#include "tcg/tcg-mo.h"
struct TCGCPUOps {
+ /**
+ * mttcg_supported: multi-threaded TCG is supported
+ *
+ * Target (TCG frontend) supports:
+ * - atomic instructions
+ * - memory ordering primitives (barriers)
+ */
+ bool mttcg_supported;
/**
* @guest_default_memory_order: default barrier that is required
diff --git a/include/exec/poison.h b/include/exec/poison.h
index a09e0c12631..bc422719d80 100644
--- a/include/exec/poison.h
+++ b/include/exec/poison.h
@@ -35,7 +35,6 @@
#pragma GCC poison TARGET_HAS_BFLT
#pragma GCC poison TARGET_NAME
-#pragma GCC poison TARGET_SUPPORTS_MTTCG
#pragma GCC poison TARGET_BIG_ENDIAN
#pragma GCC poison TCG_GUEST_DEFAULT_MO
#pragma GCC poison TARGET_HAS_PRECISE_SMC
diff --git a/accel/tcg/tcg-all.c b/accel/tcg/tcg-all.c
index 267830658ca..bf27c5c0fb3 100644
--- a/accel/tcg/tcg-all.c
+++ b/accel/tcg/tcg-all.c
@@ -41,8 +41,10 @@
#include "hw/boards.h"
#include "system/tcg.h"
#endif
+#include "accel/tcg/cpu-ops.h"
#include "internal-common.h"
#include "cpu-param.h"
+#include "cpu.h"
struct TCGState {
@@ -71,11 +73,8 @@ bool qemu_tcg_mttcg_enabled(void)
static void mttcg_init(TCGState *s)
{
-#ifdef TARGET_SUPPORTS_MTTCG
- bool mttcg_supported = true;
-#else
- bool mttcg_supported = false;
-#endif
+ CPUClass *cc = CPU_CLASS(object_class_by_name(CPU_RESOLVING_TYPE));
+ bool mttcg_supported = cc->tcg_ops->mttcg_supported;
if (s->mttcg_enabled == ON_OFF_AUTO_AUTO) {
/*
@@ -96,6 +95,10 @@ static void mttcg_init(TCGState *s)
s->mttcg_enabled = mttcg_supported;
}
}
+ if (s->mttcg_enabled == ON_OFF_AUTO_ON && !mttcg_supported) {
+ warn_report("Guest not yet converted to MTTCG - "
+ "you may get unexpected results");
+ }
mttcg_enabled = s->mttcg_enabled;
}
@@ -162,10 +165,6 @@ static void tcg_set_thread(Object *obj, const char *value, Error **errp)
if (icount_enabled()) {
error_setg(errp, "No MTTCG when icount is enabled");
} else {
-#ifndef TARGET_SUPPORTS_MTTCG
- warn_report("Guest not yet converted to MTTCG - "
- "you may get unexpected results");
-#endif
s->mttcg_enabled = ON_OFF_AUTO_ON;
}
} else if (strcmp(value, "single") == 0) {
diff --git a/target/alpha/cpu.c b/target/alpha/cpu.c
index eeaf3a81c1a..851a3d10d59 100644
--- a/target/alpha/cpu.c
+++ b/target/alpha/cpu.c
@@ -235,6 +235,7 @@ static const struct SysemuCPUOps alpha_sysemu_ops = {
#include "accel/tcg/cpu-ops.h"
static const TCGCPUOps alpha_tcg_ops = {
+ .mttcg_supported = true,
/* Alpha processors have a weak memory model */
.guest_default_memory_order = 0,
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index 3e9760b5518..377791c84dd 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -2671,6 +2671,7 @@ static const struct SysemuCPUOps arm_sysemu_ops = {
#ifdef CONFIG_TCG
static const TCGCPUOps arm_tcg_ops = {
+ .mttcg_supported = true,
/* ARM processors have a weak memory model */
.guest_default_memory_order = 0,
diff --git a/target/arm/tcg/cpu-v7m.c b/target/arm/tcg/cpu-v7m.c
index 89d4e4b4a2f..85d8db87f9b 100644
--- a/target/arm/tcg/cpu-v7m.c
+++ b/target/arm/tcg/cpu-v7m.c
@@ -232,6 +232,7 @@ static void cortex_m55_initfn(Object *obj)
}
static const TCGCPUOps arm_v7m_tcg_ops = {
+ .mttcg_supported = true,
/* ARM processors have a weak memory model */
.guest_default_memory_order = 0,
diff --git a/target/avr/cpu.c b/target/avr/cpu.c
index 8f79cf4c08b..064ee3ec3f1 100644
--- a/target/avr/cpu.c
+++ b/target/avr/cpu.c
@@ -224,6 +224,7 @@ static const struct SysemuCPUOps avr_sysemu_ops = {
#include "accel/tcg/cpu-ops.h"
static const TCGCPUOps avr_tcg_ops = {
+ .mttcg_supported = false,
.guest_default_memory_order = 0,
.initialize = avr_cpu_tcg_init,
.translate_code = avr_cpu_translate_code,
diff --git a/target/hexagon/cpu.c b/target/hexagon/cpu.c
index 3d14e5cc6a0..a8293749f3f 100644
--- a/target/hexagon/cpu.c
+++ b/target/hexagon/cpu.c
@@ -325,6 +325,7 @@ static void hexagon_cpu_init(Object *obj)
#include "accel/tcg/cpu-ops.h"
static const TCGCPUOps hexagon_tcg_ops = {
+ .mttcg_supported = false,
/* MTTCG not yet supported: require strict ordering */
.guest_default_memory_order = TCG_MO_ALL,
.initialize = hexagon_translate_init,
diff --git a/target/hppa/cpu.c b/target/hppa/cpu.c
index dfbd9330565..1bfd2a402a9 100644
--- a/target/hppa/cpu.c
+++ b/target/hppa/cpu.c
@@ -253,6 +253,7 @@ static const struct SysemuCPUOps hppa_sysemu_ops = {
#include "accel/tcg/cpu-ops.h"
static const TCGCPUOps hppa_tcg_ops = {
+ .mttcg_supported = true,
/* PA-RISC 1.x processors have a strong memory model. */
/*
* ??? While we do not yet implement PA-RISC 2.0, those processors have
diff --git a/target/i386/tcg/tcg-cpu.c b/target/i386/tcg/tcg-cpu.c
index d941df09560..a0258f4739e 100644
--- a/target/i386/tcg/tcg-cpu.c
+++ b/target/i386/tcg/tcg-cpu.c
@@ -125,6 +125,7 @@ static bool x86_debug_check_breakpoint(CPUState *cs)
#include "accel/tcg/cpu-ops.h"
static const TCGCPUOps x86_tcg_ops = {
+ .mttcg_supported = true,
/*
* The x86 has a strong memory model with some store-after-load re-ordering
*/
diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c
index f5b8ef29ab0..19151651ae0 100644
--- a/target/loongarch/cpu.c
+++ b/target/loongarch/cpu.c
@@ -864,6 +864,7 @@ static void loongarch_cpu_dump_state(CPUState *cs, FILE *f, int flags)
#include "accel/tcg/cpu-ops.h"
static const TCGCPUOps loongarch_tcg_ops = {
+ .mttcg_supported = true,
.guest_default_memory_order = 0,
.initialize = loongarch_translate_init,
diff --git a/target/m68k/cpu.c b/target/m68k/cpu.c
index b2d8c8f1dea..2fda167b73e 100644
--- a/target/m68k/cpu.c
+++ b/target/m68k/cpu.c
@@ -589,6 +589,7 @@ static const struct SysemuCPUOps m68k_sysemu_ops = {
#include "accel/tcg/cpu-ops.h"
static const TCGCPUOps m68k_tcg_ops = {
+ .mttcg_supported = false,
/* MTTCG not yet supported: require strict ordering */
.guest_default_memory_order = TCG_MO_ALL,
diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c
index 4efba0dddb2..65c461265fb 100644
--- a/target/microblaze/cpu.c
+++ b/target/microblaze/cpu.c
@@ -427,6 +427,7 @@ static const struct SysemuCPUOps mb_sysemu_ops = {
#include "accel/tcg/cpu-ops.h"
static const TCGCPUOps mb_tcg_ops = {
+ .mttcg_supported = true,
/* MicroBlaze is always in-order. */
.guest_default_memory_order = TCG_MO_ALL,
diff --git a/target/mips/cpu.c b/target/mips/cpu.c
index 010773405a8..77bdb6db887 100644
--- a/target/mips/cpu.c
+++ b/target/mips/cpu.c
@@ -550,6 +550,7 @@ static const Property mips_cpu_properties[] = {
#ifdef CONFIG_TCG
#include "accel/tcg/cpu-ops.h"
static const TCGCPUOps mips_tcg_ops = {
+ .mttcg_supported = TARGET_LONG_BITS == 32,
.guest_default_memory_order = 0,
.initialize = mips_tcg_init,
diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c
index 87fe779042c..51df212bd6b 100644
--- a/target/openrisc/cpu.c
+++ b/target/openrisc/cpu.c
@@ -243,6 +243,7 @@ static const struct SysemuCPUOps openrisc_sysemu_ops = {
#include "accel/tcg/cpu-ops.h"
static const TCGCPUOps openrisc_tcg_ops = {
+ .mttcg_supported = true,
.guest_default_memory_order = 0,
.initialize = openrisc_translate_init,
diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c
index 8300fa5777e..f95c731c97f 100644
--- a/target/ppc/cpu_init.c
+++ b/target/ppc/cpu_init.c
@@ -7478,6 +7478,7 @@ static const struct SysemuCPUOps ppc_sysemu_ops = {
#include "accel/tcg/cpu-ops.h"
static const TCGCPUOps ppc_tcg_ops = {
+ .mttcg_supported = TARGET_LONG_BITS == 64,
.guest_default_memory_order = 0,
.initialize = ppc_translate_init,
.translate_code = ppc_translate_code,
diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
index 88f7cdb887c..3afbae9733b 100644
--- a/target/riscv/tcg/tcg-cpu.c
+++ b/target/riscv/tcg/tcg-cpu.c
@@ -141,6 +141,7 @@ static void riscv_restore_state_to_opc(CPUState *cs,
}
static const TCGCPUOps riscv_tcg_ops = {
+ .mttcg_supported = true,
.guest_default_memory_order = 0,
.initialize = riscv_translate_init,
diff --git a/target/rx/cpu.c b/target/rx/cpu.c
index f073fe8fc98..654bf7ae5b2 100644
--- a/target/rx/cpu.c
+++ b/target/rx/cpu.c
@@ -204,6 +204,7 @@ static const struct SysemuCPUOps rx_sysemu_ops = {
#include "accel/tcg/cpu-ops.h"
static const TCGCPUOps rx_tcg_ops = {
+ .mttcg_supported = false,
/* MTTCG not yet supported: require strict ordering */
.guest_default_memory_order = TCG_MO_ALL,
diff --git a/target/s390x/cpu.c b/target/s390x/cpu.c
index 1e101b5afeb..41cccc1e692 100644
--- a/target/s390x/cpu.c
+++ b/target/s390x/cpu.c
@@ -345,6 +345,7 @@ void cpu_get_tb_cpu_state(CPUS390XState *env, vaddr *pc,
}
static const TCGCPUOps s390_tcg_ops = {
+ .mttcg_supported = true,
/*
* The z/Architecture has a strong memory model with some
* store-after-load re-ordering.
diff --git a/target/sh4/cpu.c b/target/sh4/cpu.c
index 7a05301c6ff..e20e49fca8a 100644
--- a/target/sh4/cpu.c
+++ b/target/sh4/cpu.c
@@ -262,6 +262,7 @@ static const struct SysemuCPUOps sh4_sysemu_ops = {
#include "accel/tcg/cpu-ops.h"
static const TCGCPUOps superh_tcg_ops = {
+ .mttcg_supported = false,
/* MTTCG not yet supported: require strict ordering */
.guest_default_memory_order = TCG_MO_ALL,
diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c
index 56d9417ae3f..f6b3c0f129a 100644
--- a/target/sparc/cpu.c
+++ b/target/sparc/cpu.c
@@ -1001,6 +1001,7 @@ static const struct SysemuCPUOps sparc_sysemu_ops = {
#include "accel/tcg/cpu-ops.h"
static const TCGCPUOps sparc_tcg_ops = {
+ .mttcg_supported = true,
/*
* From Oracle SPARC Architecture 2015:
*
diff --git a/target/tricore/cpu.c b/target/tricore/cpu.c
index c68954b4096..258f55a566f 100644
--- a/target/tricore/cpu.c
+++ b/target/tricore/cpu.c
@@ -172,6 +172,7 @@ static const struct SysemuCPUOps tricore_sysemu_ops = {
#include "accel/tcg/cpu-ops.h"
static const TCGCPUOps tricore_tcg_ops = {
+ .mttcg_supported = false,
/* MTTCG not yet supported: require strict ordering */
.guest_default_memory_order = TCG_MO_ALL,
.initialize = tricore_tcg_init,
diff --git a/target/xtensa/cpu.c b/target/xtensa/cpu.c
index 2cbf4e30108..3f00e8e4239 100644
--- a/target/xtensa/cpu.c
+++ b/target/xtensa/cpu.c
@@ -232,6 +232,7 @@ static const struct SysemuCPUOps xtensa_sysemu_ops = {
#include "accel/tcg/cpu-ops.h"
static const TCGCPUOps xtensa_tcg_ops = {
+ .mttcg_supported = true,
/* Xtensa processors have a weak memory model */
.guest_default_memory_order = 0,
--
2.47.1
^ permalink raw reply related [flat|nested] 23+ messages in thread* Re: [PATCH-for-10.1 v3 19/19] tcg: Convert TARGET_SUPPORTS_MTTCG to TCGCPUOps::mttcg_supported field
2025-04-03 22:04 ` [PATCH-for-10.1 v3 19/19] tcg: Convert TARGET_SUPPORTS_MTTCG to TCGCPUOps::mttcg_supported field Philippe Mathieu-Daudé
@ 2025-04-05 11:29 ` Richard Henderson
2025-04-05 14:14 ` Philippe Mathieu-Daudé
0 siblings, 1 reply; 23+ messages in thread
From: Richard Henderson @ 2025-04-05 11:29 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, qemu-devel; +Cc: Pierrick Bouvier
On 4/3/25 15:04, Philippe Mathieu-Daudé wrote:
> Instead of having a compile-time TARGET_SUPPORTS_MTTCG definition,
> have each target set the 'mttcg_supported' field in the TCGCPUOps
> structure.
>
> Since so far we only emulate one target architecture at a time,
> tcg_init_machine() gets whether MTTCG is supported via the
> current CPU class (CPU_RESOLVING_TYPE).
>
> Since TARGET_SUPPORTS_MTTCG isn't available anymore,
> instead of emiting a warning when the 'thread' property
> is set in tcg_set_thread(), emit it in tcg_init_machine()
> where it is consumed.
>
> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
> Reviewed-by: Anton Johansson <anjo@rev.ng>
> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
This doesn't work for i386 and riscv, which have both been "updated" to initialize
cc->tcg_ops via ${arch}_tcg_cpu_accel_type_info ...
> static void mttcg_init(TCGState *s)
> {
> -#ifdef TARGET_SUPPORTS_MTTCG
> - bool mttcg_supported = true;
> -#else
> - bool mttcg_supported = false;
> -#endif
> + CPUClass *cc = CPU_CLASS(object_class_by_name(CPU_RESOLVING_TYPE));
> + bool mttcg_supported = cc->tcg_ops->mttcg_supported;
... which has not yet been called, so NULL pointer dereference.
I'm not sure why the init of tcg_ops was moved from ${arch}_cpu_class_init.
Probably it looked nice to remove the #ifdef CONFIG_TCG.
There's a definite ordering problem here, and I'm not sure how to fix it.
r~
^ permalink raw reply [flat|nested] 23+ messages in thread* Re: [PATCH-for-10.1 v3 19/19] tcg: Convert TARGET_SUPPORTS_MTTCG to TCGCPUOps::mttcg_supported field
2025-04-05 11:29 ` Richard Henderson
@ 2025-04-05 14:14 ` Philippe Mathieu-Daudé
0 siblings, 0 replies; 23+ messages in thread
From: Philippe Mathieu-Daudé @ 2025-04-05 14:14 UTC (permalink / raw)
To: Richard Henderson, qemu-devel; +Cc: Pierrick Bouvier
On 5/4/25 13:29, Richard Henderson wrote:
> On 4/3/25 15:04, Philippe Mathieu-Daudé wrote:
>> Instead of having a compile-time TARGET_SUPPORTS_MTTCG definition,
>> have each target set the 'mttcg_supported' field in the TCGCPUOps
>> structure.
>>
>> Since so far we only emulate one target architecture at a time,
>> tcg_init_machine() gets whether MTTCG is supported via the
>> current CPU class (CPU_RESOLVING_TYPE).
>>
>> Since TARGET_SUPPORTS_MTTCG isn't available anymore,
>> instead of emiting a warning when the 'thread' property
>> is set in tcg_set_thread(), emit it in tcg_init_machine()
>> where it is consumed.
>>
>> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
>> Reviewed-by: Anton Johansson <anjo@rev.ng>
>> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
>> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
>
> This doesn't work for i386 and riscv, which have both been "updated" to
> initialize cc->tcg_ops via ${arch}_tcg_cpu_accel_type_info ...
>
>> static void mttcg_init(TCGState *s)
>> {
>> -#ifdef TARGET_SUPPORTS_MTTCG
>> - bool mttcg_supported = true;
>> -#else
>> - bool mttcg_supported = false;
>> -#endif
>> + CPUClass *cc = CPU_CLASS(object_class_by_name(CPU_RESOLVING_TYPE));
>> + bool mttcg_supported = cc->tcg_ops->mttcg_supported;
>
> ... which has not yet been called, so NULL pointer dereference.
>
> I'm not sure why the init of tcg_ops was moved from ${arch}_cpu_class_init.
> Probably it looked nice to remove the #ifdef CONFIG_TCG.
>
> There's a definite ordering problem here, and I'm not sure how to fix it.
Can you just drop this single patch? I'll see what needs to be done.
Thanks,
Phil.
^ permalink raw reply [flat|nested] 23+ messages in thread