[RFC PATCH-for-10.1 00/39] single-binary: Make hw/arm/ common

[RFC PATCH-for-10.1 00/39] single-binary: Make hw/arm/ common

[Philippe Mathieu-Daudé]

Hi,

At this point this series is mostly a draft for Pierrick.

After introducing the generic TargetInfo API [*], we implement
the ARM variants, then use the API to remove target-specific code,
allowing to eventually remove the target-specific arm_ss[] source
set in meson.build, having all objects in arm_common_ss[].
Various header cleanups are necessary before getting there.

Regards,

Phil.

Available here, based on tcg-next:
https://gitlab.com/philmd/qemu/-/tags/single-binary-hw-arm-rfc-v1

[*] https://lore.kernel.org/qemu-devel/20250403234914.9154-1-philmd@linaro.org/

Philippe Mathieu-Daudé (39):
  target/arm: Implement per-binary TargetInfo structures
  target/arm: Register TYPE_BINARY_QEMU_SYSTEM_ARM/AARCH64 interfaces
  target/arm: Filter CPU types for binary
  hw/arm: Filter machine types for binary
  hw/arm/aspeed: Filter machine types for binary
  hw/arm/aspeed: Build objects once
  hw/arm/raspi: Filter machine types for binary
  hw/arm/raspi: Build objects once
  target/arm/cpregs: Include missing 'target/arm/cpu.h' header
  hw/arm/boot: Include missing 'system/memory.h' header
  hw/arm: Use full "target/arm/cpu.h" path to include target's "cpu.h"
  target/arm/cpu-features: Include missing 'cpu.h' header
  target/arm/qmp: Include missing 'cpu.h' header
  target/arm/kvm: Include missing 'cpu-qom.h' header
  target/arm/hvf: Include missing 'cpu-qom.h' header
  hw/arm: Remove unnecessary 'cpu.h' header
  target/arm: Restrict inclusion of 'multiprocessing.h'
  target/arm: Move some definitions from 'cpu.h' to 'multiprocessing.h'
  hw/arm: Include missing 'target/arm/gtimer.h' header
  target/arm: Extract PSCI definitions to 'psci.h'
  target/arm: Extract feature definitions to 'cpu_has_feature.h' header
  target/arm: Add arm_cpu_has_feature() helper
  hw/arm/realview: Replace arm_feature() -> arm_cpu_has_feature()
  hw/arm/virt-acpi: Replace arm_feature() -> arm_cpu_has_feature()
  hw/arm: Build virt-acpi-build.c once
  system/hvf: Avoid including 'cpu.h'
  system/hvf: Expose hvf_enabled() to common code
  exec: Do not poison hardware accelerators
  hw/arm: Build sbsa-ref.c once
  target/arm: Replace target_ulong -> hwaddr in ARMMMUFaultInfo
  target/arm: Replace target_ulong -> uint64_t for HWBreakpoint
  target/arm: Replace target_ulong -> vaddr for CPUWatchpoint
  hw/core/machine: Allow dynamic registration of valid CPU types
  hw/arm/virt: Register valid CPU types dynamically
  hw/arm/virt: Replace TARGET_AARCH64 -> target_long_bits()
  target/arm: Expose Aarch64 helpers indistinctly
  hw/arm: Build virt.c once
  hw/arm: Move xen files to arm_common_ss[]
  hw/arm/meson: Remove arm_ss[] source set

 MAINTAINERS                              |  1 +
 meson.build                              |  1 +
 include/exec/poison.h                    |  4 --
 include/hw/arm/boot.h                    |  3 +-
 include/hw/arm/digic.h                   |  2 +-
 include/hw/arm/fsl-imx6.h                |  2 +-
 include/hw/arm/fsl-imx6ul.h              |  2 +-
 include/hw/arm/fsl-imx7.h                |  2 +-
 include/hw/arm/fsl-imx8mp.h              |  2 +-
 include/hw/boards.h                      |  8 +++
 include/qemu/target_info-qom.h           | 20 ++++++
 include/system/hvf.h                     | 17 ++++--
 include/system/hvf_int.h                 |  2 +
 target/arm/cpregs.h                      |  1 +
 target/arm/cpu-features.h                |  1 +
 target/arm/cpu.h                         | 78 +-----------------------
 target/arm/cpu_has_feature.h             | 67 ++++++++++++++++++++
 target/arm/hvf_arm.h                     |  2 +-
 target/arm/internals.h                   | 22 +++----
 target/arm/kvm_arm.h                     |  1 +
 target/arm/multiprocessing.h             | 18 ++++++
 target/arm/psci.h                        | 18 ++++++
 accel/stubs/hvf-stub.c                   | 12 ++++
 hw/arm/aspeed.c                          | 30 ++++++---
 hw/arm/aspeed_ast2600.c                  |  1 +
 hw/arm/aspeed_ast27x0.c                  |  2 +
 hw/arm/b-l475e-iot01a.c                  |  1 +
 hw/arm/bananapi_m2u.c                    |  1 +
 hw/arm/bcm2836.c                         |  4 --
 hw/arm/bcm2838.c                         |  1 +
 hw/arm/boot.c                            |  2 +
 hw/arm/collie.c                          |  1 +
 hw/arm/exynos4210.c                      |  3 +-
 hw/arm/exynos4_boards.c                  |  1 +
 hw/arm/fby35.c                           |  1 +
 hw/arm/fsl-imx8mp.c                      |  1 +
 hw/arm/highbank.c                        |  4 +-
 hw/arm/imx8mp-evk.c                      |  1 +
 hw/arm/mcimx6ul-evk.c                    |  1 +
 hw/arm/mcimx7d-sabre.c                   |  1 +
 hw/arm/microbit.c                        |  1 +
 hw/arm/mps2-tz.c                         |  4 ++
 hw/arm/mps2.c                            |  4 ++
 hw/arm/mps3r.c                           |  3 +-
 hw/arm/musca.c                           |  2 +
 hw/arm/npcm8xx.c                         |  2 +
 hw/arm/omap_sx1.c                        |  2 +
 hw/arm/orangepi.c                        |  1 +
 hw/arm/raspi.c                           |  9 +--
 hw/arm/raspi4b.c                         |  1 +
 hw/arm/realview.c                        | 14 +++--
 hw/arm/sbsa-ref.c                        |  3 +
 hw/arm/smmuv3.c                          |  1 -
 hw/arm/stellaris.c                       |  3 +
 hw/arm/versatilepb.c                     |  1 +
 hw/arm/vexpress.c                        |  2 +
 hw/arm/virt-acpi-build.c                 |  4 +-
 hw/arm/virt.c                            | 44 +++++++------
 hw/arm/xilinx_zynq.c                     |  1 +
 hw/arm/xlnx-versal-virt.c                |  2 +
 hw/arm/xlnx-zcu102.c                     |  2 +
 hw/core/machine.c                        | 28 +++++++++
 hw/vmapple/vmapple.c                     |  3 +
 target/arm/arm-qmp-cmds.c                |  1 +
 target/arm/cpu.c                         | 10 +++
 target/arm/cpu64.c                       |  2 +
 target/arm/helper.c                      |  1 +
 target/arm/hvf/hvf.c                     |  1 +
 target/arm/hyp_gdbstub.c                 | 14 ++---
 target/arm/kvm.c                         |  1 +
 target/arm/target_info-aarch64-softmmu.c | 24 ++++++++
 target/arm/target_info-arm-softmmu.c     | 24 ++++++++
 target/arm/tcg/op_helper.c               |  2 +
 target/arm/tcg/psci.c                    |  1 +
 target_info-qom.c                        |  8 +++
 accel/stubs/meson.build                  |  1 +
 hw/arm/meson.build                       | 22 ++++---
 scripts/make-config-poison.sh            |  4 ++
 target/arm/meson.build                   |  5 ++
 79 files changed, 429 insertions(+), 171 deletions(-)
 create mode 100644 target/arm/cpu_has_feature.h
 create mode 100644 target/arm/psci.h
 create mode 100644 accel/stubs/hvf-stub.c
 create mode 100644 target/arm/target_info-aarch64-softmmu.c
 create mode 100644 target/arm/target_info-arm-softmmu.c

-- 
2.47.1

[RFC PATCH-for-10.1 01/39] target/arm: Implement per-binary TargetInfo structures

[Philippe Mathieu-Daudé]

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
 meson.build                              |  1 +
 target/arm/target_info-aarch64-softmmu.c | 24 ++++++++++++++++++++++++
 target/arm/target_info-arm-softmmu.c     | 24 ++++++++++++++++++++++++
 target/arm/meson.build                   |  5 +++++
 4 files changed, 54 insertions(+)
 create mode 100644 target/arm/target_info-aarch64-softmmu.c
 create mode 100644 target/arm/target_info-arm-softmmu.c

diff --git a/meson.build b/meson.build
index b93253166c8..9df662932a4 100644
--- a/meson.build
+++ b/meson.build
@@ -3263,6 +3263,7 @@ host_kconfig = \
 ignored = [ 'TARGET_XML_FILES', 'TARGET_ABI_DIR', 'TARGET_ARCH' ]
 
 target_info = [
+  'arm-softmmu', 'aarch64-softmmu',
 ]
 
 default_targets = 'CONFIG_DEFAULT_TARGETS' in config_host
diff --git a/target/arm/target_info-aarch64-softmmu.c b/target/arm/target_info-aarch64-softmmu.c
new file mode 100644
index 00000000000..002aac642f8
--- /dev/null
+++ b/target/arm/target_info-aarch64-softmmu.c
@@ -0,0 +1,24 @@
+/*
+ * QEMU legacy binary helpers
+ *
+ *  Copyright (c) Linaro
+ *
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ */
+
+#include "qemu/osdep.h"
+#include "qemu/target_info-impl.h"
+#include "cpu-qom.h"
+
+static const BinaryTargetInfo target_info_aarch64_system = {
+    .name = "aarch64",
+    .system_arch = SYS_EMU_TARGET_AARCH64,
+    .endianness = ENDIAN_MODE_LITTLE,
+    .long_bits = 64,
+    .cpu_resolving_type = TYPE_ARM_CPU,
+};
+
+const BinaryTargetInfo *target_info(void)
+{
+    return &target_info_aarch64_system;
+}
diff --git a/target/arm/target_info-arm-softmmu.c b/target/arm/target_info-arm-softmmu.c
new file mode 100644
index 00000000000..24b68b1ad8b
--- /dev/null
+++ b/target/arm/target_info-arm-softmmu.c
@@ -0,0 +1,24 @@
+/*
+ * QEMU legacy binary helpers
+ *
+ *  Copyright (c) Linaro
+ *
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ */
+
+#include "qemu/osdep.h"
+#include "qemu/target_info-impl.h"
+#include "cpu-qom.h"
+
+static const BinaryTargetInfo target_info_arm_system = {
+    .name = "arm",
+    .system_arch = SYS_EMU_TARGET_ARM,
+    .endianness = ENDIAN_MODE_LITTLE,
+    .long_bits = 32,
+    .cpu_resolving_type = TYPE_ARM_CPU,
+};
+
+const BinaryTargetInfo *target_info(void)
+{
+    return &target_info_arm_system;
+}
diff --git a/target/arm/meson.build b/target/arm/meson.build
index 3065081d241..706c49c1b2a 100644
--- a/target/arm/meson.build
+++ b/target/arm/meson.build
@@ -25,6 +25,11 @@ arm_system_ss.add(files(
   'machine.c',
   'ptw.c',
 ))
+arm_system_ss.add(when: 'TARGET_AARCH64', if_true: files(
+  'target_info-aarch64-softmmu.c',
+), if_false: files(
+  'target_info-arm-softmmu.c',
+))
 
 arm_user_ss = ss.source_set()
 
-- 
2.47.1

[RFC PATCH-for-10.1 02/39] target/arm: Register TYPE_BINARY_QEMU_SYSTEM_ARM/AARCH64 interfaces

[Philippe Mathieu-Daudé]

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
 include/qemu/target_info-qom.h | 20 ++++++++++++++++++++
 target_info-qom.c              |  8 ++++++++
 2 files changed, 28 insertions(+)

diff --git a/include/qemu/target_info-qom.h b/include/qemu/target_info-qom.h
index c87d47acf66..880b34e699e 100644
--- a/include/qemu/target_info-qom.h
+++ b/include/qemu/target_info-qom.h
@@ -9,6 +9,26 @@
 #ifndef QEMU_TARGET_INFO_QOM_H
 #define QEMU_TARGET_INFO_QOM_H
 
+#include "qom/object.h"
+
 #define TYPE_LEGACY_BINARY_PREFIX "legacy-binary-"
 
+#define TYPE_LEGACY_BINARY_QEMU_SYSTEM_ARM \
+        "legacy-binary-qemu-system-arm"
+#define TYPE_LEGACY_BINARY_QEMU_SYSTEM_AARCH64 \
+        "legacy-binary-qemu-system-aarch64"
+
+#define LEGACY_BINARY_QEMU_SYSTEM_ARM_INTERFACE \
+    (InterfaceInfo[]) { \
+        { TYPE_LEGACY_BINARY_QEMU_SYSTEM_ARM }, \
+        { TYPE_LEGACY_BINARY_QEMU_SYSTEM_AARCH64 }, \
+        { }, \
+    }
+
+#define LEGACY_BINARY_QEMU_SYSTEM_AARCH64_INTERFACE \
+    (InterfaceInfo[]) { \
+        { TYPE_LEGACY_BINARY_QEMU_SYSTEM_AARCH64 }, \
+        { }, \
+    }
+
 #endif
diff --git a/target_info-qom.c b/target_info-qom.c
index 6970b95ee0b..db3054c307d 100644
--- a/target_info-qom.c
+++ b/target_info-qom.c
@@ -10,6 +10,14 @@
 #include "qemu/target_info-qom.h"
 
 static const TypeInfo target_info_types[] = {
+    {
+        .name           = TYPE_LEGACY_BINARY_QEMU_SYSTEM_ARM,
+        .parent         = TYPE_INTERFACE,
+    },
+    {
+        .name           = TYPE_LEGACY_BINARY_QEMU_SYSTEM_AARCH64,
+        .parent         = TYPE_INTERFACE,
+    },
 };
 
 DEFINE_TYPES(target_info_types)
-- 
2.47.1

[RFC PATCH-for-10.1 03/39] target/arm: Filter CPU types for binary

[Philippe Mathieu-Daudé]

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
 target/arm/cpu.c   | 2 ++
 target/arm/cpu64.c | 2 ++
 2 files changed, 4 insertions(+)

diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index 377791c84dd..b1aa482c726 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -50,6 +50,7 @@
 #include "disas/capstone.h"
 #include "fpu/softfloat.h"
 #include "cpregs.h"
+#include "qemu/target_info-qom.h"
 #include "target/arm/cpu-qom.h"
 #include "target/arm/gtimer.h"
 
@@ -2759,6 +2760,7 @@ void arm_cpu_register(const ARMCPUInfo *info)
         .instance_init = arm_cpu_instance_init,
         .class_init = info->class_init ?: cpu_register_class_init,
         .class_data = (void *)info,
+        .interfaces = LEGACY_BINARY_QEMU_SYSTEM_ARM_INTERFACE,
     };
 
     type_info.name = g_strdup_printf("%s-" TYPE_ARM_CPU, info->name);
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
index 8188ede5cc8..9f8c98563ac 100644
--- a/target/arm/cpu64.c
+++ b/target/arm/cpu64.c
@@ -24,6 +24,7 @@
 #include "cpregs.h"
 #include "qemu/module.h"
 #include "qemu/units.h"
+#include "qemu/target_info-qom.h"
 #include "system/kvm.h"
 #include "system/hvf.h"
 #include "system/qtest.h"
@@ -856,6 +857,7 @@ void aarch64_cpu_register(const ARMCPUInfo *info)
         .instance_init = aarch64_cpu_instance_init,
         .class_init = info->class_init ?: cpu_register_class_init,
         .class_data = (void *)info,
+        .interfaces = LEGACY_BINARY_QEMU_SYSTEM_AARCH64_INTERFACE,
     };
 
     type_info.name = g_strdup_printf("%s-" TYPE_ARM_CPU, info->name);
-- 
2.47.1

[RFC PATCH-for-10.1 04/39] hw/arm: Filter machine types for binary

[Philippe Mathieu-Daudé]

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
 hw/arm/b-l475e-iot01a.c   | 1 +
 hw/arm/collie.c           | 1 +
 hw/arm/exynos4_boards.c   | 1 +
 hw/arm/fby35.c            | 1 +
 hw/arm/highbank.c         | 2 ++
 hw/arm/microbit.c         | 1 +
 hw/arm/mps2-tz.c          | 4 ++++
 hw/arm/mps2.c             | 4 ++++
 hw/arm/mps3r.c            | 1 +
 hw/arm/musca.c            | 2 ++
 hw/arm/omap_sx1.c         | 2 ++
 hw/arm/realview.c         | 4 ++++
 hw/arm/sbsa-ref.c         | 1 +
 hw/arm/stellaris.c        | 3 +++
 hw/arm/versatilepb.c      | 1 +
 hw/arm/vexpress.c         | 2 ++
 hw/arm/xilinx_zynq.c      | 1 +
 hw/arm/xlnx-versal-virt.c | 1 +
 hw/arm/xlnx-zcu102.c      | 1 +
 19 files changed, 34 insertions(+)

diff --git a/hw/arm/b-l475e-iot01a.c b/hw/arm/b-l475e-iot01a.c
index c9a5209216c..f7fb6c54395 100644
--- a/hw/arm/b-l475e-iot01a.c
+++ b/hw/arm/b-l475e-iot01a.c
@@ -131,6 +131,7 @@ static const TypeInfo bl475e_machine_type[] = {
         .parent         = TYPE_MACHINE,
         .instance_size  = sizeof(Bl475eMachineState),
         .class_init     = bl475e_machine_init,
+        .interfaces     = LEGACY_BINARY_QEMU_SYSTEM_ARM_INTERFACE,
     }
 };
 
diff --git a/hw/arm/collie.c b/hw/arm/collie.c
index e83aee58c6b..c5bed6c7006 100644
--- a/hw/arm/collie.c
+++ b/hw/arm/collie.c
@@ -86,6 +86,7 @@ static const TypeInfo collie_machine_typeinfo = {
     .parent = TYPE_MACHINE,
     .class_init = collie_machine_class_init,
     .instance_size = sizeof(CollieMachineState),
+    .interfaces = LEGACY_BINARY_QEMU_SYSTEM_ARM_INTERFACE,
 };
 
 static void collie_machine_register_types(void)
diff --git a/hw/arm/exynos4_boards.c b/hw/arm/exynos4_boards.c
index 2d8f2d73265..53b79b893d8 100644
--- a/hw/arm/exynos4_boards.c
+++ b/hw/arm/exynos4_boards.c
@@ -192,6 +192,7 @@ static const TypeInfo smdkc210_type = {
     .name = MACHINE_TYPE_NAME("smdkc210"),
     .parent = TYPE_MACHINE,
     .class_init = smdkc210_class_init,
+    .interfaces = LEGACY_BINARY_QEMU_SYSTEM_ARM_INTERFACE,
 };
 
 static void exynos4_machines_init(void)
diff --git a/hw/arm/fby35.c b/hw/arm/fby35.c
index 6d3663f14a1..d4cc596fb67 100644
--- a/hw/arm/fby35.c
+++ b/hw/arm/fby35.c
@@ -187,6 +187,7 @@ static const TypeInfo fby35_types[] = {
         .class_init = fby35_class_init,
         .instance_size = sizeof(Fby35State),
         .instance_init = fby35_instance_init,
+        .interfaces = LEGACY_BINARY_QEMU_SYSTEM_ARM_INTERFACE,
     },
 };
 
diff --git a/hw/arm/highbank.c b/hw/arm/highbank.c
index 0f3c207d548..ea3621e4f87 100644
--- a/hw/arm/highbank.c
+++ b/hw/arm/highbank.c
@@ -363,6 +363,7 @@ static const TypeInfo highbank_type = {
     .name = MACHINE_TYPE_NAME("highbank"),
     .parent = TYPE_MACHINE,
     .class_init = highbank_class_init,
+    .interfaces = LEGACY_BINARY_QEMU_SYSTEM_ARM_INTERFACE,
 };
 
 static void midway_class_init(ObjectClass *oc, void *data)
@@ -387,6 +388,7 @@ static const TypeInfo midway_type = {
     .name = MACHINE_TYPE_NAME("midway"),
     .parent = TYPE_MACHINE,
     .class_init = midway_class_init,
+    .interfaces = LEGACY_BINARY_QEMU_SYSTEM_ARM_INTERFACE,
 };
 
 static void calxeda_machines_init(void)
diff --git a/hw/arm/microbit.c b/hw/arm/microbit.c
index ade363daaa4..dd265d8cfb3 100644
--- a/hw/arm/microbit.c
+++ b/hw/arm/microbit.c
@@ -74,6 +74,7 @@ static const TypeInfo microbit_info = {
     .parent = TYPE_MACHINE,
     .instance_size = sizeof(MicrobitMachineState),
     .class_init = microbit_machine_class_init,
+    .interfaces = LEGACY_BINARY_QEMU_SYSTEM_ARM_INTERFACE,
 };
 
 static void microbit_machine_init(void)
diff --git a/hw/arm/mps2-tz.c b/hw/arm/mps2-tz.c
index b0633a5a69e..1f0a431adc8 100644
--- a/hw/arm/mps2-tz.c
+++ b/hw/arm/mps2-tz.c
@@ -1463,24 +1463,28 @@ static const TypeInfo mps2tz_an505_info = {
     .name = TYPE_MPS2TZ_AN505_MACHINE,
     .parent = TYPE_MPS2TZ_MACHINE,
     .class_init = mps2tz_an505_class_init,
+    .interfaces = LEGACY_BINARY_QEMU_SYSTEM_ARM_INTERFACE,
 };
 
 static const TypeInfo mps2tz_an521_info = {
     .name = TYPE_MPS2TZ_AN521_MACHINE,
     .parent = TYPE_MPS2TZ_MACHINE,
     .class_init = mps2tz_an521_class_init,
+    .interfaces = LEGACY_BINARY_QEMU_SYSTEM_ARM_INTERFACE,
 };
 
 static const TypeInfo mps3tz_an524_info = {
     .name = TYPE_MPS3TZ_AN524_MACHINE,
     .parent = TYPE_MPS2TZ_MACHINE,
     .class_init = mps3tz_an524_class_init,
+    .interfaces = LEGACY_BINARY_QEMU_SYSTEM_ARM_INTERFACE,
 };
 
 static const TypeInfo mps3tz_an547_info = {
     .name = TYPE_MPS3TZ_AN547_MACHINE,
     .parent = TYPE_MPS2TZ_MACHINE,
     .class_init = mps3tz_an547_class_init,
+    .interfaces = LEGACY_BINARY_QEMU_SYSTEM_ARM_INTERFACE,
 };
 
 static void mps2tz_machine_init(void)
diff --git a/hw/arm/mps2.c b/hw/arm/mps2.c
index 6958485a668..e4763add3db 100644
--- a/hw/arm/mps2.c
+++ b/hw/arm/mps2.c
@@ -563,24 +563,28 @@ static const TypeInfo mps2_an385_info = {
     .name = TYPE_MPS2_AN385_MACHINE,
     .parent = TYPE_MPS2_MACHINE,
     .class_init = mps2_an385_class_init,
+    .interfaces = LEGACY_BINARY_QEMU_SYSTEM_ARM_INTERFACE,
 };
 
 static const TypeInfo mps2_an386_info = {
     .name = TYPE_MPS2_AN386_MACHINE,
     .parent = TYPE_MPS2_MACHINE,
     .class_init = mps2_an386_class_init,
+    .interfaces = LEGACY_BINARY_QEMU_SYSTEM_ARM_INTERFACE,
 };
 
 static const TypeInfo mps2_an500_info = {
     .name = TYPE_MPS2_AN500_MACHINE,
     .parent = TYPE_MPS2_MACHINE,
     .class_init = mps2_an500_class_init,
+    .interfaces = LEGACY_BINARY_QEMU_SYSTEM_ARM_INTERFACE,
 };
 
 static const TypeInfo mps2_an511_info = {
     .name = TYPE_MPS2_AN511_MACHINE,
     .parent = TYPE_MPS2_MACHINE,
     .class_init = mps2_an511_class_init,
+    .interfaces = LEGACY_BINARY_QEMU_SYSTEM_ARM_INTERFACE,
 };
 
 static void mps2_machine_init(void)
diff --git a/hw/arm/mps3r.c b/hw/arm/mps3r.c
index 4dd1e8a7180..e9abbf00b43 100644
--- a/hw/arm/mps3r.c
+++ b/hw/arm/mps3r.c
@@ -634,6 +634,7 @@ static const TypeInfo mps3r_machine_types[] = {
         .name = TYPE_MPS3R_AN536_MACHINE,
         .parent = TYPE_MPS3R_MACHINE,
         .class_init = mps3r_an536_class_init,
+        .interfaces = LEGACY_BINARY_QEMU_SYSTEM_ARM_INTERFACE,
     },
 };
 
diff --git a/hw/arm/musca.c b/hw/arm/musca.c
index a4f43f1992b..5d63a4e9ec7 100644
--- a/hw/arm/musca.c
+++ b/hw/arm/musca.c
@@ -657,12 +657,14 @@ static const TypeInfo musca_a_info = {
     .name = TYPE_MUSCA_A_MACHINE,
     .parent = TYPE_MUSCA_MACHINE,
     .class_init = musca_a_class_init,
+    .interfaces = LEGACY_BINARY_QEMU_SYSTEM_ARM_INTERFACE,
 };
 
 static const TypeInfo musca_b1_info = {
     .name = TYPE_MUSCA_B1_MACHINE,
     .parent = TYPE_MUSCA_MACHINE,
     .class_init = musca_b1_class_init,
+    .interfaces = LEGACY_BINARY_QEMU_SYSTEM_ARM_INTERFACE,
 };
 
 static void musca_machine_init(void)
diff --git a/hw/arm/omap_sx1.c b/hw/arm/omap_sx1.c
index aa1e96b3ad7..bb676f63eb5 100644
--- a/hw/arm/omap_sx1.c
+++ b/hw/arm/omap_sx1.c
@@ -219,6 +219,7 @@ static const TypeInfo sx1_machine_v2_type = {
     .name = MACHINE_TYPE_NAME("sx1"),
     .parent = TYPE_MACHINE,
     .class_init = sx1_machine_v2_class_init,
+    .interfaces = LEGACY_BINARY_QEMU_SYSTEM_ARM_INTERFACE,
 };
 
 static void sx1_machine_v1_class_init(ObjectClass *oc, void *data)
@@ -238,6 +239,7 @@ static const TypeInfo sx1_machine_v1_type = {
     .name = MACHINE_TYPE_NAME("sx1-v1"),
     .parent = TYPE_MACHINE,
     .class_init = sx1_machine_v1_class_init,
+    .interfaces = LEGACY_BINARY_QEMU_SYSTEM_ARM_INTERFACE,
 };
 
 static void sx1_machine_init(void)
diff --git a/hw/arm/realview.c b/hw/arm/realview.c
index 008eeaf049a..f81d084eb80 100644
--- a/hw/arm/realview.c
+++ b/hw/arm/realview.c
@@ -431,6 +431,7 @@ static const TypeInfo realview_eb_type = {
     .name = MACHINE_TYPE_NAME("realview-eb"),
     .parent = TYPE_MACHINE,
     .class_init = realview_eb_class_init,
+    .interfaces = LEGACY_BINARY_QEMU_SYSTEM_ARM_INTERFACE,
 };
 
 static void realview_eb_mpcore_class_init(ObjectClass *oc, void *data)
@@ -452,6 +453,7 @@ static const TypeInfo realview_eb_mpcore_type = {
     .name = MACHINE_TYPE_NAME("realview-eb-mpcore"),
     .parent = TYPE_MACHINE,
     .class_init = realview_eb_mpcore_class_init,
+    .interfaces = LEGACY_BINARY_QEMU_SYSTEM_ARM_INTERFACE,
 };
 
 static void realview_pb_a8_class_init(ObjectClass *oc, void *data)
@@ -471,6 +473,7 @@ static const TypeInfo realview_pb_a8_type = {
     .name = MACHINE_TYPE_NAME("realview-pb-a8"),
     .parent = TYPE_MACHINE,
     .class_init = realview_pb_a8_class_init,
+    .interfaces = LEGACY_BINARY_QEMU_SYSTEM_ARM_INTERFACE,
 };
 
 static void realview_pbx_a9_class_init(ObjectClass *oc, void *data)
@@ -491,6 +494,7 @@ static const TypeInfo realview_pbx_a9_type = {
     .name = MACHINE_TYPE_NAME("realview-pbx-a9"),
     .parent = TYPE_MACHINE,
     .class_init = realview_pbx_a9_class_init,
+    .interfaces = LEGACY_BINARY_QEMU_SYSTEM_ARM_INTERFACE,
 };
 
 static void realview_machine_init(void)
diff --git a/hw/arm/sbsa-ref.c b/hw/arm/sbsa-ref.c
index aa09d7a0917..112cbbf29e6 100644
--- a/hw/arm/sbsa-ref.c
+++ b/hw/arm/sbsa-ref.c
@@ -920,6 +920,7 @@ static const TypeInfo sbsa_ref_info = {
     .instance_init = sbsa_ref_instance_init,
     .class_init    = sbsa_ref_class_init,
     .instance_size = sizeof(SBSAMachineState),
+    .interfaces    = LEGACY_BINARY_QEMU_SYSTEM_ARM_INTERFACE,
 };
 
 static void sbsa_ref_machine_init(void)
diff --git a/hw/arm/stellaris.c b/hw/arm/stellaris.c
index cbe914c93e9..b901683f78a 100644
--- a/hw/arm/stellaris.c
+++ b/hw/arm/stellaris.c
@@ -1475,6 +1475,7 @@ static const TypeInfo stellaris_i2c_info = {
     .instance_size = sizeof(stellaris_i2c_state),
     .instance_init = stellaris_i2c_init,
     .class_init    = stellaris_i2c_class_init,
+    .interfaces    = LEGACY_BINARY_QEMU_SYSTEM_ARM_INTERFACE,
 };
 
 static void stellaris_adc_class_init(ObjectClass *klass, void *data)
@@ -1492,6 +1493,7 @@ static const TypeInfo stellaris_adc_info = {
     .instance_size = sizeof(StellarisADCState),
     .instance_init = stellaris_adc_init,
     .class_init    = stellaris_adc_class_init,
+    .interfaces    = LEGACY_BINARY_QEMU_SYSTEM_ARM_INTERFACE,
 };
 
 static void stellaris_sys_class_init(ObjectClass *klass, void *data)
@@ -1512,6 +1514,7 @@ static const TypeInfo stellaris_sys_info = {
     .instance_size = sizeof(ssys_state),
     .instance_init = stellaris_sys_instance_init,
     .class_init = stellaris_sys_class_init,
+    .interfaces = LEGACY_BINARY_QEMU_SYSTEM_ARM_INTERFACE,
 };
 
 static void stellaris_register_types(void)
diff --git a/hw/arm/versatilepb.c b/hw/arm/versatilepb.c
index 35766445fa4..3cfcd56f06b 100644
--- a/hw/arm/versatilepb.c
+++ b/hw/arm/versatilepb.c
@@ -452,6 +452,7 @@ static const TypeInfo versatileab_type = {
     .name = MACHINE_TYPE_NAME("versatileab"),
     .parent = TYPE_MACHINE,
     .class_init = versatileab_class_init,
+    .interfaces = LEGACY_BINARY_QEMU_SYSTEM_ARM_INTERFACE,
 };
 
 static void versatile_machine_init(void)
diff --git a/hw/arm/vexpress.c b/hw/arm/vexpress.c
index 76c6107766c..6cd8c42925b 100644
--- a/hw/arm/vexpress.c
+++ b/hw/arm/vexpress.c
@@ -850,6 +850,7 @@ static const TypeInfo vexpress_a9_info = {
     .parent = TYPE_VEXPRESS_MACHINE,
     .class_init = vexpress_a9_class_init,
     .instance_init = vexpress_a9_instance_init,
+    .interfaces = LEGACY_BINARY_QEMU_SYSTEM_ARM_INTERFACE,
 };
 
 static const TypeInfo vexpress_a15_info = {
@@ -857,6 +858,7 @@ static const TypeInfo vexpress_a15_info = {
     .parent = TYPE_VEXPRESS_MACHINE,
     .class_init = vexpress_a15_class_init,
     .instance_init = vexpress_a15_instance_init,
+    .interfaces = LEGACY_BINARY_QEMU_SYSTEM_ARM_INTERFACE,
 };
 
 static void vexpress_machine_init(void)
diff --git a/hw/arm/xilinx_zynq.c b/hw/arm/xilinx_zynq.c
index b8916665ed6..8f2f0f35ff3 100644
--- a/hw/arm/xilinx_zynq.c
+++ b/hw/arm/xilinx_zynq.c
@@ -480,6 +480,7 @@ static const TypeInfo zynq_machine_type = {
     .parent = TYPE_MACHINE,
     .class_init = zynq_machine_class_init,
     .instance_size = sizeof(ZynqMachineState),
+    .interfaces = LEGACY_BINARY_QEMU_SYSTEM_ARM_INTERFACE,
 };
 
 static void zynq_machine_register_types(void)
diff --git a/hw/arm/xlnx-versal-virt.c b/hw/arm/xlnx-versal-virt.c
index 0c6f0359e3d..e19c4d9ef58 100644
--- a/hw/arm/xlnx-versal-virt.c
+++ b/hw/arm/xlnx-versal-virt.c
@@ -833,6 +833,7 @@ static const TypeInfo versal_virt_machine_init_typeinfo = {
     .instance_init = versal_virt_machine_instance_init,
     .instance_size = sizeof(VersalVirt),
     .instance_finalize = versal_virt_machine_finalize,
+    .interfaces = LEGACY_BINARY_QEMU_SYSTEM_ARM_INTERFACE,
 };
 
 static void versal_virt_machine_init_register_types(void)
diff --git a/hw/arm/xlnx-zcu102.c b/hw/arm/xlnx-zcu102.c
index 4fdb153e4d8..88b1eafab4d 100644
--- a/hw/arm/xlnx-zcu102.c
+++ b/hw/arm/xlnx-zcu102.c
@@ -303,6 +303,7 @@ static const TypeInfo xlnx_zcu102_machine_init_typeinfo = {
     .class_init = xlnx_zcu102_machine_class_init,
     .instance_init = xlnx_zcu102_machine_instance_init,
     .instance_size = sizeof(XlnxZCU102),
+    .interfaces = LEGACY_BINARY_QEMU_SYSTEM_ARM_INTERFACE,
 };
 
 static void xlnx_zcu102_machine_init_register_types(void)
-- 
2.47.1

[RFC PATCH-for-10.1 05/39] hw/arm/aspeed: Filter machine types for binary

[Philippe Mathieu-Daudé]

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
 hw/arm/aspeed.c | 30 +++++++++++++++++++++++-------
 1 file changed, 23 insertions(+), 7 deletions(-)

diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c
index 82f42582fa3..245f961a868 100644
--- a/hw/arm/aspeed.c
+++ b/hw/arm/aspeed.c
@@ -179,13 +179,11 @@ struct AspeedMachineState {
 #define AST2600_EVB_HW_STRAP1 0x000000C0
 #define AST2600_EVB_HW_STRAP2 0x00000003
 
-#ifdef TARGET_AARCH64
 /* AST2700 evb hardware value */
 /* SCU HW Strap1 */
 #define AST2700_EVB_HW_STRAP1 0x00000800
 /* SCUIO HW Strap1 */
 #define AST2700_EVB_HW_STRAP2 0x00000700
-#endif
 
 /* Rainier hardware value: (QEMU prototype) */
 #define RAINIER_BMC_HW_STRAP1 (0x00422016 | SCU_AST2600_HW_STRAP_BOOT_SRC_EMMC)
@@ -1663,7 +1661,6 @@ static void aspeed_minibmc_machine_ast1030_evb_class_init(ObjectClass *oc,
     aspeed_machine_class_init_cpus_defaults(mc);
 }
 
-#ifdef TARGET_AARCH64
 static void ast2700_evb_i2c_init(AspeedMachineState *bmc)
 {
     AspeedSoCState *soc = bmc->soc;
@@ -1713,7 +1710,6 @@ static void aspeed_machine_ast2700a1_evb_class_init(ObjectClass *oc, void *data)
     mc->default_ram_size = 1 * GiB;
     aspeed_machine_class_init_cpus_defaults(mc);
 }
-#endif
 
 static void aspeed_machine_qcom_dc_scm_v1_class_init(ObjectClass *oc,
                                                      void *data)
@@ -1760,92 +1756,112 @@ static const TypeInfo aspeed_machine_types[] = {
         .name          = MACHINE_TYPE_NAME("palmetto-bmc"),
         .parent        = TYPE_ASPEED_MACHINE,
         .class_init    = aspeed_machine_palmetto_class_init,
+        .interfaces    = LEGACY_BINARY_QEMU_SYSTEM_ARM_INTERFACE,
     }, {
         .name          = MACHINE_TYPE_NAME("supermicrox11-bmc"),
         .parent        = TYPE_ASPEED_MACHINE,
         .class_init    = aspeed_machine_supermicrox11_bmc_class_init,
+        .interfaces    = LEGACY_BINARY_QEMU_SYSTEM_ARM_INTERFACE,
     }, {
         .name          = MACHINE_TYPE_NAME("supermicro-x11spi-bmc"),
         .parent        = TYPE_ASPEED_MACHINE,
         .class_init    = aspeed_machine_supermicro_x11spi_bmc_class_init,
+        .interfaces    = LEGACY_BINARY_QEMU_SYSTEM_ARM_INTERFACE,
     }, {
         .name          = MACHINE_TYPE_NAME("ast2500-evb"),
         .parent        = TYPE_ASPEED_MACHINE,
         .class_init    = aspeed_machine_ast2500_evb_class_init,
+        .interfaces    = LEGACY_BINARY_QEMU_SYSTEM_ARM_INTERFACE,
     }, {
         .name          = MACHINE_TYPE_NAME("romulus-bmc"),
         .parent        = TYPE_ASPEED_MACHINE,
         .class_init    = aspeed_machine_romulus_class_init,
+        .interfaces    = LEGACY_BINARY_QEMU_SYSTEM_ARM_INTERFACE,
     }, {
         .name          = MACHINE_TYPE_NAME("sonorapass-bmc"),
         .parent        = TYPE_ASPEED_MACHINE,
         .class_init    = aspeed_machine_sonorapass_class_init,
+        .interfaces    = LEGACY_BINARY_QEMU_SYSTEM_ARM_INTERFACE,
     }, {
         .name          = MACHINE_TYPE_NAME("witherspoon-bmc"),
         .parent        = TYPE_ASPEED_MACHINE,
         .class_init    = aspeed_machine_witherspoon_class_init,
+        .interfaces    = LEGACY_BINARY_QEMU_SYSTEM_ARM_INTERFACE,
     }, {
         .name          = MACHINE_TYPE_NAME("ast2600-evb"),
         .parent        = TYPE_ASPEED_MACHINE,
         .class_init    = aspeed_machine_ast2600_evb_class_init,
+        .interfaces    = LEGACY_BINARY_QEMU_SYSTEM_ARM_INTERFACE,
     }, {
         .name          = MACHINE_TYPE_NAME("yosemitev2-bmc"),
         .parent        = TYPE_ASPEED_MACHINE,
         .class_init    = aspeed_machine_yosemitev2_class_init,
+        .interfaces    = LEGACY_BINARY_QEMU_SYSTEM_ARM_INTERFACE,
     }, {
         .name          = MACHINE_TYPE_NAME("tiogapass-bmc"),
         .parent        = TYPE_ASPEED_MACHINE,
         .class_init    = aspeed_machine_tiogapass_class_init,
+        .interfaces    = LEGACY_BINARY_QEMU_SYSTEM_ARM_INTERFACE,
     }, {
         .name          = MACHINE_TYPE_NAME("g220a-bmc"),
         .parent        = TYPE_ASPEED_MACHINE,
         .class_init    = aspeed_machine_g220a_class_init,
+        .interfaces    = LEGACY_BINARY_QEMU_SYSTEM_ARM_INTERFACE,
     }, {
         .name          = MACHINE_TYPE_NAME("qcom-dc-scm-v1-bmc"),
         .parent        = TYPE_ASPEED_MACHINE,
         .class_init    = aspeed_machine_qcom_dc_scm_v1_class_init,
+        .interfaces    = LEGACY_BINARY_QEMU_SYSTEM_ARM_INTERFACE,
     }, {
         .name          = MACHINE_TYPE_NAME("qcom-firework-bmc"),
         .parent        = TYPE_ASPEED_MACHINE,
         .class_init    = aspeed_machine_qcom_firework_class_init,
+        .interfaces    = LEGACY_BINARY_QEMU_SYSTEM_ARM_INTERFACE,
     }, {
         .name          = MACHINE_TYPE_NAME("fp5280g2-bmc"),
         .parent        = TYPE_ASPEED_MACHINE,
         .class_init    = aspeed_machine_fp5280g2_class_init,
+        .interfaces    = LEGACY_BINARY_QEMU_SYSTEM_ARM_INTERFACE,
     }, {
         .name          = MACHINE_TYPE_NAME("quanta-q71l-bmc"),
         .parent        = TYPE_ASPEED_MACHINE,
         .class_init    = aspeed_machine_quanta_q71l_class_init,
+        .interfaces    = LEGACY_BINARY_QEMU_SYSTEM_ARM_INTERFACE,
     }, {
         .name          = MACHINE_TYPE_NAME("rainier-bmc"),
         .parent        = TYPE_ASPEED_MACHINE,
         .class_init    = aspeed_machine_rainier_class_init,
+        .interfaces    = LEGACY_BINARY_QEMU_SYSTEM_ARM_INTERFACE,
     }, {
         .name          = MACHINE_TYPE_NAME("fuji-bmc"),
         .parent        = TYPE_ASPEED_MACHINE,
         .class_init    = aspeed_machine_fuji_class_init,
+        .interfaces    = LEGACY_BINARY_QEMU_SYSTEM_ARM_INTERFACE,
     }, {
         .name          = MACHINE_TYPE_NAME("bletchley-bmc"),
         .parent        = TYPE_ASPEED_MACHINE,
         .class_init    = aspeed_machine_bletchley_class_init,
+        .interfaces    = LEGACY_BINARY_QEMU_SYSTEM_ARM_INTERFACE,
     }, {
         .name          = MACHINE_TYPE_NAME("fby35-bmc"),
         .parent        = MACHINE_TYPE_NAME("ast2600-evb"),
         .class_init    = aspeed_machine_fby35_class_init,
+        .interfaces    = LEGACY_BINARY_QEMU_SYSTEM_ARM_INTERFACE,
     }, {
         .name           = MACHINE_TYPE_NAME("ast1030-evb"),
         .parent         = TYPE_ASPEED_MACHINE,
         .class_init     = aspeed_minibmc_machine_ast1030_evb_class_init,
-#ifdef TARGET_AARCH64
+        .interfaces     = LEGACY_BINARY_QEMU_SYSTEM_ARM_INTERFACE,
     }, {
         .name          = MACHINE_TYPE_NAME("ast2700a0-evb"),
         .parent        = TYPE_ASPEED_MACHINE,
         .class_init    = aspeed_machine_ast2700a0_evb_class_init,
-        }, {
+        .interfaces    = LEGACY_BINARY_QEMU_SYSTEM_AARCH64_INTERFACE,
+    }, {
         .name          = MACHINE_TYPE_NAME("ast2700a1-evb"),
         .parent        = TYPE_ASPEED_MACHINE,
         .class_init    = aspeed_machine_ast2700a1_evb_class_init,
-#endif
+        .interfaces    = LEGACY_BINARY_QEMU_SYSTEM_AARCH64_INTERFACE,
     }, {
         .name          = TYPE_ASPEED_MACHINE,
         .parent        = TYPE_MACHINE,
-- 
2.47.1

[RFC PATCH-for-10.1 06/39] hw/arm/aspeed: Build objects once

[Philippe Mathieu-Daudé]

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
 hw/arm/meson.build | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/hw/arm/meson.build b/hw/arm/meson.build
index 09b1cfe5b57..f76e7fb229f 100644
--- a/hw/arm/meson.build
+++ b/hw/arm/meson.build
@@ -39,15 +39,15 @@ arm_common_ss.add(when: 'CONFIG_XLNX_VERSAL', if_true: files('xlnx-versal.c', 'x
 arm_common_ss.add(when: 'CONFIG_FSL_IMX25', if_true: files('fsl-imx25.c', 'imx25_pdk.c'))
 arm_common_ss.add(when: 'CONFIG_FSL_IMX31', if_true: files('fsl-imx31.c', 'kzm.c'))
 arm_common_ss.add(when: 'CONFIG_FSL_IMX6', if_true: files('fsl-imx6.c'))
-arm_ss.add(when: 'CONFIG_ASPEED_SOC', if_true: files(
+arm_common_ss.add(when: 'CONFIG_ASPEED_SOC', if_true: files(
   'aspeed.c',
   'aspeed_soc_common.c',
   'aspeed_ast2400.c',
   'aspeed_ast2600.c',
   'aspeed_ast10x0.c',
+  'aspeed_ast27x0.c',
   'aspeed_eeprom.c',
   'fby35.c'))
-arm_common_ss.add(when: ['CONFIG_ASPEED_SOC', 'TARGET_AARCH64'], if_true: files('aspeed_ast27x0.c'))
 arm_common_ss.add(when: 'CONFIG_MPS2', if_true: files('mps2.c'))
 arm_common_ss.add(when: 'CONFIG_MPS2', if_true: files('mps2-tz.c'))
 arm_common_ss.add(when: 'CONFIG_MSF2', if_true: files('msf2-soc.c'))
-- 
2.47.1

[RFC PATCH-for-10.1 07/39] hw/arm/raspi: Filter machine types for binary

[Philippe Mathieu-Daudé]

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
 hw/arm/bcm2836.c | 4 ----
 hw/arm/raspi.c   | 9 +++++----
 hw/arm/raspi4b.c | 1 +
 3 files changed, 6 insertions(+), 8 deletions(-)

diff --git a/hw/arm/bcm2836.c b/hw/arm/bcm2836.c
index 95e16806fa1..7dd81e8e0f9 100644
--- a/hw/arm/bcm2836.c
+++ b/hw/arm/bcm2836.c
@@ -195,7 +195,6 @@ static void bcm2836_class_init(ObjectClass *oc, void *data)
     dc->realize = bcm2836_realize;
 };
 
-#ifdef TARGET_AARCH64
 static void bcm2837_class_init(ObjectClass *oc, void *data)
 {
     DeviceClass *dc = DEVICE_CLASS(oc);
@@ -208,7 +207,6 @@ static void bcm2837_class_init(ObjectClass *oc, void *data)
     bc->clusterid = 0x0;
     dc->realize = bcm2836_realize;
 };
-#endif
 
 static const TypeInfo bcm283x_types[] = {
     {
@@ -219,12 +217,10 @@ static const TypeInfo bcm283x_types[] = {
         .name           = TYPE_BCM2836,
         .parent         = TYPE_BCM283X,
         .class_init     = bcm2836_class_init,
-#ifdef TARGET_AARCH64
     }, {
         .name           = TYPE_BCM2837,
         .parent         = TYPE_BCM283X,
         .class_init     = bcm2837_class_init,
-#endif
     }, {
         .name           = TYPE_BCM283X,
         .parent         = TYPE_BCM283X_BASE,
diff --git a/hw/arm/raspi.c b/hw/arm/raspi.c
index dce35ca11aa..b049c6035d4 100644
--- a/hw/arm/raspi.c
+++ b/hw/arm/raspi.c
@@ -367,7 +367,6 @@ static void raspi2b_machine_class_init(ObjectClass *oc, void *data)
     raspi_machine_class_init(mc, rmc->board_rev);
 };
 
-#ifdef TARGET_AARCH64
 static void raspi3ap_machine_class_init(ObjectClass *oc, void *data)
 {
     MachineClass *mc = MACHINE_CLASS(oc);
@@ -387,31 +386,33 @@ static void raspi3b_machine_class_init(ObjectClass *oc, void *data)
     rmc->board_rev = 0xa02082;
     raspi_machine_class_init(mc, rmc->board_rev);
 };
-#endif /* TARGET_AARCH64 */
 
 static const TypeInfo raspi_machine_types[] = {
     {
         .name           = MACHINE_TYPE_NAME("raspi0"),
         .parent         = TYPE_RASPI_MACHINE,
         .class_init     = raspi0_machine_class_init,
+        .interfaces     = LEGACY_BINARY_QEMU_SYSTEM_ARM_INTERFACE,
     }, {
         .name           = MACHINE_TYPE_NAME("raspi1ap"),
         .parent         = TYPE_RASPI_MACHINE,
         .class_init     = raspi1ap_machine_class_init,
+        .interfaces     = LEGACY_BINARY_QEMU_SYSTEM_ARM_INTERFACE,
     }, {
         .name           = MACHINE_TYPE_NAME("raspi2b"),
         .parent         = TYPE_RASPI_MACHINE,
         .class_init     = raspi2b_machine_class_init,
-#ifdef TARGET_AARCH64
+        .interfaces     = LEGACY_BINARY_QEMU_SYSTEM_ARM_INTERFACE,
     }, {
         .name           = MACHINE_TYPE_NAME("raspi3ap"),
         .parent         = TYPE_RASPI_MACHINE,
         .class_init     = raspi3ap_machine_class_init,
+        .interfaces     = LEGACY_BINARY_QEMU_SYSTEM_AARCH64_INTERFACE,
     }, {
         .name           = MACHINE_TYPE_NAME("raspi3b"),
         .parent         = TYPE_RASPI_MACHINE,
         .class_init     = raspi3b_machine_class_init,
-#endif
+        .interfaces     = LEGACY_BINARY_QEMU_SYSTEM_AARCH64_INTERFACE,
     }, {
         .name           = TYPE_RASPI_MACHINE,
         .parent         = TYPE_RASPI_BASE_MACHINE,
diff --git a/hw/arm/raspi4b.c b/hw/arm/raspi4b.c
index f6de103a3e1..12c7ed42ced 100644
--- a/hw/arm/raspi4b.c
+++ b/hw/arm/raspi4b.c
@@ -127,6 +127,7 @@ static const TypeInfo raspi4b_machine_type = {
     .parent         = TYPE_RASPI_BASE_MACHINE,
     .instance_size  = sizeof(Raspi4bMachineState),
     .class_init     = raspi4b_machine_class_init,
+    .interfaces     = LEGACY_BINARY_QEMU_SYSTEM_AARCH64_INTERFACE,
 };
 
 static void raspi4b_machine_register_type(void)
-- 
2.47.1

[RFC PATCH-for-10.1 08/39] hw/arm/raspi: Build objects once

[Philippe Mathieu-Daudé]

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
 hw/arm/meson.build | 8 ++++++--
 1 file changed, 6 insertions(+), 2 deletions(-)

diff --git a/hw/arm/meson.build b/hw/arm/meson.build
index f76e7fb229f..f52034ff6a2 100644
--- a/hw/arm/meson.build
+++ b/hw/arm/meson.build
@@ -27,8 +27,12 @@ arm_common_ss.add(when: 'CONFIG_OMAP', if_true: files('omap1.c'))
 arm_common_ss.add(when: 'CONFIG_ALLWINNER_A10', if_true: files('allwinner-a10.c', 'cubieboard.c'))
 arm_common_ss.add(when: 'CONFIG_ALLWINNER_H3', if_true: files('allwinner-h3.c', 'orangepi.c'))
 arm_common_ss.add(when: 'CONFIG_ALLWINNER_R40', if_true: files('allwinner-r40.c', 'bananapi_m2u.c'))
-arm_ss.add(when: 'CONFIG_RASPI', if_true: files('bcm2836.c', 'raspi.c'))
-arm_common_ss.add(when: ['CONFIG_RASPI', 'TARGET_AARCH64'], if_true: files('bcm2838.c', 'raspi4b.c'))
+arm_common_ss.add(when: 'CONFIG_RASPI', if_true: files(
+  'bcm2836.c',
+  'bcm2838.c',
+  'raspi.c',
+  'raspi4b.c',
+))
 arm_common_ss.add(when: 'CONFIG_STM32F100_SOC', if_true: files('stm32f100_soc.c'))
 arm_common_ss.add(when: 'CONFIG_STM32F205_SOC', if_true: files('stm32f205_soc.c'))
 arm_common_ss.add(when: 'CONFIG_STM32F405_SOC', if_true: files('stm32f405_soc.c'))
-- 
2.47.1

[RFC PATCH-for-10.1 09/39] target/arm/cpregs: Include missing 'target/arm/cpu.h' header

[Philippe Mathieu-Daudé]

CPReadFn type definitions use the CPUARMState type, itself
declared in "cpu.h". Include this file in order to avoid when
refactoring headers:

  ../target/arm/cpregs.h:241:27: error: unknown type name 'CPUARMState'
  typedef uint64_t CPReadFn(CPUARMState *env, const ARMCPRegInfo *opaque);
                            ^

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
 target/arm/cpregs.h | 1 +
 1 file changed, 1 insertion(+)

diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h
index 2183de8eda6..c1a7ae37356 100644
--- a/target/arm/cpregs.h
+++ b/target/arm/cpregs.h
@@ -23,6 +23,7 @@
 
 #include "hw/registerfields.h"
 #include "target/arm/kvm-consts.h"
+#include "cpu.h"
 
 /*
  * ARMCPRegInfo type field bits:
-- 
2.47.1

[RFC PATCH-for-10.1 10/39] hw/arm/boot: Include missing 'system/memory.h' header

[Philippe Mathieu-Daudé]

default_reset_secondary() uses address_space_stl_notdirty(),
itself declared in "system/memory.h". Include this header in
order to avoid when refactoring headers:

  ../hw/arm/boot.c:281:5: error: implicit declaration of function 'address_space_stl_notdirty' is invalid in C99 [-Werror,-Wimplicit-function-declaration]
    address_space_stl_notdirty(as, info->smp_bootreg_addr,
    ^

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
 hw/arm/boot.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/hw/arm/boot.c b/hw/arm/boot.c
index f94b940bc31..79afb51b8a5 100644
--- a/hw/arm/boot.c
+++ b/hw/arm/boot.c
@@ -19,6 +19,7 @@
 #include "system/kvm.h"
 #include "system/tcg.h"
 #include "system/system.h"
+#include "system/memory.h"
 #include "system/numa.h"
 #include "hw/boards.h"
 #include "system/reset.h"
-- 
2.47.1

[RFC PATCH-for-10.1 11/39] hw/arm: Use full "target/arm/cpu.h" path to include target's "cpu.h"

[Philippe Mathieu-Daudé]

We would like to get rid of '-I target/$ARCH/' in the CPPFLAGS.
Use the full path to "cpu.h": "target/arm/cpu.h".

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
 include/hw/arm/digic.h      | 2 +-
 include/hw/arm/fsl-imx6.h   | 2 +-
 include/hw/arm/fsl-imx6ul.h | 2 +-
 include/hw/arm/fsl-imx7.h   | 2 +-
 include/hw/arm/fsl-imx8mp.h | 2 +-
 5 files changed, 5 insertions(+), 5 deletions(-)

diff --git a/include/hw/arm/digic.h b/include/hw/arm/digic.h
index 8f2735c284f..646802806e0 100644
--- a/include/hw/arm/digic.h
+++ b/include/hw/arm/digic.h
@@ -18,7 +18,7 @@
 #ifndef HW_ARM_DIGIC_H
 #define HW_ARM_DIGIC_H
 
-#include "cpu.h"
+#include "target/arm/cpu.h"
 #include "hw/timer/digic-timer.h"
 #include "hw/char/digic-uart.h"
 #include "qom/object.h"
diff --git a/include/hw/arm/fsl-imx6.h b/include/hw/arm/fsl-imx6.h
index 124bbd478fd..0ac145cf6ba 100644
--- a/include/hw/arm/fsl-imx6.h
+++ b/include/hw/arm/fsl-imx6.h
@@ -35,7 +35,7 @@
 #include "hw/pci-host/designware.h"
 #include "hw/or-irq.h"
 #include "system/memory.h"
-#include "cpu.h"
+#include "target/arm/cpu.h"
 #include "qom/object.h"
 
 #define TYPE_FSL_IMX6 "fsl-imx6"
diff --git a/include/hw/arm/fsl-imx6ul.h b/include/hw/arm/fsl-imx6ul.h
index 4e3209b25b2..f8f9c249a23 100644
--- a/include/hw/arm/fsl-imx6ul.h
+++ b/include/hw/arm/fsl-imx6ul.h
@@ -34,7 +34,7 @@
 #include "hw/usb/chipidea.h"
 #include "hw/usb/imx-usb-phy.h"
 #include "system/memory.h"
-#include "cpu.h"
+#include "target/arm/cpu.h"
 #include "qom/object.h"
 #include "qemu/units.h"
 
diff --git a/include/hw/arm/fsl-imx7.h b/include/hw/arm/fsl-imx7.h
index aa7818c4999..6aedd2b80b5 100644
--- a/include/hw/arm/fsl-imx7.h
+++ b/include/hw/arm/fsl-imx7.h
@@ -37,7 +37,7 @@
 #include "hw/pci-host/designware.h"
 #include "hw/usb/chipidea.h"
 #include "hw/or-irq.h"
-#include "cpu.h"
+#include "target/arm/cpu.h"
 #include "qom/object.h"
 #include "qemu/units.h"
 
diff --git a/include/hw/arm/fsl-imx8mp.h b/include/hw/arm/fsl-imx8mp.h
index bc97fc416eb..f20f9e53187 100644
--- a/include/hw/arm/fsl-imx8mp.h
+++ b/include/hw/arm/fsl-imx8mp.h
@@ -9,7 +9,7 @@
 #ifndef FSL_IMX8MP_H
 #define FSL_IMX8MP_H
 
-#include "cpu.h"
+#include "target/arm/cpu.h"
 #include "hw/char/imx_serial.h"
 #include "hw/gpio/imx_gpio.h"
 #include "hw/i2c/imx_i2c.h"
-- 
2.47.1

[RFC PATCH-for-10.1 12/39] target/arm/cpu-features: Include missing 'cpu.h' header

[Philippe Mathieu-Daudé]

"target/arm/cpu-features.h" dereferences the ARMISARegisters
structure, which is defined in "cpu.h". Include the latter to
avoid when refactoring unrelated headers:

  In file included from target/arm/internals.h:33:
  target/arm/cpu-features.h:45:54: error: unknown type name 'ARMISARegisters'
     45 | static inline bool isar_feature_aa32_thumb_div(const ARMISARegisters *id)
        |                                                      ^
  target/arm/cpu-features.h:47:12: error: use of undeclared identifier 'R_ID_ISAR0_DIVIDE_SHIFT'
     47 |     return FIELD_EX32(id->id_isar0, ID_ISAR0, DIVIDE) != 0;
        |            ^

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
---
 target/arm/cpu-features.h | 1 +
 1 file changed, 1 insertion(+)

diff --git a/target/arm/cpu-features.h b/target/arm/cpu-features.h
index 525e4cee12f..4452e7c21e3 100644
--- a/target/arm/cpu-features.h
+++ b/target/arm/cpu-features.h
@@ -22,6 +22,7 @@
 
 #include "hw/registerfields.h"
 #include "qemu/host-utils.h"
+#include "cpu.h"
 
 /*
  * Naming convention for isar_feature functions:
-- 
2.47.1

[RFC PATCH-for-10.1 13/39] target/arm/qmp: Include missing 'cpu.h' header

[Philippe Mathieu-Daudé]

arm-qmp-cmds.c uses ARM_MAX_VQ, which is defined in "cpu.h".
Include the latter to avoid when refactoring unrelated headers:

  target/arm/arm-qmp-cmds.c:83:19: error: use of undeclared identifier 'ARM_MAX_VQ'
     83 | QEMU_BUILD_BUG_ON(ARM_MAX_VQ > 16);
        |                   ^

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
---
 target/arm/arm-qmp-cmds.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/target/arm/arm-qmp-cmds.c b/target/arm/arm-qmp-cmds.c
index 883c0a0e8cc..d654be2a619 100644
--- a/target/arm/arm-qmp-cmds.c
+++ b/target/arm/arm-qmp-cmds.c
@@ -30,6 +30,7 @@
 #include "qapi/qapi-commands-misc-target.h"
 #include "qobject/qdict.h"
 #include "qom/qom-qobject.h"
+#include "cpu.h"
 
 static GICCapability *gic_cap_new(int version)
 {
-- 
2.47.1

[RFC PATCH-for-10.1 14/39] target/arm/kvm: Include missing 'cpu-qom.h' header

[Philippe Mathieu-Daudé]

ARMCPU typedef is declared in "cpu-qom.h". Include it in
order to avoid when refactoring unrelated headers:

  target/arm/kvm_arm.h:54:29: error: unknown type name 'ARMCPU'
     54 | bool write_list_to_kvmstate(ARMCPU *cpu, int level);
        |                             ^

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
---
 target/arm/kvm_arm.h | 1 +
 1 file changed, 1 insertion(+)

diff --git a/target/arm/kvm_arm.h b/target/arm/kvm_arm.h
index 05c3de8cd46..2db2f060e6a 100644
--- a/target/arm/kvm_arm.h
+++ b/target/arm/kvm_arm.h
@@ -12,6 +12,7 @@
 #define QEMU_KVM_ARM_H
 
 #include "system/kvm.h"
+#include "target/arm/cpu-qom.h"
 
 #define KVM_ARM_VGIC_V2   (1 << 0)
 #define KVM_ARM_VGIC_V3   (1 << 1)
-- 
2.47.1

[RFC PATCH-for-10.1 15/39] target/arm/hvf: Include missing 'cpu-qom.h' header

[Philippe Mathieu-Daudé]

ARMCPU typedef is declared in "cpu-qom.h". Include it in
order to avoid when refactoring unrelated headers:

  target/arm/hvf_arm.h:23:41: error: unknown type name 'ARMCPU'
     23 | void hvf_arm_set_cpu_features_from_host(ARMCPU *cpu);
        |                                         ^

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
---
 target/arm/hvf_arm.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/target/arm/hvf_arm.h b/target/arm/hvf_arm.h
index 26c717b3826..ee5545f2d10 100644
--- a/target/arm/hvf_arm.h
+++ b/target/arm/hvf_arm.h
@@ -11,7 +11,7 @@
 #ifndef QEMU_HVF_ARM_H
 #define QEMU_HVF_ARM_H
 
-#include "cpu.h"
+#include "target/arm/cpu-qom.h"
 
 /**
  * hvf_arm_init_debug() - initialize guest debug capabilities
-- 
2.47.1

[RFC PATCH-for-10.1 16/39] hw/arm: Remove unnecessary 'cpu.h' header

[Philippe Mathieu-Daudé]

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
---
 hw/arm/exynos4210.c | 1 -
 hw/arm/highbank.c   | 1 -
 hw/arm/mps3r.c      | 1 -
 hw/arm/smmuv3.c     | 1 -
 4 files changed, 4 deletions(-)

diff --git a/hw/arm/exynos4210.c b/hw/arm/exynos4210.c
index b452470598b..04439364370 100644
--- a/hw/arm/exynos4210.c
+++ b/hw/arm/exynos4210.c
@@ -24,7 +24,6 @@
 #include "qemu/osdep.h"
 #include "qapi/error.h"
 #include "exec/tswap.h"
-#include "cpu.h"
 #include "hw/cpu/a9mpcore.h"
 #include "hw/irq.h"
 #include "system/blockdev.h"
diff --git a/hw/arm/highbank.c b/hw/arm/highbank.c
index ea3621e4f87..0caa08631ad 100644
--- a/hw/arm/highbank.c
+++ b/hw/arm/highbank.c
@@ -35,7 +35,6 @@
 #include "hw/cpu/a15mpcore.h"
 #include "qemu/log.h"
 #include "qom/object.h"
-#include "cpu.h"
 #include "target/arm/cpu-qom.h"
 
 #define SMP_BOOT_ADDR           0x100
diff --git a/hw/arm/mps3r.c b/hw/arm/mps3r.c
index e9abbf00b43..604f6845fde 100644
--- a/hw/arm/mps3r.c
+++ b/hw/arm/mps3r.c
@@ -29,7 +29,6 @@
 #include "qapi/error.h"
 #include "qobject/qlist.h"
 #include "system/address-spaces.h"
-#include "cpu.h"
 #include "system/system.h"
 #include "hw/boards.h"
 #include "hw/or-irq.h"
diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c
index 4362ae6aa1c..df3f5a707a9 100644
--- a/hw/arm/smmuv3.c
+++ b/hw/arm/smmuv3.c
@@ -24,7 +24,6 @@
 #include "hw/qdev-properties.h"
 #include "hw/qdev-core.h"
 #include "hw/pci/pci.h"
-#include "cpu.h"
 #include "exec/target_page.h"
 #include "trace.h"
 #include "qemu/log.h"
-- 
2.47.1

[RFC PATCH-for-10.1 17/39] target/arm: Restrict inclusion of 'multiprocessing.h'

[Philippe Mathieu-Daudé]

Only cpu.c requires "multiprocessing.h" definitions so far.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
---
 target/arm/cpu.h | 1 -
 target/arm/cpu.c | 1 +
 2 files changed, 1 insertion(+), 1 deletion(-)

diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index 3705b34285b..1a1ae229e1d 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -30,7 +30,6 @@
 #include "exec/gdbstub.h"
 #include "exec/page-protection.h"
 #include "qapi/qapi-types-common.h"
-#include "target/arm/multiprocessing.h"
 #include "target/arm/gtimer.h"
 
 #define EXCP_UDEF            1   /* undefined instruction */
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index b1aa482c726..6f62745d7f6 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -53,6 +53,7 @@
 #include "qemu/target_info-qom.h"
 #include "target/arm/cpu-qom.h"
 #include "target/arm/gtimer.h"
+#include "target/arm/multiprocessing.h"
 
 static void arm_cpu_set_pc(CPUState *cs, vaddr value)
 {
-- 
2.47.1

[RFC PATCH-for-10.1 18/39] target/arm: Move some definitions from 'cpu.h' to 'multiprocessing.h'

[Philippe Mathieu-Daudé]

arm_build_mp_affinity() and affinity mask definitionss are
related to multiprocessing. Move them to "multiprocessing.h",
including this header when necessary.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
---
 target/arm/cpu.h             | 17 -----------------
 target/arm/multiprocessing.h | 18 ++++++++++++++++++
 hw/arm/aspeed_ast2600.c      |  1 +
 hw/arm/aspeed_ast27x0.c      |  1 +
 hw/arm/exynos4210.c          |  1 +
 hw/arm/npcm8xx.c             |  1 +
 hw/arm/sbsa-ref.c            |  1 +
 hw/vmapple/vmapple.c         |  1 +
 target/arm/kvm.c             |  1 +
 9 files changed, 25 insertions(+), 17 deletions(-)

diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index 1a1ae229e1d..0db7292698c 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -1158,23 +1158,6 @@ void gt_rme_post_el_change(ARMCPU *cpu, void *opaque);
 
 void arm_cpu_post_init(Object *obj);
 
-#define ARM_AFF0_SHIFT 0
-#define ARM_AFF0_MASK  (0xFFULL << ARM_AFF0_SHIFT)
-#define ARM_AFF1_SHIFT 8
-#define ARM_AFF1_MASK  (0xFFULL << ARM_AFF1_SHIFT)
-#define ARM_AFF2_SHIFT 16
-#define ARM_AFF2_MASK  (0xFFULL << ARM_AFF2_SHIFT)
-#define ARM_AFF3_SHIFT 32
-#define ARM_AFF3_MASK  (0xFFULL << ARM_AFF3_SHIFT)
-#define ARM_DEFAULT_CPUS_PER_CLUSTER 8
-
-#define ARM32_AFFINITY_MASK (ARM_AFF0_MASK | ARM_AFF1_MASK | ARM_AFF2_MASK)
-#define ARM64_AFFINITY_MASK \
-    (ARM_AFF0_MASK | ARM_AFF1_MASK | ARM_AFF2_MASK | ARM_AFF3_MASK)
-#define ARM64_AFFINITY_INVALID (~ARM64_AFFINITY_MASK)
-
-uint64_t arm_build_mp_affinity(int idx, uint8_t clustersz);
-
 #ifndef CONFIG_USER_ONLY
 extern const VMStateDescription vmstate_arm_cpu;
 
diff --git a/target/arm/multiprocessing.h b/target/arm/multiprocessing.h
index 81715d345c2..8eec79b11d8 100644
--- a/target/arm/multiprocessing.h
+++ b/target/arm/multiprocessing.h
@@ -11,6 +11,24 @@
 
 #include "target/arm/cpu-qom.h"
 
+#define ARM_AFF0_SHIFT 0
+#define ARM_AFF0_MASK  (0xFFULL << ARM_AFF0_SHIFT)
+#define ARM_AFF1_SHIFT 8
+#define ARM_AFF1_MASK  (0xFFULL << ARM_AFF1_SHIFT)
+#define ARM_AFF2_SHIFT 16
+#define ARM_AFF2_MASK  (0xFFULL << ARM_AFF2_SHIFT)
+#define ARM_AFF3_SHIFT 32
+#define ARM_AFF3_MASK  (0xFFULL << ARM_AFF3_SHIFT)
+#define ARM_DEFAULT_CPUS_PER_CLUSTER 8
+
+#define ARM32_AFFINITY_MASK \
+            (ARM_AFF0_MASK|ARM_AFF1_MASK|ARM_AFF2_MASK)
+#define ARM64_AFFINITY_MASK \
+            (ARM_AFF0_MASK|ARM_AFF1_MASK|ARM_AFF2_MASK|ARM_AFF3_MASK)
+#define ARM64_AFFINITY_INVALID (~ARM64_AFFINITY_MASK)
+
+uint64_t arm_build_mp_affinity(int idx, uint8_t clustersz);
+
 uint64_t arm_cpu_mp_affinity(ARMCPU *cpu);
 
 #endif
diff --git a/hw/arm/aspeed_ast2600.c b/hw/arm/aspeed_ast2600.c
index 1f994ba26c6..4438402340b 100644
--- a/hw/arm/aspeed_ast2600.c
+++ b/hw/arm/aspeed_ast2600.c
@@ -17,6 +17,7 @@
 #include "net/net.h"
 #include "system/system.h"
 #include "target/arm/cpu-qom.h"
+#include "target/arm/multiprocessing.h"
 
 #define ASPEED_SOC_IOMEM_SIZE       0x00200000
 #define ASPEED_SOC_DPMCU_SIZE       0x00040000
diff --git a/hw/arm/aspeed_ast27x0.c b/hw/arm/aspeed_ast27x0.c
index dce7255a2c0..37bfeef304d 100644
--- a/hw/arm/aspeed_ast27x0.c
+++ b/hw/arm/aspeed_ast27x0.c
@@ -22,6 +22,7 @@
 #include "hw/intc/arm_gicv3.h"
 #include "qobject/qlist.h"
 #include "qemu/log.h"
+#include "target/arm/multiprocessing.h"
 
 static const hwaddr aspeed_soc_ast2700_memmap[] = {
     [ASPEED_DEV_SRAM]      =  0x10000000,
diff --git a/hw/arm/exynos4210.c b/hw/arm/exynos4210.c
index 04439364370..01e6e2fb052 100644
--- a/hw/arm/exynos4210.c
+++ b/hw/arm/exynos4210.c
@@ -36,6 +36,7 @@
 #include "hw/sd/sdhci.h"
 #include "hw/usb/hcd-ehci.h"
 #include "target/arm/cpu-qom.h"
+#include "target/arm/multiprocessing.h"
 
 #define EXYNOS4210_CHIPID_ADDR         0x10000000
 
diff --git a/hw/arm/npcm8xx.c b/hw/arm/npcm8xx.c
index f182accc47c..3987e55355b 100644
--- a/hw/arm/npcm8xx.c
+++ b/hw/arm/npcm8xx.c
@@ -29,6 +29,7 @@
 #include "qapi/error.h"
 #include "qemu/units.h"
 #include "system/system.h"
+#include "target/arm/multiprocessing.h"
 
 /*
  * This covers the whole MMIO space. We'll use this to catch any MMIO accesses
diff --git a/hw/arm/sbsa-ref.c b/hw/arm/sbsa-ref.c
index 112cbbf29e6..90fbb56ba7a 100644
--- a/hw/arm/sbsa-ref.c
+++ b/hw/arm/sbsa-ref.c
@@ -52,6 +52,7 @@
 #include "qom/object.h"
 #include "target/arm/cpu-qom.h"
 #include "target/arm/gtimer.h"
+#include "target/arm/multiprocessing.h"
 
 #define RAMLIMIT_GB 8192
 #define RAMLIMIT_BYTES (RAMLIMIT_GB * GiB)
diff --git a/hw/vmapple/vmapple.c b/hw/vmapple/vmapple.c
index fa117bf1511..9bb5b0553a2 100644
--- a/hw/vmapple/vmapple.c
+++ b/hw/vmapple/vmapple.c
@@ -51,6 +51,7 @@
 #include "system/reset.h"
 #include "system/runstate.h"
 #include "system/system.h"
+#include "target/arm/multiprocessing.h"
 
 struct VMAppleMachineState {
     MachineState parent;
diff --git a/target/arm/kvm.c b/target/arm/kvm.c
index 97de8c7e939..a28acdecf3e 100644
--- a/target/arm/kvm.c
+++ b/target/arm/kvm.c
@@ -39,6 +39,7 @@
 #include "hw/acpi/acpi.h"
 #include "hw/acpi/ghes.h"
 #include "target/arm/gtimer.h"
+#include "target/arm/multiprocessing.h"
 #include "migration/blocker.h"
 
 const KVMCapabilityInfo kvm_arch_required_capabilities[] = {
-- 
2.47.1

[RFC PATCH-for-10.1 19/39] hw/arm: Include missing 'target/arm/gtimer.h' header

[Philippe Mathieu-Daudé]

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
---
 hw/arm/aspeed_ast27x0.c    | 1 +
 hw/arm/bcm2838.c           | 1 +
 hw/arm/exynos4210.c        | 1 +
 hw/arm/fsl-imx8mp.c        | 1 +
 hw/arm/mps3r.c             | 1 +
 hw/arm/npcm8xx.c           | 1 +
 hw/vmapple/vmapple.c       | 1 +
 target/arm/tcg/op_helper.c | 1 +
 8 files changed, 8 insertions(+)

diff --git a/hw/arm/aspeed_ast27x0.c b/hw/arm/aspeed_ast27x0.c
index 37bfeef304d..5c2481225dd 100644
--- a/hw/arm/aspeed_ast27x0.c
+++ b/hw/arm/aspeed_ast27x0.c
@@ -22,6 +22,7 @@
 #include "hw/intc/arm_gicv3.h"
 #include "qobject/qlist.h"
 #include "qemu/log.h"
+#include "target/arm/gtimer.h"
 #include "target/arm/multiprocessing.h"
 
 static const hwaddr aspeed_soc_ast2700_memmap[] = {
diff --git a/hw/arm/bcm2838.c b/hw/arm/bcm2838.c
index ddb7c5f757a..38d9b785a75 100644
--- a/hw/arm/bcm2838.c
+++ b/hw/arm/bcm2838.c
@@ -12,6 +12,7 @@
 #include "hw/arm/raspi_platform.h"
 #include "hw/sysbus.h"
 #include "hw/arm/bcm2838.h"
+#include "target/arm/gtimer.h"
 #include "trace.h"
 
 #define GIC400_MAINTENANCE_IRQ      9
diff --git a/hw/arm/exynos4210.c b/hw/arm/exynos4210.c
index 01e6e2fb052..ca40df3db75 100644
--- a/hw/arm/exynos4210.c
+++ b/hw/arm/exynos4210.c
@@ -36,6 +36,7 @@
 #include "hw/sd/sdhci.h"
 #include "hw/usb/hcd-ehci.h"
 #include "target/arm/cpu-qom.h"
+#include "target/arm/gtimer.h"
 #include "target/arm/multiprocessing.h"
 
 #define EXYNOS4210_CHIPID_ADDR         0x10000000
diff --git a/hw/arm/fsl-imx8mp.c b/hw/arm/fsl-imx8mp.c
index 2cf5eeaf313..180feca9d80 100644
--- a/hw/arm/fsl-imx8mp.c
+++ b/hw/arm/fsl-imx8mp.c
@@ -17,6 +17,7 @@
 #include "hw/boards.h"
 #include "system/system.h"
 #include "target/arm/cpu-qom.h"
+#include "target/arm/gtimer.h"
 #include "qapi/error.h"
 #include "qobject/qlist.h"
 
diff --git a/hw/arm/mps3r.c b/hw/arm/mps3r.c
index 604f6845fde..37c0de28a92 100644
--- a/hw/arm/mps3r.c
+++ b/hw/arm/mps3r.c
@@ -47,6 +47,7 @@
 #include "hw/ssi/pl022.h"
 #include "hw/timer/cmsdk-apb-dualtimer.h"
 #include "hw/watchdog/cmsdk-apb-watchdog.h"
+#include "target/arm/gtimer.h"
 
 /* Define the layout of RAM and ROM in a board */
 typedef struct RAMInfo {
diff --git a/hw/arm/npcm8xx.c b/hw/arm/npcm8xx.c
index 3987e55355b..2f11bc53a86 100644
--- a/hw/arm/npcm8xx.c
+++ b/hw/arm/npcm8xx.c
@@ -29,6 +29,7 @@
 #include "qapi/error.h"
 #include "qemu/units.h"
 #include "system/system.h"
+#include "target/arm/gtimer.h"
 #include "target/arm/multiprocessing.h"
 
 /*
diff --git a/hw/vmapple/vmapple.c b/hw/vmapple/vmapple.c
index 9bb5b0553a2..25652b16f0c 100644
--- a/hw/vmapple/vmapple.c
+++ b/hw/vmapple/vmapple.c
@@ -51,6 +51,7 @@
 #include "system/reset.h"
 #include "system/runstate.h"
 #include "system/system.h"
+#include "target/arm/gtimer.h"
 #include "target/arm/multiprocessing.h"
 
 struct VMAppleMachineState {
diff --git a/target/arm/tcg/op_helper.c b/target/arm/tcg/op_helper.c
index 38d49cbb9d8..005f84082af 100644
--- a/target/arm/tcg/op_helper.c
+++ b/target/arm/tcg/op_helper.c
@@ -25,6 +25,7 @@
 #include "cpu-features.h"
 #include "exec/exec-all.h"
 #include "accel/tcg/cpu-ldst.h"
+#include "target/arm/gtimer.h"
 #include "cpregs.h"
 
 #define SIGNBIT (uint32_t)0x80000000
-- 
2.47.1

[RFC PATCH-for-10.1 20/39] target/arm: Extract PSCI definitions to 'psci.h'

[Philippe Mathieu-Daudé]

Extract PSCI definitions (which are not target specific)
to the new "target/arm/psci.h", so code from hw/arm/ can
use them without having to include the target specific
"cpu.h" header.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
---
 include/hw/arm/boot.h      |  3 ++-
 target/arm/cpu.h           |  6 ------
 target/arm/psci.h          | 18 ++++++++++++++++++
 hw/arm/bananapi_m2u.c      |  1 +
 hw/arm/boot.c              |  1 +
 hw/arm/highbank.c          |  1 +
 hw/arm/imx8mp-evk.c        |  1 +
 hw/arm/mcimx6ul-evk.c      |  1 +
 hw/arm/mcimx7d-sabre.c     |  1 +
 hw/arm/orangepi.c          |  1 +
 hw/arm/sbsa-ref.c          |  1 +
 hw/arm/virt-acpi-build.c   |  1 +
 hw/arm/virt.c              |  1 +
 hw/arm/xlnx-versal-virt.c  |  1 +
 hw/arm/xlnx-zcu102.c       |  1 +
 hw/vmapple/vmapple.c       |  1 +
 target/arm/helper.c        |  1 +
 target/arm/hvf/hvf.c       |  1 +
 target/arm/tcg/op_helper.c |  1 +
 target/arm/tcg/psci.c      |  1 +
 20 files changed, 37 insertions(+), 7 deletions(-)
 create mode 100644 target/arm/psci.h

diff --git a/include/hw/arm/boot.h b/include/hw/arm/boot.h
index b12bf61ca81..648fdb88862 100644
--- a/include/hw/arm/boot.h
+++ b/include/hw/arm/boot.h
@@ -12,6 +12,7 @@
 #define HW_ARM_BOOT_H
 
 #include "target/arm/cpu-qom.h"
+//#include "target/arm/psci.h"
 #include "qemu/notify.h"
 
 typedef enum {
@@ -100,7 +101,7 @@ struct arm_boot_info {
      * as the conduit specifies calls should go to (eg guest firmware booted
      * to EL3) then PSCI will not be enabled.
      */
-    int psci_conduit;
+    int psci_conduit;//
     /* Used internally by arm_boot.c */
     int is_linux;
     hwaddr initrd_start;
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index 0db7292698c..930c5366029 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -3104,12 +3104,6 @@ static inline bool bswap_code(bool sctlr_b)
 void cpu_get_tb_cpu_state(CPUARMState *env, vaddr *pc,
                           uint64_t *cs_base, uint32_t *flags);
 
-enum {
-    QEMU_PSCI_CONDUIT_DISABLED = 0,
-    QEMU_PSCI_CONDUIT_SMC = 1,
-    QEMU_PSCI_CONDUIT_HVC = 2,
-};
-
 #ifndef CONFIG_USER_ONLY
 /* Return the address space index to use for a memory access */
 static inline int arm_asidx_from_attrs(CPUState *cs, MemTxAttrs attrs)
diff --git a/target/arm/psci.h b/target/arm/psci.h
new file mode 100644
index 00000000000..8b868dfbb91
--- /dev/null
+++ b/target/arm/psci.h
@@ -0,0 +1,18 @@
+/*
+ * ARM Power State Coordination Interface (PSCI) definitions
+ *
+ *  Copyright (c) 2003 Fabrice Bellard
+ *
+ * SPDX-License-Identifier: LGPL-2.1-or-later
+ */
+
+#ifndef TARGET_ARM_PSCI_H
+#define TARGET_ARM_PSCI_H
+
+enum {
+    QEMU_PSCI_CONDUIT_DISABLED = 0,
+    QEMU_PSCI_CONDUIT_SMC = 1,
+    QEMU_PSCI_CONDUIT_HVC = 2,
+};
+
+#endif
diff --git a/hw/arm/bananapi_m2u.c b/hw/arm/bananapi_m2u.c
index b750a575f72..61e01a38099 100644
--- a/hw/arm/bananapi_m2u.c
+++ b/hw/arm/bananapi_m2u.c
@@ -27,6 +27,7 @@
 #include "hw/qdev-properties.h"
 #include "hw/arm/allwinner-r40.h"
 #include "hw/arm/boot.h"
+#include "target/arm/psci.h"
 
 static struct arm_boot_info bpim2u_binfo;
 
diff --git a/hw/arm/boot.c b/hw/arm/boot.c
index 79afb51b8a5..b81a850819b 100644
--- a/hw/arm/boot.c
+++ b/hw/arm/boot.c
@@ -29,6 +29,7 @@
 #include "qemu/config-file.h"
 #include "qemu/option.h"
 #include "qemu/units.h"
+#include "target/arm/psci.h"
 
 /* Kernel boot protocol is specified in the kernel docs
  * Documentation/arm/Booting and Documentation/arm64/booting.txt
diff --git a/hw/arm/highbank.c b/hw/arm/highbank.c
index 0caa08631ad..16fb2508d30 100644
--- a/hw/arm/highbank.c
+++ b/hw/arm/highbank.c
@@ -36,6 +36,7 @@
 #include "qemu/log.h"
 #include "qom/object.h"
 #include "target/arm/cpu-qom.h"
+#include "target/arm/psci.h"
 
 #define SMP_BOOT_ADDR           0x100
 #define SMP_BOOT_REG            0x40
diff --git a/hw/arm/imx8mp-evk.c b/hw/arm/imx8mp-evk.c
index 6e64ec4ea54..c8a99b2c49e 100644
--- a/hw/arm/imx8mp-evk.c
+++ b/hw/arm/imx8mp-evk.c
@@ -15,6 +15,7 @@
 #include "system/qtest.h"
 #include "qemu/error-report.h"
 #include "qapi/error.h"
+#include "target/arm/psci.h"
 
 static void imx8mp_evk_init(MachineState *machine)
 {
diff --git a/hw/arm/mcimx6ul-evk.c b/hw/arm/mcimx6ul-evk.c
index 86982cb0772..be5e50abf17 100644
--- a/hw/arm/mcimx6ul-evk.c
+++ b/hw/arm/mcimx6ul-evk.c
@@ -18,6 +18,7 @@
 #include "hw/qdev-properties.h"
 #include "qemu/error-report.h"
 #include "system/qtest.h"
+#include "target/arm/psci.h"
 
 static void mcimx6ul_evk_init(MachineState *machine)
 {
diff --git a/hw/arm/mcimx7d-sabre.c b/hw/arm/mcimx7d-sabre.c
index 33119610113..e0f25b92594 100644
--- a/hw/arm/mcimx7d-sabre.c
+++ b/hw/arm/mcimx7d-sabre.c
@@ -20,6 +20,7 @@
 #include "hw/qdev-properties.h"
 #include "qemu/error-report.h"
 #include "system/qtest.h"
+#include "target/arm/psci.h"
 
 static void mcimx7d_sabre_init(MachineState *machine)
 {
diff --git a/hw/arm/orangepi.c b/hw/arm/orangepi.c
index e0956880d11..99037a09a36 100644
--- a/hw/arm/orangepi.c
+++ b/hw/arm/orangepi.c
@@ -26,6 +26,7 @@
 #include "hw/qdev-properties.h"
 #include "hw/arm/allwinner-h3.h"
 #include "hw/arm/boot.h"
+#include "target/arm/psci.h"
 
 static struct arm_boot_info orangepi_binfo;
 
diff --git a/hw/arm/sbsa-ref.c b/hw/arm/sbsa-ref.c
index 90fbb56ba7a..1f592627c99 100644
--- a/hw/arm/sbsa-ref.c
+++ b/hw/arm/sbsa-ref.c
@@ -53,6 +53,7 @@
 #include "target/arm/cpu-qom.h"
 #include "target/arm/gtimer.h"
 #include "target/arm/multiprocessing.h"
+#include "target/arm/psci.h"
 
 #define RAMLIMIT_GB 8192
 #define RAMLIMIT_BYTES (RAMLIMIT_GB * GiB)
diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c
index 3ac8f8e1786..da61af1d359 100644
--- a/hw/arm/virt-acpi-build.c
+++ b/hw/arm/virt-acpi-build.c
@@ -59,6 +59,7 @@
 #include "hw/acpi/viot.h"
 #include "hw/virtio/virtio-acpi.h"
 #include "target/arm/multiprocessing.h"
+#include "target/arm/psci.h"
 
 #define ARM_SPI_BASE 32
 
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
index a96452f17a4..fe2dec9500f 100644
--- a/hw/arm/virt.c
+++ b/hw/arm/virt.c
@@ -79,6 +79,7 @@
 #include "target/arm/internals.h"
 #include "target/arm/multiprocessing.h"
 #include "target/arm/gtimer.h"
+#include "target/arm/psci.h"
 #include "hw/mem/pc-dimm.h"
 #include "hw/mem/nvdimm.h"
 #include "hw/acpi/generic_event_device.h"
diff --git a/hw/arm/xlnx-versal-virt.c b/hw/arm/xlnx-versal-virt.c
index e19c4d9ef58..94fad8e60f2 100644
--- a/hw/arm/xlnx-versal-virt.c
+++ b/hw/arm/xlnx-versal-virt.c
@@ -21,6 +21,7 @@
 #include "hw/arm/xlnx-versal.h"
 #include "hw/arm/boot.h"
 #include "target/arm/multiprocessing.h"
+#include "target/arm/psci.h"
 #include "qom/object.h"
 
 #define TYPE_XLNX_VERSAL_VIRT_MACHINE MACHINE_TYPE_NAME("xlnx-versal-virt")
diff --git a/hw/arm/xlnx-zcu102.c b/hw/arm/xlnx-zcu102.c
index 88b1eafab4d..902ee65ca5f 100644
--- a/hw/arm/xlnx-zcu102.c
+++ b/hw/arm/xlnx-zcu102.c
@@ -26,6 +26,7 @@
 #include "qom/object.h"
 #include "net/can_emu.h"
 #include "audio/audio.h"
+#include "target/arm/psci.h"
 
 struct XlnxZCU102 {
     MachineState parent_obj;
diff --git a/hw/vmapple/vmapple.c b/hw/vmapple/vmapple.c
index 25652b16f0c..b73b6fb8115 100644
--- a/hw/vmapple/vmapple.c
+++ b/hw/vmapple/vmapple.c
@@ -53,6 +53,7 @@
 #include "system/system.h"
 #include "target/arm/gtimer.h"
 #include "target/arm/multiprocessing.h"
+#include "target/arm/psci.h"
 
 struct VMAppleMachineState {
     MachineState parent;
diff --git a/target/arm/helper.c b/target/arm/helper.c
index 7fb6e886306..48238ae0b20 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -34,6 +34,7 @@
 #endif
 #include "cpregs.h"
 #include "target/arm/gtimer.h"
+#include "target/arm/psci.h"
 
 #define ARM_CPU_FREQ 1000000000 /* FIXME: 1 GHz, should be configurable */
 
diff --git a/target/arm/hvf/hvf.c b/target/arm/hvf/hvf.c
index 34ca36fab55..f617e73feae 100644
--- a/target/arm/hvf/hvf.c
+++ b/target/arm/hvf/hvf.c
@@ -33,6 +33,7 @@
 #include "target/arm/internals.h"
 #include "target/arm/multiprocessing.h"
 #include "target/arm/gtimer.h"
+#include "target/arm/psci.h"
 #include "trace.h"
 #include "migration/vmstate.h"
 
diff --git a/target/arm/tcg/op_helper.c b/target/arm/tcg/op_helper.c
index 005f84082af..6e9db2e77e2 100644
--- a/target/arm/tcg/op_helper.c
+++ b/target/arm/tcg/op_helper.c
@@ -26,6 +26,7 @@
 #include "exec/exec-all.h"
 #include "accel/tcg/cpu-ldst.h"
 #include "target/arm/gtimer.h"
+#include "target/arm/psci.h"
 #include "cpregs.h"
 
 #define SIGNBIT (uint32_t)0x80000000
diff --git a/target/arm/tcg/psci.c b/target/arm/tcg/psci.c
index cabed43e8a8..0313cdd6ba2 100644
--- a/target/arm/tcg/psci.c
+++ b/target/arm/tcg/psci.c
@@ -25,6 +25,7 @@
 #include "internals.h"
 #include "arm-powerctl.h"
 #include "target/arm/multiprocessing.h"
+#include "target/arm/psci.h"
 
 bool arm_is_psci_call(ARMCPU *cpu, int excp_type)
 {
-- 
2.47.1

[RFC PATCH-for-10.1 21/39] target/arm: Extract feature definitions to 'cpu_has_feature.h' header

[Philippe Mathieu-Daudé]

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
---
 target/arm/cpu.h             | 54 +-----------------------------
 target/arm/cpu_has_feature.h | 65 ++++++++++++++++++++++++++++++++++++
 2 files changed, 66 insertions(+), 53 deletions(-)
 create mode 100644 target/arm/cpu_has_feature.h

diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index 930c5366029..fd8beb8bcb1 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -30,6 +30,7 @@
 #include "exec/gdbstub.h"
 #include "exec/page-protection.h"
 #include "qapi/qapi-types-common.h"
+#include "target/arm/cpu_has_feature.h"
 #include "target/arm/gtimer.h"
 
 #define EXCP_UDEF            1   /* undefined instruction */
@@ -2379,59 +2380,6 @@ FIELD(MFAR, NS, 63, 1)
 
 QEMU_BUILD_BUG_ON(ARRAY_SIZE(((ARMCPU *)0)->ccsidr) <= R_V7M_CSSELR_INDEX_MASK);
 
-/* If adding a feature bit which corresponds to a Linux ELF
- * HWCAP bit, remember to update the feature-bit-to-hwcap
- * mapping in linux-user/elfload.c:get_elf_hwcap().
- */
-enum arm_features {
-    ARM_FEATURE_AUXCR,  /* ARM1026 Auxiliary control register.  */
-    ARM_FEATURE_XSCALE, /* Intel XScale extensions.  */
-    ARM_FEATURE_IWMMXT, /* Intel iwMMXt extension.  */
-    ARM_FEATURE_V6,
-    ARM_FEATURE_V6K,
-    ARM_FEATURE_V7,
-    ARM_FEATURE_THUMB2,
-    ARM_FEATURE_PMSA,   /* no MMU; may have Memory Protection Unit */
-    ARM_FEATURE_NEON,
-    ARM_FEATURE_M, /* Microcontroller profile.  */
-    ARM_FEATURE_OMAPCP, /* OMAP specific CP15 ops handling.  */
-    ARM_FEATURE_THUMB2EE,
-    ARM_FEATURE_V7MP,    /* v7 Multiprocessing Extensions */
-    ARM_FEATURE_V7VE, /* v7 Virtualization Extensions (non-EL2 parts) */
-    ARM_FEATURE_V4T,
-    ARM_FEATURE_V5,
-    ARM_FEATURE_STRONGARM,
-    ARM_FEATURE_VAPA, /* cp15 VA to PA lookups */
-    ARM_FEATURE_GENERIC_TIMER,
-    ARM_FEATURE_MVFR, /* Media and VFP Feature Registers 0 and 1 */
-    ARM_FEATURE_DUMMY_C15_REGS, /* RAZ/WI all of cp15 crn=15 */
-    ARM_FEATURE_CACHE_TEST_CLEAN, /* 926/1026 style test-and-clean ops */
-    ARM_FEATURE_CACHE_DIRTY_REG, /* 1136/1176 cache dirty status register */
-    ARM_FEATURE_CACHE_BLOCK_OPS, /* v6 optional cache block operations */
-    ARM_FEATURE_MPIDR, /* has cp15 MPIDR */
-    ARM_FEATURE_LPAE, /* has Large Physical Address Extension */
-    ARM_FEATURE_V8,
-    ARM_FEATURE_AARCH64, /* supports 64 bit mode */
-    ARM_FEATURE_CBAR, /* has cp15 CBAR */
-    ARM_FEATURE_CBAR_RO, /* has cp15 CBAR and it is read-only */
-    ARM_FEATURE_EL2, /* has EL2 Virtualization support */
-    ARM_FEATURE_EL3, /* has EL3 Secure monitor support */
-    ARM_FEATURE_THUMB_DSP, /* DSP insns supported in the Thumb encodings */
-    ARM_FEATURE_PMU, /* has PMU support */
-    ARM_FEATURE_VBAR, /* has cp15 VBAR */
-    ARM_FEATURE_M_SECURITY, /* M profile Security Extension */
-    ARM_FEATURE_M_MAIN, /* M profile Main Extension */
-    ARM_FEATURE_V8_1M, /* M profile extras only in v8.1M and later */
-    /*
-     * ARM_FEATURE_BACKCOMPAT_CNTFRQ makes the CPU default cntfrq be 62.5MHz
-     * if the board doesn't set a value, instead of 1GHz. It is for backwards
-     * compatibility and used only with CPU definitions that were already
-     * in QEMU before we changed the default. It should not be set on any
-     * CPU types added in future.
-     */
-    ARM_FEATURE_BACKCOMPAT_CNTFRQ, /* 62.5MHz timer default */
-};
-
 static inline int arm_feature(CPUARMState *env, int feature)
 {
     return (env->features & (1ULL << feature)) != 0;
diff --git a/target/arm/cpu_has_feature.h b/target/arm/cpu_has_feature.h
new file mode 100644
index 00000000000..2adfccd9208
--- /dev/null
+++ b/target/arm/cpu_has_feature.h
@@ -0,0 +1,65 @@
+/*
+ * Helper to check ARM CPU has features
+ *
+ *  Copyright (c) 2003 Fabrice Bellard
+ *
+ * SPDX-License-Identifier: LGPL-2.1-or-later
+ */
+#ifndef TARGET_ARM_CPU_HAS_FEATURE_H
+#define TARGET_ARM_CPU_HAS_FEATURE_H
+
+/*
+ * If adding a feature bit which corresponds to a Linux ELF
+ * HWCAP bit, remember to update the feature-bit-to-hwcap
+ * mapping in linux-user/elfload.c:get_elf_hwcap().
+ */
+typedef enum arm_features {
+    ARM_FEATURE_AUXCR,  /* ARM1026 Auxiliary control register.  */
+    ARM_FEATURE_XSCALE, /* Intel XScale extensions.  */
+    ARM_FEATURE_IWMMXT, /* Intel iwMMXt extension.  */
+    ARM_FEATURE_V6,
+    ARM_FEATURE_V6K,
+    ARM_FEATURE_V7,
+    ARM_FEATURE_THUMB2,
+    ARM_FEATURE_PMSA,   /* no MMU; may have Memory Protection Unit */
+    ARM_FEATURE_NEON,
+    ARM_FEATURE_M, /* Microcontroller profile.  */
+    ARM_FEATURE_OMAPCP, /* OMAP specific CP15 ops handling.  */
+    ARM_FEATURE_THUMB2EE,
+    ARM_FEATURE_V7MP,    /* v7 Multiprocessing Extensions */
+    ARM_FEATURE_V7VE, /* v7 Virtualization Extensions (non-EL2 parts) */
+    ARM_FEATURE_V4T,
+    ARM_FEATURE_V5,
+    ARM_FEATURE_STRONGARM,
+    ARM_FEATURE_VAPA, /* cp15 VA to PA lookups */
+    ARM_FEATURE_GENERIC_TIMER,
+    ARM_FEATURE_MVFR, /* Media and VFP Feature Registers 0 and 1 */
+    ARM_FEATURE_DUMMY_C15_REGS, /* RAZ/WI all of cp15 crn=15 */
+    ARM_FEATURE_CACHE_TEST_CLEAN, /* 926/1026 style test-and-clean ops */
+    ARM_FEATURE_CACHE_DIRTY_REG, /* 1136/1176 cache dirty status register */
+    ARM_FEATURE_CACHE_BLOCK_OPS, /* v6 optional cache block operations */
+    ARM_FEATURE_MPIDR, /* has cp15 MPIDR */
+    ARM_FEATURE_LPAE, /* has Large Physical Address Extension */
+    ARM_FEATURE_V8,
+    ARM_FEATURE_AARCH64, /* supports 64 bit mode */
+    ARM_FEATURE_CBAR, /* has cp15 CBAR */
+    ARM_FEATURE_CBAR_RO, /* has cp15 CBAR and it is read-only */
+    ARM_FEATURE_EL2, /* has EL2 Virtualization support */
+    ARM_FEATURE_EL3, /* has EL3 Secure monitor support */
+    ARM_FEATURE_THUMB_DSP, /* DSP insns supported in the Thumb encodings */
+    ARM_FEATURE_PMU, /* has PMU support */
+    ARM_FEATURE_VBAR, /* has cp15 VBAR */
+    ARM_FEATURE_M_SECURITY, /* M profile Security Extension */
+    ARM_FEATURE_M_MAIN, /* M profile Main Extension */
+    ARM_FEATURE_V8_1M, /* M profile extras only in v8.1M and later */
+    /*
+     * ARM_FEATURE_BACKCOMPAT_CNTFRQ makes the CPU default cntfrq be 62.5MHz
+     * if the board doesn't set a value, instead of 1GHz. It is for backwards
+     * compatibility and used only with CPU definitions that were already
+     * in QEMU before we changed the default. It should not be set on any
+     * CPU types added in future.
+     */
+    ARM_FEATURE_BACKCOMPAT_CNTFRQ, /* 62.5MHz timer default */
+} ArmCpuFeature;
+
+#endif
-- 
2.47.1

[RFC PATCH-for-10.1 22/39] target/arm: Add arm_cpu_has_feature() helper

[Philippe Mathieu-Daudé]

arm_cpu_has_feature() is equivalent of arm_feature(), however
while the latter uses CPUARMState so is target-specific, the
former doesn't and can be called by target-agnostic code in hw/.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
---
 target/arm/cpu_has_feature.h | 2 ++
 target/arm/cpu.c             | 7 +++++++
 2 files changed, 9 insertions(+)

diff --git a/target/arm/cpu_has_feature.h b/target/arm/cpu_has_feature.h
index 2adfccd9208..352f9d75bed 100644
--- a/target/arm/cpu_has_feature.h
+++ b/target/arm/cpu_has_feature.h
@@ -62,4 +62,6 @@ typedef enum arm_features {
     ARM_FEATURE_BACKCOMPAT_CNTFRQ, /* 62.5MHz timer default */
 } ArmCpuFeature;
 
+bool arm_cpu_has_feature(ARMCPU *cpu, ArmCpuFeature feature);
+
 #endif
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index 6f62745d7f6..66a58916fcc 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -55,6 +55,13 @@
 #include "target/arm/gtimer.h"
 #include "target/arm/multiprocessing.h"
 
+bool arm_cpu_has_feature(ARMCPU *cpu, ArmCpuFeature feature)
+{
+    CPUARMState *env = &cpu->env;
+
+    return arm_feature(env, feature);
+}
+
 static void arm_cpu_set_pc(CPUState *cs, vaddr value)
 {
     ARMCPU *cpu = ARM_CPU(cs);
-- 
2.47.1

[RFC PATCH-for-10.1 23/39] hw/arm/realview: Replace arm_feature() -> arm_cpu_has_feature()

[Philippe Mathieu-Daudé]

By using arm_cpu_has_feature() instead of arm_feature()
we don't need to include "cpu.h" anymore.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
---
 hw/arm/realview.c | 10 ++++------
 1 file changed, 4 insertions(+), 6 deletions(-)

diff --git a/hw/arm/realview.c b/hw/arm/realview.c
index f81d084eb80..48cfe05add0 100644
--- a/hw/arm/realview.c
+++ b/hw/arm/realview.c
@@ -9,7 +9,6 @@
 
 #include "qemu/osdep.h"
 #include "qapi/error.h"
-#include "cpu.h"
 #include "hw/sysbus.h"
 #include "hw/arm/boot.h"
 #include "hw/arm/primecell.h"
@@ -31,6 +30,7 @@
 #include "hw/sd/sd.h"
 #include "audio/audio.h"
 #include "target/arm/cpu-qom.h"
+#include "target/arm/cpu_has_feature.h"
 
 #define SMP_BOOT_ADDR 0xe0000000
 #define SMP_BOOTREG_ADDR 0x10000030
@@ -77,7 +77,6 @@ static void realview_init(MachineState *machine,
                           enum realview_board_type board_type)
 {
     ARMCPU *cpu = NULL;
-    CPUARMState *env;
     MemoryRegion *sysmem = get_system_memory();
     MemoryRegion *ram_lo;
     MemoryRegion *ram_hi = g_new(MemoryRegion, 1);
@@ -138,16 +137,15 @@ static void realview_init(MachineState *machine,
         cpu_irq[n] = qdev_get_gpio_in(DEVICE(cpuobj), ARM_CPU_IRQ);
     }
     cpu = ARM_CPU(first_cpu);
-    env = &cpu->env;
-    if (arm_feature(env, ARM_FEATURE_V7)) {
+    if (arm_cpu_has_feature(cpu, ARM_FEATURE_V7)) {
         if (is_mpcore) {
             proc_id = 0x0c000000;
         } else {
             proc_id = 0x0e000000;
         }
-    } else if (arm_feature(env, ARM_FEATURE_V6K)) {
+    } else if (arm_cpu_has_feature(cpu, ARM_FEATURE_V6K)) {
         proc_id = 0x06000000;
-    } else if (arm_feature(env, ARM_FEATURE_V6)) {
+    } else if (arm_cpu_has_feature(cpu, ARM_FEATURE_V6)) {
         proc_id = 0x04000000;
     } else {
         proc_id = 0x02000000;
-- 
2.47.1

[RFC PATCH-for-10.1 24/39] hw/arm/virt-acpi: Replace arm_feature() -> arm_cpu_has_feature()

[Philippe Mathieu-Daudé]

Using arm_cpu_has_feature() instead of arm_feature() remove
a dependency on (the indirectly included) "cpu.h" header.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
---
 hw/arm/virt-acpi-build.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c
index da61af1d359..ae28d958895 100644
--- a/hw/arm/virt-acpi-build.c
+++ b/hw/arm/virt-acpi-build.c
@@ -58,6 +58,7 @@
 #include "hw/acpi/ghes.h"
 #include "hw/acpi/viot.h"
 #include "hw/virtio/virtio-acpi.h"
+#include "target/arm/cpu_has_feature.h"
 #include "target/arm/multiprocessing.h"
 #include "target/arm/psci.h"
 
@@ -697,7 +698,7 @@ build_madt(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms)
         ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(i));
         uint64_t physical_base_address = 0, gich = 0, gicv = 0;
         uint32_t vgic_interrupt = vms->virt ? ARCH_GIC_MAINT_IRQ : 0;
-        uint32_t pmu_interrupt = arm_feature(&armcpu->env, ARM_FEATURE_PMU) ?
+        uint32_t pmu_interrupt = arm_cpu_has_feature(armcpu, ARM_FEATURE_PMU) ?
                                              VIRTUAL_PMU_IRQ : 0;
 
         if (vms->gic_version == VIRT_GIC_VERSION_2) {
-- 
2.47.1

[RFC PATCH-for-10.1 25/39] hw/arm: Build virt-acpi-build.c once

[Philippe Mathieu-Daudé]

Previous commits removed the target-specificities,
we can now move virt-acpi-build.c to arm_common_ss[].

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
 hw/arm/meson.build | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/hw/arm/meson.build b/hw/arm/meson.build
index f52034ff6a2..536e3c369c5 100644
--- a/hw/arm/meson.build
+++ b/hw/arm/meson.build
@@ -1,7 +1,7 @@
 arm_ss = ss.source_set()
 arm_common_ss = ss.source_set()
 arm_ss.add(when: 'CONFIG_ARM_VIRT', if_true: files('virt.c'))
-arm_ss.add(when: 'CONFIG_ACPI', if_true: files('virt-acpi-build.c'))
+arm_common_ss.add(when: 'CONFIG_ACPI', if_true: files('virt-acpi-build.c'))
 arm_common_ss.add(when: 'CONFIG_DIGIC', if_true: files('digic_boards.c'))
 arm_common_ss.add(when: 'CONFIG_EMCRAFT_SF2', if_true: files('msf2-som.c'))
 arm_common_ss.add(when: 'CONFIG_HIGHBANK', if_true: files('highbank.c'))
-- 
2.47.1

[RFC PATCH-for-10.1 26/39] system/hvf: Avoid including 'cpu.h'

[Philippe Mathieu-Daudé]

"system/hvf.h" doesn't need to include a full "cpu.h",
only "exec/vaddr.h" and "qemu/queue.h" are required.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
 include/system/hvf.h     | 3 ++-
 include/system/hvf_int.h | 2 ++
 2 files changed, 4 insertions(+), 1 deletion(-)

diff --git a/include/system/hvf.h b/include/system/hvf.h
index 730f927f034..d50049e1a1a 100644
--- a/include/system/hvf.h
+++ b/include/system/hvf.h
@@ -14,10 +14,11 @@
 #define HVF_H
 
 #include "qemu/accel.h"
+#include "qemu/queue.h"
+#include "exec/vaddr.h"
 #include "qom/object.h"
 
 #ifdef COMPILING_PER_TARGET
-#include "cpu.h"
 
 #ifdef CONFIG_HVF
 extern bool hvf_allowed;
diff --git a/include/system/hvf_int.h b/include/system/hvf_int.h
index 42ae18433f0..8c8b84012d9 100644
--- a/include/system/hvf_int.h
+++ b/include/system/hvf_int.h
@@ -11,6 +11,8 @@
 #ifndef HVF_INT_H
 #define HVF_INT_H
 
+#include "qemu/queue.h"
+
 #ifdef __aarch64__
 #include <Hypervisor/Hypervisor.h>
 typedef hv_vcpu_t hvf_vcpuid;
-- 
2.47.1

[RFC PATCH-for-10.1 27/39] system/hvf: Expose hvf_enabled() to common code

[Philippe Mathieu-Daudé]

Currently hvf_enabled() is restricted to target-specific code.
By defining CONFIG_HVF_IS_POSSIBLE we allow its use anywhere.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
 MAINTAINERS             |  1 +
 include/system/hvf.h    | 14 +++++++++-----
 accel/stubs/hvf-stub.c  | 12 ++++++++++++
 accel/stubs/meson.build |  1 +
 4 files changed, 23 insertions(+), 5 deletions(-)
 create mode 100644 accel/stubs/hvf-stub.c

diff --git a/MAINTAINERS b/MAINTAINERS
index c7083ab1d93..00ef33be0e2 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -525,6 +525,7 @@ R: Phil Dennis-Jordan <phil@philjordan.eu>
 W: https://wiki.qemu.org/Features/HVF
 S: Maintained
 F: accel/hvf/
+F: accel/stubs/hvf-stub.c
 F: include/system/hvf.h
 F: include/system/hvf_int.h
 
diff --git a/include/system/hvf.h b/include/system/hvf.h
index d50049e1a1a..7b45a2e1988 100644
--- a/include/system/hvf.h
+++ b/include/system/hvf.h
@@ -19,15 +19,19 @@
 #include "qom/object.h"
 
 #ifdef COMPILING_PER_TARGET
+# ifdef CONFIG_HVF
+#  define CONFIG_HVF_IS_POSSIBLE
+# endif /* !CONFIG_HVF */
+#else
+# define CONFIG_HVF_IS_POSSIBLE
+#endif /* COMPILING_PER_TARGET */
 
-#ifdef CONFIG_HVF
+#ifdef CONFIG_HVF_IS_POSSIBLE
 extern bool hvf_allowed;
 #define hvf_enabled() (hvf_allowed)
-#else /* !CONFIG_HVF */
+#else /* !CONFIG_HVF_IS_POSSIBLE */
 #define hvf_enabled() 0
-#endif /* !CONFIG_HVF */
-
-#endif /* COMPILING_PER_TARGET */
+#endif /* !CONFIG_HVF_IS_POSSIBLE */
 
 #define TYPE_HVF_ACCEL ACCEL_CLASS_NAME("hvf")
 
diff --git a/accel/stubs/hvf-stub.c b/accel/stubs/hvf-stub.c
new file mode 100644
index 00000000000..42eadc5ca92
--- /dev/null
+++ b/accel/stubs/hvf-stub.c
@@ -0,0 +1,12 @@
+/*
+ * HVF stubs for QEMU
+ *
+ *  Copyright (c) Linaro
+ *
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ */
+
+#include "qemu/osdep.h"
+#include "system/hvf.h"
+
+bool hvf_allowed;
diff --git a/accel/stubs/meson.build b/accel/stubs/meson.build
index 91a2d219258..8ca1a4529e2 100644
--- a/accel/stubs/meson.build
+++ b/accel/stubs/meson.build
@@ -2,5 +2,6 @@ system_stubs_ss = ss.source_set()
 system_stubs_ss.add(when: 'CONFIG_XEN', if_false: files('xen-stub.c'))
 system_stubs_ss.add(when: 'CONFIG_KVM', if_false: files('kvm-stub.c'))
 system_stubs_ss.add(when: 'CONFIG_TCG', if_false: files('tcg-stub.c'))
+system_stubs_ss.add(when: 'CONFIG_HVF', if_false: files('hvf-stub.c'))
 
 specific_ss.add_all(when: ['CONFIG_SYSTEM_ONLY'], if_true: system_stubs_ss)
-- 
2.47.1

[RFC PATCH-for-10.1 28/39] exec: Do not poison hardware accelerators

[Philippe Mathieu-Daudé]

Hardware accelerators depends on the host, not the guest.

Suggested-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
 include/exec/poison.h         | 4 ----
 scripts/make-config-poison.sh | 4 ++++
 2 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/include/exec/poison.h b/include/exec/poison.h
index 00aedc41d82..0574d683f6a 100644
--- a/include/exec/poison.h
+++ b/include/exec/poison.h
@@ -62,11 +62,7 @@
 #pragma GCC poison CONFIG_SPARC_DIS
 #pragma GCC poison CONFIG_XTENSA_DIS
 
-#pragma GCC poison CONFIG_HVF
 #pragma GCC poison CONFIG_LINUX_USER
-#pragma GCC poison CONFIG_KVM
-#pragma GCC poison CONFIG_WHPX
-#pragma GCC poison CONFIG_XEN
 
 #ifndef COMPILING_SYSTEM_VS_USER
 #pragma GCC poison CONFIG_USER_ONLY
diff --git a/scripts/make-config-poison.sh b/scripts/make-config-poison.sh
index 2b36907e239..09d2384745f 100755
--- a/scripts/make-config-poison.sh
+++ b/scripts/make-config-poison.sh
@@ -8,6 +8,10 @@ fi
 # but filter out several which are handled manually.
 exec sed -n \
   -e' /CONFIG_TCG/d' \
+  -e' /CONFIG_HVF/d' \
+  -e' /CONFIG_KVM/d' \
+  -e' /CONFIG_WHPX/d' \
+  -e' /CONFIG_XEN/d' \
   -e '/CONFIG_USER_ONLY/d' \
   -e '/CONFIG_SOFTMMU/d' \
   -e '/^#define / {' \
-- 
2.47.1

[RFC PATCH-for-10.1 29/39] hw/arm: Build sbsa-ref.c once

[Philippe Mathieu-Daudé]

Since previous commit allowed the use of accelerator definitions
in common code, we can now move sbsa-ref.c to arm_common_ss[].

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
 hw/arm/meson.build | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/hw/arm/meson.build b/hw/arm/meson.build
index 536e3c369c5..7eb49c7327f 100644
--- a/hw/arm/meson.build
+++ b/hw/arm/meson.build
@@ -14,7 +14,7 @@ arm_common_ss.add(when: 'CONFIG_OLIMEX_STM32_H405', if_true: files('olimex-stm32
 arm_common_ss.add(when: 'CONFIG_NPCM7XX', if_true: files('npcm7xx.c', 'npcm7xx_boards.c'))
 arm_common_ss.add(when: 'CONFIG_NPCM8XX', if_true: files('npcm8xx.c', 'npcm8xx_boards.c'))
 arm_common_ss.add(when: 'CONFIG_REALVIEW', if_true: files('realview.c'))
-arm_ss.add(when: 'CONFIG_SBSA_REF', if_true: files('sbsa-ref.c'))
+arm_common_ss.add(when: 'CONFIG_SBSA_REF', if_true: files('sbsa-ref.c'))
 arm_common_ss.add(when: 'CONFIG_STELLARIS', if_true: files('stellaris.c'))
 arm_common_ss.add(when: 'CONFIG_STM32VLDISCOVERY', if_true: files('stm32vldiscovery.c'))
 arm_common_ss.add(when: 'CONFIG_ZYNQ', if_true: files('xilinx_zynq.c'))
-- 
2.47.1

[RFC PATCH-for-10.1 30/39] target/arm: Replace target_ulong -> hwaddr in ARMMMUFaultInfo

[Philippe Mathieu-Daudé]

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
 target/arm/internals.h | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/target/arm/internals.h b/target/arm/internals.h
index 01408e40a34..d6ac00be0f2 100644
--- a/target/arm/internals.h
+++ b/target/arm/internals.h
@@ -25,6 +25,7 @@
 #ifndef TARGET_ARM_INTERNALS_H
 #define TARGET_ARM_INTERNALS_H
 
+#include "exec/hwaddr.h"
 #include "exec/breakpoint.h"
 #include "hw/registerfields.h"
 #include "tcg/tcg-gvec-desc.h"
@@ -726,8 +727,8 @@ typedef struct ARMMMUFaultInfo ARMMMUFaultInfo;
 struct ARMMMUFaultInfo {
     ARMFaultType type;
     ARMGPCF gpcf;
-    target_ulong s2addr;
-    target_ulong paddr;
+    hwaddr s2addr;
+    hwaddr paddr;
     ARMSecuritySpace paddr_space;
     int level;
     int domain;
-- 
2.47.1

[RFC PATCH-for-10.1 31/39] target/arm: Replace target_ulong -> uint64_t for HWBreakpoint

[Philippe Mathieu-Daudé]

CPUARMState::pc is of type uint64_t.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
 target/arm/internals.h   | 6 +++---
 target/arm/hyp_gdbstub.c | 6 +++---
 2 files changed, 6 insertions(+), 6 deletions(-)

diff --git a/target/arm/internals.h b/target/arm/internals.h
index d6ac00be0f2..ce60aee41d8 100644
--- a/target/arm/internals.h
+++ b/target/arm/internals.h
@@ -1944,9 +1944,9 @@ extern GArray *hw_breakpoints, *hw_watchpoints;
 #define get_hw_bp(i)    (&g_array_index(hw_breakpoints, HWBreakpoint, i))
 #define get_hw_wp(i)    (&g_array_index(hw_watchpoints, HWWatchpoint, i))
 
-bool find_hw_breakpoint(CPUState *cpu, target_ulong pc);
-int insert_hw_breakpoint(target_ulong pc);
-int delete_hw_breakpoint(target_ulong pc);
+bool find_hw_breakpoint(CPUState *cpu, uint64_t pc);
+int insert_hw_breakpoint(uint64_t pc);
+int delete_hw_breakpoint(uint64_t pc);
 
 bool check_watchpoint_in_range(int i, target_ulong addr);
 CPUWatchpoint *find_hw_watchpoint(CPUState *cpu, target_ulong addr);
diff --git a/target/arm/hyp_gdbstub.c b/target/arm/hyp_gdbstub.c
index 1e861263b3d..4e52d37ed80 100644
--- a/target/arm/hyp_gdbstub.c
+++ b/target/arm/hyp_gdbstub.c
@@ -54,7 +54,7 @@ GArray *hw_breakpoints, *hw_watchpoints;
  * here so future PC comparisons will work properly.
  */
 
-int insert_hw_breakpoint(target_ulong addr)
+int insert_hw_breakpoint(uint64_t addr)
 {
     HWBreakpoint brk = {
         .bcr = 0x1,                             /* BCR E=1, enable */
@@ -80,7 +80,7 @@ int insert_hw_breakpoint(target_ulong addr)
  * Delete a breakpoint and shuffle any above down
  */
 
-int delete_hw_breakpoint(target_ulong pc)
+int delete_hw_breakpoint(uint64_t pc)
 {
     int i;
     for (i = 0; i < hw_breakpoints->len; i++) {
@@ -226,7 +226,7 @@ int delete_hw_watchpoint(target_ulong addr, target_ulong len, int type)
     return -ENOENT;
 }
 
-bool find_hw_breakpoint(CPUState *cpu, target_ulong pc)
+bool find_hw_breakpoint(CPUState *cpu, uint64_t pc)
 {
     int i;
 
-- 
2.47.1

[RFC PATCH-for-10.1 32/39] target/arm: Replace target_ulong -> vaddr for CPUWatchpoint

[Philippe Mathieu-Daudé]

CPUWatchpoint::vaddr/len are of type vaddr.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
 target/arm/internals.h   | 9 +++++----
 target/arm/hyp_gdbstub.c | 8 ++++----
 2 files changed, 9 insertions(+), 8 deletions(-)

diff --git a/target/arm/internals.h b/target/arm/internals.h
index ce60aee41d8..86577207b85 100644
--- a/target/arm/internals.h
+++ b/target/arm/internals.h
@@ -26,6 +26,7 @@
 #define TARGET_ARM_INTERNALS_H
 
 #include "exec/hwaddr.h"
+#include "exec/vaddr.h"
 #include "exec/breakpoint.h"
 #include "hw/registerfields.h"
 #include "tcg/tcg-gvec-desc.h"
@@ -1948,10 +1949,10 @@ bool find_hw_breakpoint(CPUState *cpu, uint64_t pc);
 int insert_hw_breakpoint(uint64_t pc);
 int delete_hw_breakpoint(uint64_t pc);
 
-bool check_watchpoint_in_range(int i, target_ulong addr);
-CPUWatchpoint *find_hw_watchpoint(CPUState *cpu, target_ulong addr);
-int insert_hw_watchpoint(target_ulong addr, target_ulong len, int type);
-int delete_hw_watchpoint(target_ulong addr, target_ulong len, int type);
+bool check_watchpoint_in_range(int i, vaddr addr);
+CPUWatchpoint *find_hw_watchpoint(CPUState *cpu, vaddr addr);
+int insert_hw_watchpoint(vaddr addr, vaddr len, int type);
+int delete_hw_watchpoint(vaddr addr, vaddr len, int type);
 
 /* Return the current value of the system counter in ticks */
 uint64_t gt_get_countervalue(CPUARMState *env);
diff --git a/target/arm/hyp_gdbstub.c b/target/arm/hyp_gdbstub.c
index 4e52d37ed80..4d8fd933868 100644
--- a/target/arm/hyp_gdbstub.c
+++ b/target/arm/hyp_gdbstub.c
@@ -125,7 +125,7 @@ int delete_hw_breakpoint(uint64_t pc)
  * need to ensure you mask the address as required and set BAS=0xff
  */
 
-int insert_hw_watchpoint(target_ulong addr, target_ulong len, int type)
+int insert_hw_watchpoint(vaddr addr, vaddr len, int type)
 {
     HWWatchpoint wp = {
         .wcr = R_DBGWCR_E_MASK, /* E=1, enable */
@@ -182,7 +182,7 @@ int insert_hw_watchpoint(target_ulong addr, target_ulong len, int type)
     return 0;
 }
 
-bool check_watchpoint_in_range(int i, target_ulong addr)
+bool check_watchpoint_in_range(int i, vaddr addr)
 {
     HWWatchpoint *wp = get_hw_wp(i);
     uint64_t addr_top, addr_bottom = wp->wvr;
@@ -214,7 +214,7 @@ bool check_watchpoint_in_range(int i, target_ulong addr)
  * Delete a breakpoint and shuffle any above down
  */
 
-int delete_hw_watchpoint(target_ulong addr, target_ulong len, int type)
+int delete_hw_watchpoint(vaddr addr, vaddr len, int type)
 {
     int i;
     for (i = 0; i < cur_hw_wps; i++) {
@@ -239,7 +239,7 @@ bool find_hw_breakpoint(CPUState *cpu, uint64_t pc)
     return false;
 }
 
-CPUWatchpoint *find_hw_watchpoint(CPUState *cpu, target_ulong addr)
+CPUWatchpoint *find_hw_watchpoint(CPUState *cpu, vaddr addr)
 {
     int i;
 
-- 
2.47.1

[RFC PATCH-for-10.1 33/39] hw/core/machine: Allow dynamic registration of valid CPU types

[Philippe Mathieu-Daudé]

Add MachineClass::valid_cpu_types_list, a dynamic list of strings.

CPU types can be registered with machine_class_add_valid_cpu_type().

Suggested-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
 include/hw/boards.h |  8 ++++++++
 hw/core/machine.c   | 28 ++++++++++++++++++++++++++++
 2 files changed, 36 insertions(+)

diff --git a/include/hw/boards.h b/include/hw/boards.h
index b1bbf3c34d4..92a13b0dc32 100644
--- a/include/hw/boards.h
+++ b/include/hw/boards.h
@@ -57,6 +57,13 @@ void machine_set_cache_topo_level(MachineState *ms, CacheLevelAndType cache,
 bool machine_check_smp_cache(const MachineState *ms, Error **errp);
 void machine_memory_devices_init(MachineState *ms, hwaddr base, uint64_t size);
 
+/**
+ * machine_class_add_valid_cpu_type: Add type to list of valid CPUs
+ * @mc: Machine class
+ * @type: CPU type to allow (should be a subtype of TYPE_CPU)
+ */
+void machine_class_add_valid_cpu_type(MachineClass *mc, const char *type);
+
 /**
  * machine_class_allow_dynamic_sysbus_dev: Add type to list of valid devices
  * @mc: Machine class
@@ -307,6 +314,7 @@ struct MachineClass {
     bool ignore_memory_transaction_failures;
     int numa_mem_align_shift;
     const char * const *valid_cpu_types;
+    strList *valid_cpu_types_list;
     strList *allowed_dynamic_sysbus_devices;
     bool auto_enable_numa_with_memhp;
     bool auto_enable_numa_with_memdev;
diff --git a/hw/core/machine.c b/hw/core/machine.c
index f52a4f2273b..5993c6e38d5 100644
--- a/hw/core/machine.c
+++ b/hw/core/machine.c
@@ -1538,6 +1538,11 @@ const char *machine_class_default_cpu_type(MachineClass *mc)
     return mc->default_cpu_type;
 }
 
+void machine_class_add_valid_cpu_type(MachineClass *mc, const char *type)
+{
+    QAPI_LIST_PREPEND(mc->valid_cpu_types_list, g_strdup(type));
+}
+
 static bool is_cpu_type_supported(const MachineState *machine, Error **errp)
 {
     MachineClass *mc = MACHINE_GET_CLASS(machine);
@@ -1581,6 +1586,29 @@ static bool is_cpu_type_supported(const MachineState *machine, Error **errp)
             return false;
         }
     }
+    if (mc->valid_cpu_types_list) {
+        bool valid = false;
+        unsigned count = 0;
+        strList *wl;
+
+        for (wl = mc->valid_cpu_types_list; !valid && wl; wl = wl->next) {
+            valid |= !!object_class_dynamic_cast(oc, wl->value);
+            count++;
+        }
+
+        if (!valid) {
+            g_autofree char *requested = cpu_model_from_type(machine->cpu_type);
+            error_setg(errp, "Invalid CPU model: %s", requested);
+            error_append_hint(errp, "The valid models are: ");
+            for (wl = mc->valid_cpu_types_list; wl; wl = wl->next) {
+                g_autofree char *model = cpu_model_from_type(wl->value);
+                error_append_hint(errp, "%s%s", model, --count ? ", " : "");
+            }
+            error_append_hint(errp, "\n");
+
+            return false;
+        }
+    }
 
     /* Check if CPU type is deprecated and warn if so */
     cc = CPU_CLASS(oc);
-- 
2.47.1

[RFC PATCH-for-10.1 34/39] hw/arm/virt: Register valid CPU types dynamically

[Philippe Mathieu-Daudé]

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
 hw/arm/virt.c | 35 ++++++++++++++++-------------------
 1 file changed, 16 insertions(+), 19 deletions(-)

diff --git a/hw/arm/virt.c b/hw/arm/virt.c
index fe2dec9500f..e241e71e1c3 100644
--- a/hw/arm/virt.c
+++ b/hw/arm/virt.c
@@ -3129,32 +3129,30 @@ static void virt_machine_class_init(ObjectClass *oc, void *data)
 {
     MachineClass *mc = MACHINE_CLASS(oc);
     HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc);
-    static const char * const valid_cpu_types[] = {
+
 #ifdef CONFIG_TCG
-        ARM_CPU_TYPE_NAME("cortex-a7"),
-        ARM_CPU_TYPE_NAME("cortex-a15"),
+    machine_class_add_valid_cpu_type(mc, ARM_CPU_TYPE_NAME("cortex-a7"));
+    machine_class_add_valid_cpu_type(mc, ARM_CPU_TYPE_NAME("cortex-a15"));
 #ifdef TARGET_AARCH64
-        ARM_CPU_TYPE_NAME("cortex-a35"),
-        ARM_CPU_TYPE_NAME("cortex-a55"),
-        ARM_CPU_TYPE_NAME("cortex-a72"),
-        ARM_CPU_TYPE_NAME("cortex-a76"),
-        ARM_CPU_TYPE_NAME("cortex-a710"),
-        ARM_CPU_TYPE_NAME("a64fx"),
-        ARM_CPU_TYPE_NAME("neoverse-n1"),
-        ARM_CPU_TYPE_NAME("neoverse-v1"),
-        ARM_CPU_TYPE_NAME("neoverse-n2"),
+    machine_class_add_valid_cpu_type(mc, ARM_CPU_TYPE_NAME("cortex-a35"));
+    machine_class_add_valid_cpu_type(mc, ARM_CPU_TYPE_NAME("cortex-a55"));
+    machine_class_add_valid_cpu_type(mc, ARM_CPU_TYPE_NAME("cortex-a72"));
+    machine_class_add_valid_cpu_type(mc, ARM_CPU_TYPE_NAME("cortex-a76"));
+    machine_class_add_valid_cpu_type(mc, ARM_CPU_TYPE_NAME("cortex-a710"));
+    machine_class_add_valid_cpu_type(mc, ARM_CPU_TYPE_NAME("a64fx"));
+    machine_class_add_valid_cpu_type(mc, ARM_CPU_TYPE_NAME("neoverse-n1"));
+    machine_class_add_valid_cpu_type(mc, ARM_CPU_TYPE_NAME("neoverse-v1"));
+    machine_class_add_valid_cpu_type(mc, ARM_CPU_TYPE_NAME("neoverse-n2"));
 #endif /* TARGET_AARCH64 */
 #endif /* CONFIG_TCG */
 #ifdef TARGET_AARCH64
-        ARM_CPU_TYPE_NAME("cortex-a53"),
-        ARM_CPU_TYPE_NAME("cortex-a57"),
+    machine_class_add_valid_cpu_type(mc, ARM_CPU_TYPE_NAME("cortex-a53"));
+    machine_class_add_valid_cpu_type(mc, ARM_CPU_TYPE_NAME("cortex-a57"));
 #if defined(CONFIG_KVM) || defined(CONFIG_HVF)
-        ARM_CPU_TYPE_NAME("host"),
+    machine_class_add_valid_cpu_type(mc, ARM_CPU_TYPE_NAME("host"));
 #endif /* CONFIG_KVM || CONFIG_HVF */
 #endif /* TARGET_AARCH64 */
-        ARM_CPU_TYPE_NAME("max"),
-        NULL
-    };
+    machine_class_add_valid_cpu_type(mc, ARM_CPU_TYPE_NAME("max"));
 
     mc->init = machvirt_init;
     /* Start with max_cpus set to 512, which is the maximum supported by KVM.
@@ -3182,7 +3180,6 @@ static void virt_machine_class_init(ObjectClass *oc, void *data)
 #else
     mc->default_cpu_type = ARM_CPU_TYPE_NAME("max");
 #endif
-    mc->valid_cpu_types = valid_cpu_types;
     mc->get_default_cpu_node_id = virt_get_default_cpu_node_id;
     mc->kvm_type = virt_kvm_type;
     mc->hvf_get_physical_address_range = virt_hvf_get_physical_address_range;
-- 
2.47.1

[RFC PATCH-for-10.1 35/39] hw/arm/virt: Replace TARGET_AARCH64 -> target_long_bits()

[Philippe Mathieu-Daudé]

Replace the target-specific TARGET_AARCH64 definition
by a call to the generic target_long_bits() helper.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
 hw/arm/virt.c | 32 ++++++++++++++++----------------
 1 file changed, 16 insertions(+), 16 deletions(-)

diff --git a/hw/arm/virt.c b/hw/arm/virt.c
index e241e71e1c3..a020f1bd581 100644
--- a/hw/arm/virt.c
+++ b/hw/arm/virt.c
@@ -3133,25 +3133,25 @@ static void virt_machine_class_init(ObjectClass *oc, void *data)
 #ifdef CONFIG_TCG
     machine_class_add_valid_cpu_type(mc, ARM_CPU_TYPE_NAME("cortex-a7"));
     machine_class_add_valid_cpu_type(mc, ARM_CPU_TYPE_NAME("cortex-a15"));
-#ifdef TARGET_AARCH64
-    machine_class_add_valid_cpu_type(mc, ARM_CPU_TYPE_NAME("cortex-a35"));
-    machine_class_add_valid_cpu_type(mc, ARM_CPU_TYPE_NAME("cortex-a55"));
-    machine_class_add_valid_cpu_type(mc, ARM_CPU_TYPE_NAME("cortex-a72"));
-    machine_class_add_valid_cpu_type(mc, ARM_CPU_TYPE_NAME("cortex-a76"));
-    machine_class_add_valid_cpu_type(mc, ARM_CPU_TYPE_NAME("cortex-a710"));
-    machine_class_add_valid_cpu_type(mc, ARM_CPU_TYPE_NAME("a64fx"));
-    machine_class_add_valid_cpu_type(mc, ARM_CPU_TYPE_NAME("neoverse-n1"));
-    machine_class_add_valid_cpu_type(mc, ARM_CPU_TYPE_NAME("neoverse-v1"));
-    machine_class_add_valid_cpu_type(mc, ARM_CPU_TYPE_NAME("neoverse-n2"));
-#endif /* TARGET_AARCH64 */
+    if (target_long_bits() == 64) {
+        machine_class_add_valid_cpu_type(mc, ARM_CPU_TYPE_NAME("cortex-a35"));
+        machine_class_add_valid_cpu_type(mc, ARM_CPU_TYPE_NAME("cortex-a55"));
+        machine_class_add_valid_cpu_type(mc, ARM_CPU_TYPE_NAME("cortex-a72"));
+        machine_class_add_valid_cpu_type(mc, ARM_CPU_TYPE_NAME("cortex-a76"));
+        machine_class_add_valid_cpu_type(mc, ARM_CPU_TYPE_NAME("cortex-a710"));
+        machine_class_add_valid_cpu_type(mc, ARM_CPU_TYPE_NAME("a64fx"));
+        machine_class_add_valid_cpu_type(mc, ARM_CPU_TYPE_NAME("neoverse-n1"));
+        machine_class_add_valid_cpu_type(mc, ARM_CPU_TYPE_NAME("neoverse-v1"));
+        machine_class_add_valid_cpu_type(mc, ARM_CPU_TYPE_NAME("neoverse-n2"));
+    }
 #endif /* CONFIG_TCG */
-#ifdef TARGET_AARCH64
-    machine_class_add_valid_cpu_type(mc, ARM_CPU_TYPE_NAME("cortex-a53"));
-    machine_class_add_valid_cpu_type(mc, ARM_CPU_TYPE_NAME("cortex-a57"));
+    if (target_long_bits() == 64) {
+        machine_class_add_valid_cpu_type(mc, ARM_CPU_TYPE_NAME("cortex-a53"));
+        machine_class_add_valid_cpu_type(mc, ARM_CPU_TYPE_NAME("cortex-a57"));
 #if defined(CONFIG_KVM) || defined(CONFIG_HVF)
-    machine_class_add_valid_cpu_type(mc, ARM_CPU_TYPE_NAME("host"));
+        machine_class_add_valid_cpu_type(mc, ARM_CPU_TYPE_NAME("host"));
 #endif /* CONFIG_KVM || CONFIG_HVF */
-#endif /* TARGET_AARCH64 */
+    }
     machine_class_add_valid_cpu_type(mc, ARM_CPU_TYPE_NAME("max"));
 
     mc->init = machvirt_init;
-- 
2.47.1

[RFC PATCH-for-10.1 36/39] target/arm: Expose Aarch64 helpers indistinctly

[Philippe Mathieu-Daudé]

At worst, for 32-bit arm binary, using these methods will
now produce a link time error, instead of a compile time one.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
 target/arm/internals.h | 2 --
 1 file changed, 2 deletions(-)

diff --git a/target/arm/internals.h b/target/arm/internals.h
index 86577207b85..f9353887415 100644
--- a/target/arm/internals.h
+++ b/target/arm/internals.h
@@ -1810,7 +1810,6 @@ static inline uint64_t pmu_counter_mask(CPUARMState *env)
   return (1ULL << 31) | ((1ULL << pmu_num_counters(env)) - 1);
 }
 
-#ifdef TARGET_AARCH64
 GDBFeature *arm_gen_dynamic_svereg_feature(CPUState *cpu, int base_reg);
 int aarch64_gdb_get_sve_reg(CPUState *cs, GByteArray *buf, int reg);
 int aarch64_gdb_set_sve_reg(CPUState *cs, uint8_t *buf, int reg);
@@ -1828,7 +1827,6 @@ void aarch64_max_tcg_initfn(Object *obj);
 void aarch64_add_pauth_properties(Object *obj);
 void aarch64_add_sve_properties(Object *obj);
 void aarch64_add_sme_properties(Object *obj);
-#endif
 
 /* Read the CONTROL register as the MRS instruction would. */
 uint32_t arm_v7m_mrs_control(CPUARMState *env, uint32_t secure);
-- 
2.47.1

[RFC PATCH-for-10.1 37/39] hw/arm: Build virt.c once

[Philippe Mathieu-Daudé]

Previous commits removed the TARGET_AARCH64 uses in virt.c,
we can now move it to arm_common_ss[] and build it once.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
 hw/arm/meson.build | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/hw/arm/meson.build b/hw/arm/meson.build
index 7eb49c7327f..c46e5036722 100644
--- a/hw/arm/meson.build
+++ b/hw/arm/meson.build
@@ -1,6 +1,6 @@
 arm_ss = ss.source_set()
 arm_common_ss = ss.source_set()
-arm_ss.add(when: 'CONFIG_ARM_VIRT', if_true: files('virt.c'))
+arm_common_ss.add(when: 'CONFIG_ARM_VIRT', if_true: files('virt.c'))
 arm_common_ss.add(when: 'CONFIG_ACPI', if_true: files('virt-acpi-build.c'))
 arm_common_ss.add(when: 'CONFIG_DIGIC', if_true: files('digic_boards.c'))
 arm_common_ss.add(when: 'CONFIG_EMCRAFT_SF2', if_true: files('msf2-som.c'))
-- 
2.47.1

[RFC PATCH-for-10.1 38/39] hw/arm: Move xen files to arm_common_ss[]

[Philippe Mathieu-Daudé]

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
XXX untested
---
 hw/arm/meson.build | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/hw/arm/meson.build b/hw/arm/meson.build
index c46e5036722..61f145f901f 100644
--- a/hw/arm/meson.build
+++ b/hw/arm/meson.build
@@ -63,7 +63,7 @@ arm_common_ss.add(when: 'CONFIG_FSL_IMX8MP_EVK', if_true: files('imx8mp-evk.c'))
 arm_common_ss.add(when: 'CONFIG_ARM_SMMUV3', if_true: files('smmuv3.c'))
 arm_common_ss.add(when: 'CONFIG_FSL_IMX6UL', if_true: files('fsl-imx6ul.c', 'mcimx6ul-evk.c'))
 arm_common_ss.add(when: 'CONFIG_NRF51_SOC', if_true: files('nrf51_soc.c'))
-arm_ss.add(when: 'CONFIG_XEN', if_true: files(
+arm_common_ss.add(when: 'CONFIG_XEN', if_true: files(
   'xen-stubs.c',
   'xen-pvh.c',
 ))
-- 
2.47.1

[RFC PATCH-for-10.1 39/39] hw/arm/meson: Remove arm_ss[] source set

[Philippe Mathieu-Daudé]

All units are now built as common objects.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
Yay!
---
 hw/arm/meson.build | 2 --
 1 file changed, 2 deletions(-)

diff --git a/hw/arm/meson.build b/hw/arm/meson.build
index 61f145f901f..476e6048939 100644
--- a/hw/arm/meson.build
+++ b/hw/arm/meson.build
@@ -1,4 +1,3 @@
-arm_ss = ss.source_set()
 arm_common_ss = ss.source_set()
 arm_common_ss.add(when: 'CONFIG_ARM_VIRT', if_true: files('virt.c'))
 arm_common_ss.add(when: 'CONFIG_ACPI', if_true: files('virt-acpi-build.c'))
@@ -81,5 +80,4 @@ arm_common_ss.add(when: 'CONFIG_VEXPRESS', if_true: files('vexpress.c'))
 
 arm_common_ss.add(fdt, files('boot.c'))
 
-hw_arch += {'arm': arm_ss}
 hw_common_arch += {'arm': arm_common_ss}
-- 
2.47.1

Re: [RFC PATCH-for-10.1 38/39] hw/arm: Move xen files to arm_common_ss[]

[Philippe Mathieu-Daudé]

On 4/4/25 01:58, Philippe Mathieu-Daudé wrote:
> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
> ---
> XXX untested

Now with Xen setup accessible, so tested. What is missing:

-- >8 --
diff --git a/hw/arm/xen-pvh.c b/hw/arm/xen-pvh.c
index d1509bd235..8e81947c7d 100644
--- a/hw/arm/xen-pvh.c
+++ b/hw/arm/xen-pvh.c
@@ -12,3 +12,2 @@
  #include "hw/xen/xen-pvh-common.h"
-#include "hw/xen/arch_hvm.h"

diff --git a/hw/arm/xen-stubs.c b/hw/arm/xen-stubs.c
index 5551584dc2..f3681835d7 100644
--- a/hw/arm/xen-stubs.c
+++ b/hw/arm/xen-stubs.c
@@ -11,3 +11,3 @@
  #include "hw/xen/xen-hvm-common.h"
-#include "hw/xen/arch_hvm.h"
+#include "hw/arm/xen_arch_hvm.h"

---

Otherwise we get:

In file included from ../../hw/arm/xen-pvh.c:13:
include/hw/xen/arch_hvm.h:1:13: error: attempt to use poisoned "TARGET_I386"
     1 | #if defined(TARGET_I386) || defined(TARGET_X86_64)
       |             ^
include/hw/xen/arch_hvm.h:1:37: error: attempt to use poisoned 
"TARGET_X86_64"
     1 | #if defined(TARGET_I386) || defined(TARGET_X86_64)
       |                                     ^

> ---
>   hw/arm/meson.build | 2 +-
>   1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/hw/arm/meson.build b/hw/arm/meson.build
> index c46e5036722..61f145f901f 100644
> --- a/hw/arm/meson.build
> +++ b/hw/arm/meson.build
> @@ -63,7 +63,7 @@ arm_common_ss.add(when: 'CONFIG_FSL_IMX8MP_EVK', if_true: files('imx8mp-evk.c'))
>   arm_common_ss.add(when: 'CONFIG_ARM_SMMUV3', if_true: files('smmuv3.c'))
>   arm_common_ss.add(when: 'CONFIG_FSL_IMX6UL', if_true: files('fsl-imx6ul.c', 'mcimx6ul-evk.c'))
>   arm_common_ss.add(when: 'CONFIG_NRF51_SOC', if_true: files('nrf51_soc.c'))
> -arm_ss.add(when: 'CONFIG_XEN', if_true: files(
> +arm_common_ss.add(when: 'CONFIG_XEN', if_true: files(
>     'xen-stubs.c',
>     'xen-pvh.c',
>   ))

Re: [RFC PATCH-for-10.1 00/39] single-binary: Make hw/arm/ common

[Pierrick Bouvier]

On 4/3/25 16:57, Philippe Mathieu-Daudé wrote:
> Hi,
> 
> At this point this series is mostly a draft for Pierrick.
> 
> After introducing the generic TargetInfo API [*], we implement
> the ARM variants, then use the API to remove target-specific code,
> allowing to eventually remove the target-specific arm_ss[] source
> set in meson.build, having all objects in arm_common_ss[].
> Various header cleanups are necessary before getting there.
> 

As there are some changes asked on this API, I think it's better if we 
review this series later.

I'll still comment a few commits here that point some problems in the 
approach.

> Regards,
> 
> Phil.
> 
> Available here, based on tcg-next:
> https://gitlab.com/philmd/qemu/-/tags/single-binary-hw-arm-rfc-v1
> 
> [*] https://lore.kernel.org/qemu-devel/20250403234914.9154-1-philmd@linaro.org/
> 
> Philippe Mathieu-Daudé (39):
>    target/arm: Implement per-binary TargetInfo structures
>    target/arm: Register TYPE_BINARY_QEMU_SYSTEM_ARM/AARCH64 interfaces
>    target/arm: Filter CPU types for binary
>    hw/arm: Filter machine types for binary
>    hw/arm/aspeed: Filter machine types for binary
>    hw/arm/aspeed: Build objects once
>    hw/arm/raspi: Filter machine types for binary
>    hw/arm/raspi: Build objects once
>    target/arm/cpregs: Include missing 'target/arm/cpu.h' header
>    hw/arm/boot: Include missing 'system/memory.h' header
>    hw/arm: Use full "target/arm/cpu.h" path to include target's "cpu.h"
>    target/arm/cpu-features: Include missing 'cpu.h' header
>    target/arm/qmp: Include missing 'cpu.h' header
>    target/arm/kvm: Include missing 'cpu-qom.h' header
>    target/arm/hvf: Include missing 'cpu-qom.h' header
>    hw/arm: Remove unnecessary 'cpu.h' header
>    target/arm: Restrict inclusion of 'multiprocessing.h'
>    target/arm: Move some definitions from 'cpu.h' to 'multiprocessing.h'
>    hw/arm: Include missing 'target/arm/gtimer.h' header
>    target/arm: Extract PSCI definitions to 'psci.h'
>    target/arm: Extract feature definitions to 'cpu_has_feature.h' header
>    target/arm: Add arm_cpu_has_feature() helper
>    hw/arm/realview: Replace arm_feature() -> arm_cpu_has_feature()
>    hw/arm/virt-acpi: Replace arm_feature() -> arm_cpu_has_feature()
>    hw/arm: Build virt-acpi-build.c once
>    system/hvf: Avoid including 'cpu.h'
>    system/hvf: Expose hvf_enabled() to common code
>    exec: Do not poison hardware accelerators
>    hw/arm: Build sbsa-ref.c once
>    target/arm: Replace target_ulong -> hwaddr in ARMMMUFaultInfo
>    target/arm: Replace target_ulong -> uint64_t for HWBreakpoint
>    target/arm: Replace target_ulong -> vaddr for CPUWatchpoint
>    hw/core/machine: Allow dynamic registration of valid CPU types
>    hw/arm/virt: Register valid CPU types dynamically
>    hw/arm/virt: Replace TARGET_AARCH64 -> target_long_bits()
>    target/arm: Expose Aarch64 helpers indistinctly
>    hw/arm: Build virt.c once
>    hw/arm: Move xen files to arm_common_ss[]
>    hw/arm/meson: Remove arm_ss[] source set
> 
>   MAINTAINERS                              |  1 +
>   meson.build                              |  1 +
>   include/exec/poison.h                    |  4 --
>   include/hw/arm/boot.h                    |  3 +-
>   include/hw/arm/digic.h                   |  2 +-
>   include/hw/arm/fsl-imx6.h                |  2 +-
>   include/hw/arm/fsl-imx6ul.h              |  2 +-
>   include/hw/arm/fsl-imx7.h                |  2 +-
>   include/hw/arm/fsl-imx8mp.h              |  2 +-
>   include/hw/boards.h                      |  8 +++
>   include/qemu/target_info-qom.h           | 20 ++++++
>   include/system/hvf.h                     | 17 ++++--
>   include/system/hvf_int.h                 |  2 +
>   target/arm/cpregs.h                      |  1 +
>   target/arm/cpu-features.h                |  1 +
>   target/arm/cpu.h                         | 78 +-----------------------
>   target/arm/cpu_has_feature.h             | 67 ++++++++++++++++++++
>   target/arm/hvf_arm.h                     |  2 +-
>   target/arm/internals.h                   | 22 +++----
>   target/arm/kvm_arm.h                     |  1 +
>   target/arm/multiprocessing.h             | 18 ++++++
>   target/arm/psci.h                        | 18 ++++++
>   accel/stubs/hvf-stub.c                   | 12 ++++
>   hw/arm/aspeed.c                          | 30 ++++++---
>   hw/arm/aspeed_ast2600.c                  |  1 +
>   hw/arm/aspeed_ast27x0.c                  |  2 +
>   hw/arm/b-l475e-iot01a.c                  |  1 +
>   hw/arm/bananapi_m2u.c                    |  1 +
>   hw/arm/bcm2836.c                         |  4 --
>   hw/arm/bcm2838.c                         |  1 +
>   hw/arm/boot.c                            |  2 +
>   hw/arm/collie.c                          |  1 +
>   hw/arm/exynos4210.c                      |  3 +-
>   hw/arm/exynos4_boards.c                  |  1 +
>   hw/arm/fby35.c                           |  1 +
>   hw/arm/fsl-imx8mp.c                      |  1 +
>   hw/arm/highbank.c                        |  4 +-
>   hw/arm/imx8mp-evk.c                      |  1 +
>   hw/arm/mcimx6ul-evk.c                    |  1 +
>   hw/arm/mcimx7d-sabre.c                   |  1 +
>   hw/arm/microbit.c                        |  1 +
>   hw/arm/mps2-tz.c                         |  4 ++
>   hw/arm/mps2.c                            |  4 ++
>   hw/arm/mps3r.c                           |  3 +-
>   hw/arm/musca.c                           |  2 +
>   hw/arm/npcm8xx.c                         |  2 +
>   hw/arm/omap_sx1.c                        |  2 +
>   hw/arm/orangepi.c                        |  1 +
>   hw/arm/raspi.c                           |  9 +--
>   hw/arm/raspi4b.c                         |  1 +
>   hw/arm/realview.c                        | 14 +++--
>   hw/arm/sbsa-ref.c                        |  3 +
>   hw/arm/smmuv3.c                          |  1 -
>   hw/arm/stellaris.c                       |  3 +
>   hw/arm/versatilepb.c                     |  1 +
>   hw/arm/vexpress.c                        |  2 +
>   hw/arm/virt-acpi-build.c                 |  4 +-
>   hw/arm/virt.c                            | 44 +++++++------
>   hw/arm/xilinx_zynq.c                     |  1 +
>   hw/arm/xlnx-versal-virt.c                |  2 +
>   hw/arm/xlnx-zcu102.c                     |  2 +
>   hw/core/machine.c                        | 28 +++++++++
>   hw/vmapple/vmapple.c                     |  3 +
>   target/arm/arm-qmp-cmds.c                |  1 +
>   target/arm/cpu.c                         | 10 +++
>   target/arm/cpu64.c                       |  2 +
>   target/arm/helper.c                      |  1 +
>   target/arm/hvf/hvf.c                     |  1 +
>   target/arm/hyp_gdbstub.c                 | 14 ++---
>   target/arm/kvm.c                         |  1 +
>   target/arm/target_info-aarch64-softmmu.c | 24 ++++++++
>   target/arm/target_info-arm-softmmu.c     | 24 ++++++++
>   target/arm/tcg/op_helper.c               |  2 +
>   target/arm/tcg/psci.c                    |  1 +
>   target_info-qom.c                        |  8 +++
>   accel/stubs/meson.build                  |  1 +
>   hw/arm/meson.build                       | 22 ++++---
>   scripts/make-config-poison.sh            |  4 ++
>   target/arm/meson.build                   |  5 ++
>   79 files changed, 429 insertions(+), 171 deletions(-)
>   create mode 100644 target/arm/cpu_has_feature.h
>   create mode 100644 target/arm/psci.h
>   create mode 100644 accel/stubs/hvf-stub.c
>   create mode 100644 target/arm/target_info-aarch64-softmmu.c
>   create mode 100644 target/arm/target_info-arm-softmmu.c
> 

Re: [RFC PATCH-for-10.1 00/39] single-binary: Make hw/arm/ common

[Philippe Mathieu-Daudé]

On 4/4/25 19:12, Pierrick Bouvier wrote:
> On 4/3/25 16:57, Philippe Mathieu-Daudé wrote:
>> Hi,
>>
>> At this point this series is mostly a draft for Pierrick.
>>
>> After introducing the generic TargetInfo API [*], we implement
>> the ARM variants, then use the API to remove target-specific code,
>> allowing to eventually remove the target-specific arm_ss[] source
>> set in meson.build, having all objects in arm_common_ss[].
>> Various header cleanups are necessary before getting there.
>>
> 
> As there are some changes asked on this API, I think it's better if we 
> review this series later.

I think I misunderstood your comments in my series [*] reworking
arm_cpu_has_feature(), I thought you wanted to see why it was for
(completing your 'Make hw/arm/ common' effort).

> I'll still comment a few commits here that point some problems in the 
> approach.

Thanks!

[*] 
https://lore.kernel.org/qemu-devel/cecbab0f-56f2-434a-8508-8a4df2992259@linaro.org/

Re: [RFC PATCH-for-10.1 01/39] target/arm: Implement per-binary TargetInfo structures

[Pierrick Bouvier]

On 4/3/25 16:57, Philippe Mathieu-Daudé wrote:
> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
> ---
>   meson.build                              |  1 +
>   target/arm/target_info-aarch64-softmmu.c | 24 ++++++++++++++++++++++++
>   target/arm/target_info-arm-softmmu.c     | 24 ++++++++++++++++++++++++
>   target/arm/meson.build                   |  5 +++++
>   4 files changed, 54 insertions(+)
>   create mode 100644 target/arm/target_info-aarch64-softmmu.c
>   create mode 100644 target/arm/target_info-arm-softmmu.c
> 
> diff --git a/meson.build b/meson.build
> index b93253166c8..9df662932a4 100644
> --- a/meson.build
> +++ b/meson.build
> @@ -3263,6 +3263,7 @@ host_kconfig = \
>   ignored = [ 'TARGET_XML_FILES', 'TARGET_ABI_DIR', 'TARGET_ARCH' ]
>   
>   target_info = [
> +  'arm-softmmu', 'aarch64-softmmu',
>   ]
>   
>   default_targets = 'CONFIG_DEFAULT_TARGETS' in config_host
> diff --git a/target/arm/target_info-aarch64-softmmu.c b/target/arm/target_info-aarch64-softmmu.c
> new file mode 100644
> index 00000000000..002aac642f8
> --- /dev/null
> +++ b/target/arm/target_info-aarch64-softmmu.c
> @@ -0,0 +1,24 @@
> +/*
> + * QEMU legacy binary helpers
> + *
> + *  Copyright (c) Linaro
> + *
> + * SPDX-License-Identifier: GPL-2.0-or-later
> + */
> +
> +#include "qemu/osdep.h"
> +#include "qemu/target_info-impl.h"
> +#include "cpu-qom.h"
> +
> +static const BinaryTargetInfo target_info_aarch64_system = {
> +    .name = "aarch64",
> +    .system_arch = SYS_EMU_TARGET_AARCH64,
> +    .endianness = ENDIAN_MODE_LITTLE,
> +    .long_bits = 64,
> +    .cpu_resolving_type = TYPE_ARM_CPU,
> +};
> +
> +const BinaryTargetInfo *target_info(void)
> +{
> +    return &target_info_aarch64_system;
> +}
> diff --git a/target/arm/target_info-arm-softmmu.c b/target/arm/target_info-arm-softmmu.c
> new file mode 100644
> index 00000000000..24b68b1ad8b
> --- /dev/null
> +++ b/target/arm/target_info-arm-softmmu.c
> @@ -0,0 +1,24 @@
> +/*
> + * QEMU legacy binary helpers
> + *
> + *  Copyright (c) Linaro
> + *
> + * SPDX-License-Identifier: GPL-2.0-or-later
> + */
> +
> +#include "qemu/osdep.h"
> +#include "qemu/target_info-impl.h"
> +#include "cpu-qom.h"
> +
> +static const BinaryTargetInfo target_info_arm_system = {
> +    .name = "arm",
> +    .system_arch = SYS_EMU_TARGET_ARM,
> +    .endianness = ENDIAN_MODE_LITTLE,
> +    .long_bits = 32,
> +    .cpu_resolving_type = TYPE_ARM_CPU,
> +};
> +
> +const BinaryTargetInfo *target_info(void)
> +{
> +    return &target_info_arm_system;
> +}
> diff --git a/target/arm/meson.build b/target/arm/meson.build
> index 3065081d241..706c49c1b2a 100644
> --- a/target/arm/meson.build
> +++ b/target/arm/meson.build
> @@ -25,6 +25,11 @@ arm_system_ss.add(files(
>     'machine.c',
>     'ptw.c',
>   ))
> +arm_system_ss.add(when: 'TARGET_AARCH64', if_true: files(
> +  'target_info-aarch64-softmmu.c',
> +), if_false: files(
> +  'target_info-arm-softmmu.c',
> +))
>   

Using a dictionary for keeping target_info source files, we avoid this 
if, it will become:
target_info += {'aarch64-softmmu': [target_info-aarch64-softmmu.c]}
target_info += {'arm-softmmu': [target_info-arm-softmmu.c]}

>   arm_user_ss = ss.source_set()
>   

Re: [RFC PATCH-for-10.1 03/39] target/arm: Filter CPU types for binary

[Pierrick Bouvier]

On 4/3/25 16:57, Philippe Mathieu-Daudé wrote:
> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
> ---
>   target/arm/cpu.c   | 2 ++
>   target/arm/cpu64.c | 2 ++
>   2 files changed, 4 insertions(+)
> 
> diff --git a/target/arm/cpu.c b/target/arm/cpu.c
> index 377791c84dd..b1aa482c726 100644
> --- a/target/arm/cpu.c
> +++ b/target/arm/cpu.c
> @@ -50,6 +50,7 @@
>   #include "disas/capstone.h"
>   #include "fpu/softfloat.h"
>   #include "cpregs.h"
> +#include "qemu/target_info-qom.h"
>   #include "target/arm/cpu-qom.h"
>   #include "target/arm/gtimer.h"
>   
> @@ -2759,6 +2760,7 @@ void arm_cpu_register(const ARMCPUInfo *info)
>           .instance_init = arm_cpu_instance_init,
>           .class_init = info->class_init ?: cpu_register_class_init,
>           .class_data = (void *)info,
> +        .interfaces = LEGACY_BINARY_QEMU_SYSTEM_ARM_INTERFACE,
>       };
>   
>       type_info.name = g_strdup_printf("%s-" TYPE_ARM_CPU, info->name);
> diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
> index 8188ede5cc8..9f8c98563ac 100644
> --- a/target/arm/cpu64.c
> +++ b/target/arm/cpu64.c
> @@ -24,6 +24,7 @@
>   #include "cpregs.h"
>   #include "qemu/module.h"
>   #include "qemu/units.h"
> +#include "qemu/target_info-qom.h"
>   #include "system/kvm.h"
>   #include "system/hvf.h"
>   #include "system/qtest.h"
> @@ -856,6 +857,7 @@ void aarch64_cpu_register(const ARMCPUInfo *info)
>           .instance_init = aarch64_cpu_instance_init,
>           .class_init = info->class_init ?: cpu_register_class_init,
>           .class_data = (void *)info,
> +        .interfaces = LEGACY_BINARY_QEMU_SYSTEM_AARCH64_INTERFACE,
>       };
>   
>       type_info.name = g_strdup_printf("%s-" TYPE_ARM_CPU, info->name);

I would stick to specific CPU interface type, instead of using any 
SYSTEM_AARCH64 type.

TYPE_TARGET_CPU_ARM, TYPE_TARGET_CPU_AARCH64.
And for machines:
TYPE_TARGET_MACHINE_ARM, TYPE_TARGET_MACHINE_AARCH64.

Re: [RFC PATCH-for-10.1 11/39] hw/arm: Use full "target/arm/cpu.h" path to include target's "cpu.h"

[Pierrick Bouvier]

On 4/3/25 16:57, Philippe Mathieu-Daudé wrote:
> We would like to get rid of '-I target/$ARCH/' in the CPPFLAGS.

While this change is correct, this is not strictly needed.
With the current approach, using a set of common files per architecture, 
we can rely on this include to be present, and it does not block from 
having common files.

> Use the full path to "cpu.h": "target/arm/cpu.h".
> 
> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
> ---
>   include/hw/arm/digic.h      | 2 +-
>   include/hw/arm/fsl-imx6.h   | 2 +-
>   include/hw/arm/fsl-imx6ul.h | 2 +-
>   include/hw/arm/fsl-imx7.h   | 2 +-
>   include/hw/arm/fsl-imx8mp.h | 2 +-
>   5 files changed, 5 insertions(+), 5 deletions(-)
> 
> diff --git a/include/hw/arm/digic.h b/include/hw/arm/digic.h
> index 8f2735c284f..646802806e0 100644
> --- a/include/hw/arm/digic.h
> +++ b/include/hw/arm/digic.h
> @@ -18,7 +18,7 @@
>   #ifndef HW_ARM_DIGIC_H
>   #define HW_ARM_DIGIC_H
>   
> -#include "cpu.h"
> +#include "target/arm/cpu.h"
>   #include "hw/timer/digic-timer.h"
>   #include "hw/char/digic-uart.h"
>   #include "qom/object.h"
> diff --git a/include/hw/arm/fsl-imx6.h b/include/hw/arm/fsl-imx6.h
> index 124bbd478fd..0ac145cf6ba 100644
> --- a/include/hw/arm/fsl-imx6.h
> +++ b/include/hw/arm/fsl-imx6.h
> @@ -35,7 +35,7 @@
>   #include "hw/pci-host/designware.h"
>   #include "hw/or-irq.h"
>   #include "system/memory.h"
> -#include "cpu.h"
> +#include "target/arm/cpu.h"
>   #include "qom/object.h"
>   
>   #define TYPE_FSL_IMX6 "fsl-imx6"
> diff --git a/include/hw/arm/fsl-imx6ul.h b/include/hw/arm/fsl-imx6ul.h
> index 4e3209b25b2..f8f9c249a23 100644
> --- a/include/hw/arm/fsl-imx6ul.h
> +++ b/include/hw/arm/fsl-imx6ul.h
> @@ -34,7 +34,7 @@
>   #include "hw/usb/chipidea.h"
>   #include "hw/usb/imx-usb-phy.h"
>   #include "system/memory.h"
> -#include "cpu.h"
> +#include "target/arm/cpu.h"
>   #include "qom/object.h"
>   #include "qemu/units.h"
>   
> diff --git a/include/hw/arm/fsl-imx7.h b/include/hw/arm/fsl-imx7.h
> index aa7818c4999..6aedd2b80b5 100644
> --- a/include/hw/arm/fsl-imx7.h
> +++ b/include/hw/arm/fsl-imx7.h
> @@ -37,7 +37,7 @@
>   #include "hw/pci-host/designware.h"
>   #include "hw/usb/chipidea.h"
>   #include "hw/or-irq.h"
> -#include "cpu.h"
> +#include "target/arm/cpu.h"
>   #include "qom/object.h"
>   #include "qemu/units.h"
>   
> diff --git a/include/hw/arm/fsl-imx8mp.h b/include/hw/arm/fsl-imx8mp.h
> index bc97fc416eb..f20f9e53187 100644
> --- a/include/hw/arm/fsl-imx8mp.h
> +++ b/include/hw/arm/fsl-imx8mp.h
> @@ -9,7 +9,7 @@
>   #ifndef FSL_IMX8MP_H
>   #define FSL_IMX8MP_H
>   
> -#include "cpu.h"
> +#include "target/arm/cpu.h"
>   #include "hw/char/imx_serial.h"
>   #include "hw/gpio/imx_gpio.h"
>   #include "hw/i2c/imx_i2c.h"

Re: [RFC PATCH-for-10.1 20/39] target/arm: Extract PSCI definitions to 'psci.h'

[Pierrick Bouvier]

On 4/3/25 16:58, Philippe Mathieu-Daudé wrote:
> Extract PSCI definitions (which are not target specific)
> to the new "target/arm/psci.h", so code from hw/arm/ can
> use them without having to include the target specific
> "cpu.h" header.
> 

Including cpu.h is not a problem to have common code (per architecture), 
so there is no need to do any change here.

> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
> ---
>   include/hw/arm/boot.h      |  3 ++-
>   target/arm/cpu.h           |  6 ------
>   target/arm/psci.h          | 18 ++++++++++++++++++
>   hw/arm/bananapi_m2u.c      |  1 +
>   hw/arm/boot.c              |  1 +
>   hw/arm/highbank.c          |  1 +
>   hw/arm/imx8mp-evk.c        |  1 +
>   hw/arm/mcimx6ul-evk.c      |  1 +
>   hw/arm/mcimx7d-sabre.c     |  1 +
>   hw/arm/orangepi.c          |  1 +
>   hw/arm/sbsa-ref.c          |  1 +
>   hw/arm/virt-acpi-build.c   |  1 +
>   hw/arm/virt.c              |  1 +
>   hw/arm/xlnx-versal-virt.c  |  1 +
>   hw/arm/xlnx-zcu102.c       |  1 +
>   hw/vmapple/vmapple.c       |  1 +
>   target/arm/helper.c        |  1 +
>   target/arm/hvf/hvf.c       |  1 +
>   target/arm/tcg/op_helper.c |  1 +
>   target/arm/tcg/psci.c      |  1 +
>   20 files changed, 37 insertions(+), 7 deletions(-)
>   create mode 100644 target/arm/psci.h
> 
> diff --git a/include/hw/arm/boot.h b/include/hw/arm/boot.h
> index b12bf61ca81..648fdb88862 100644
> --- a/include/hw/arm/boot.h
> +++ b/include/hw/arm/boot.h
> @@ -12,6 +12,7 @@
>   #define HW_ARM_BOOT_H
>   
>   #include "target/arm/cpu-qom.h"
> +//#include "target/arm/psci.h"
>   #include "qemu/notify.h"
>   
>   typedef enum {
> @@ -100,7 +101,7 @@ struct arm_boot_info {
>        * as the conduit specifies calls should go to (eg guest firmware booted
>        * to EL3) then PSCI will not be enabled.
>        */
> -    int psci_conduit;
> +    int psci_conduit;//
>       /* Used internally by arm_boot.c */
>       int is_linux;
>       hwaddr initrd_start;
> diff --git a/target/arm/cpu.h b/target/arm/cpu.h
> index 0db7292698c..930c5366029 100644
> --- a/target/arm/cpu.h
> +++ b/target/arm/cpu.h
> @@ -3104,12 +3104,6 @@ static inline bool bswap_code(bool sctlr_b)
>   void cpu_get_tb_cpu_state(CPUARMState *env, vaddr *pc,
>                             uint64_t *cs_base, uint32_t *flags);
>   
> -enum {
> -    QEMU_PSCI_CONDUIT_DISABLED = 0,
> -    QEMU_PSCI_CONDUIT_SMC = 1,
> -    QEMU_PSCI_CONDUIT_HVC = 2,
> -};
> -
>   #ifndef CONFIG_USER_ONLY
>   /* Return the address space index to use for a memory access */
>   static inline int arm_asidx_from_attrs(CPUState *cs, MemTxAttrs attrs)
> diff --git a/target/arm/psci.h b/target/arm/psci.h
> new file mode 100644
> index 00000000000..8b868dfbb91
> --- /dev/null
> +++ b/target/arm/psci.h
> @@ -0,0 +1,18 @@
> +/*
> + * ARM Power State Coordination Interface (PSCI) definitions
> + *
> + *  Copyright (c) 2003 Fabrice Bellard
> + *
> + * SPDX-License-Identifier: LGPL-2.1-or-later
> + */
> +
> +#ifndef TARGET_ARM_PSCI_H
> +#define TARGET_ARM_PSCI_H
> +
> +enum {
> +    QEMU_PSCI_CONDUIT_DISABLED = 0,
> +    QEMU_PSCI_CONDUIT_SMC = 1,
> +    QEMU_PSCI_CONDUIT_HVC = 2,
> +};
> +
> +#endif
> diff --git a/hw/arm/bananapi_m2u.c b/hw/arm/bananapi_m2u.c
> index b750a575f72..61e01a38099 100644
> --- a/hw/arm/bananapi_m2u.c
> +++ b/hw/arm/bananapi_m2u.c
> @@ -27,6 +27,7 @@
>   #include "hw/qdev-properties.h"
>   #include "hw/arm/allwinner-r40.h"
>   #include "hw/arm/boot.h"
> +#include "target/arm/psci.h"
>   
>   static struct arm_boot_info bpim2u_binfo;
>   
> diff --git a/hw/arm/boot.c b/hw/arm/boot.c
> index 79afb51b8a5..b81a850819b 100644
> --- a/hw/arm/boot.c
> +++ b/hw/arm/boot.c
> @@ -29,6 +29,7 @@
>   #include "qemu/config-file.h"
>   #include "qemu/option.h"
>   #include "qemu/units.h"
> +#include "target/arm/psci.h"
>   
>   /* Kernel boot protocol is specified in the kernel docs
>    * Documentation/arm/Booting and Documentation/arm64/booting.txt
> diff --git a/hw/arm/highbank.c b/hw/arm/highbank.c
> index 0caa08631ad..16fb2508d30 100644
> --- a/hw/arm/highbank.c
> +++ b/hw/arm/highbank.c
> @@ -36,6 +36,7 @@
>   #include "qemu/log.h"
>   #include "qom/object.h"
>   #include "target/arm/cpu-qom.h"
> +#include "target/arm/psci.h"
>   
>   #define SMP_BOOT_ADDR           0x100
>   #define SMP_BOOT_REG            0x40
> diff --git a/hw/arm/imx8mp-evk.c b/hw/arm/imx8mp-evk.c
> index 6e64ec4ea54..c8a99b2c49e 100644
> --- a/hw/arm/imx8mp-evk.c
> +++ b/hw/arm/imx8mp-evk.c
> @@ -15,6 +15,7 @@
>   #include "system/qtest.h"
>   #include "qemu/error-report.h"
>   #include "qapi/error.h"
> +#include "target/arm/psci.h"
>   
>   static void imx8mp_evk_init(MachineState *machine)
>   {
> diff --git a/hw/arm/mcimx6ul-evk.c b/hw/arm/mcimx6ul-evk.c
> index 86982cb0772..be5e50abf17 100644
> --- a/hw/arm/mcimx6ul-evk.c
> +++ b/hw/arm/mcimx6ul-evk.c
> @@ -18,6 +18,7 @@
>   #include "hw/qdev-properties.h"
>   #include "qemu/error-report.h"
>   #include "system/qtest.h"
> +#include "target/arm/psci.h"
>   
>   static void mcimx6ul_evk_init(MachineState *machine)
>   {
> diff --git a/hw/arm/mcimx7d-sabre.c b/hw/arm/mcimx7d-sabre.c
> index 33119610113..e0f25b92594 100644
> --- a/hw/arm/mcimx7d-sabre.c
> +++ b/hw/arm/mcimx7d-sabre.c
> @@ -20,6 +20,7 @@
>   #include "hw/qdev-properties.h"
>   #include "qemu/error-report.h"
>   #include "system/qtest.h"
> +#include "target/arm/psci.h"
>   
>   static void mcimx7d_sabre_init(MachineState *machine)
>   {
> diff --git a/hw/arm/orangepi.c b/hw/arm/orangepi.c
> index e0956880d11..99037a09a36 100644
> --- a/hw/arm/orangepi.c
> +++ b/hw/arm/orangepi.c
> @@ -26,6 +26,7 @@
>   #include "hw/qdev-properties.h"
>   #include "hw/arm/allwinner-h3.h"
>   #include "hw/arm/boot.h"
> +#include "target/arm/psci.h"
>   
>   static struct arm_boot_info orangepi_binfo;
>   
> diff --git a/hw/arm/sbsa-ref.c b/hw/arm/sbsa-ref.c
> index 90fbb56ba7a..1f592627c99 100644
> --- a/hw/arm/sbsa-ref.c
> +++ b/hw/arm/sbsa-ref.c
> @@ -53,6 +53,7 @@
>   #include "target/arm/cpu-qom.h"
>   #include "target/arm/gtimer.h"
>   #include "target/arm/multiprocessing.h"
> +#include "target/arm/psci.h"
>   
>   #define RAMLIMIT_GB 8192
>   #define RAMLIMIT_BYTES (RAMLIMIT_GB * GiB)
> diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c
> index 3ac8f8e1786..da61af1d359 100644
> --- a/hw/arm/virt-acpi-build.c
> +++ b/hw/arm/virt-acpi-build.c
> @@ -59,6 +59,7 @@
>   #include "hw/acpi/viot.h"
>   #include "hw/virtio/virtio-acpi.h"
>   #include "target/arm/multiprocessing.h"
> +#include "target/arm/psci.h"
>   
>   #define ARM_SPI_BASE 32
>   
> diff --git a/hw/arm/virt.c b/hw/arm/virt.c
> index a96452f17a4..fe2dec9500f 100644
> --- a/hw/arm/virt.c
> +++ b/hw/arm/virt.c
> @@ -79,6 +79,7 @@
>   #include "target/arm/internals.h"
>   #include "target/arm/multiprocessing.h"
>   #include "target/arm/gtimer.h"
> +#include "target/arm/psci.h"
>   #include "hw/mem/pc-dimm.h"
>   #include "hw/mem/nvdimm.h"
>   #include "hw/acpi/generic_event_device.h"
> diff --git a/hw/arm/xlnx-versal-virt.c b/hw/arm/xlnx-versal-virt.c
> index e19c4d9ef58..94fad8e60f2 100644
> --- a/hw/arm/xlnx-versal-virt.c
> +++ b/hw/arm/xlnx-versal-virt.c
> @@ -21,6 +21,7 @@
>   #include "hw/arm/xlnx-versal.h"
>   #include "hw/arm/boot.h"
>   #include "target/arm/multiprocessing.h"
> +#include "target/arm/psci.h"
>   #include "qom/object.h"
>   
>   #define TYPE_XLNX_VERSAL_VIRT_MACHINE MACHINE_TYPE_NAME("xlnx-versal-virt")
> diff --git a/hw/arm/xlnx-zcu102.c b/hw/arm/xlnx-zcu102.c
> index 88b1eafab4d..902ee65ca5f 100644
> --- a/hw/arm/xlnx-zcu102.c
> +++ b/hw/arm/xlnx-zcu102.c
> @@ -26,6 +26,7 @@
>   #include "qom/object.h"
>   #include "net/can_emu.h"
>   #include "audio/audio.h"
> +#include "target/arm/psci.h"
>   
>   struct XlnxZCU102 {
>       MachineState parent_obj;
> diff --git a/hw/vmapple/vmapple.c b/hw/vmapple/vmapple.c
> index 25652b16f0c..b73b6fb8115 100644
> --- a/hw/vmapple/vmapple.c
> +++ b/hw/vmapple/vmapple.c
> @@ -53,6 +53,7 @@
>   #include "system/system.h"
>   #include "target/arm/gtimer.h"
>   #include "target/arm/multiprocessing.h"
> +#include "target/arm/psci.h"
>   
>   struct VMAppleMachineState {
>       MachineState parent;
> diff --git a/target/arm/helper.c b/target/arm/helper.c
> index 7fb6e886306..48238ae0b20 100644
> --- a/target/arm/helper.c
> +++ b/target/arm/helper.c
> @@ -34,6 +34,7 @@
>   #endif
>   #include "cpregs.h"
>   #include "target/arm/gtimer.h"
> +#include "target/arm/psci.h"
>   
>   #define ARM_CPU_FREQ 1000000000 /* FIXME: 1 GHz, should be configurable */
>   
> diff --git a/target/arm/hvf/hvf.c b/target/arm/hvf/hvf.c
> index 34ca36fab55..f617e73feae 100644
> --- a/target/arm/hvf/hvf.c
> +++ b/target/arm/hvf/hvf.c
> @@ -33,6 +33,7 @@
>   #include "target/arm/internals.h"
>   #include "target/arm/multiprocessing.h"
>   #include "target/arm/gtimer.h"
> +#include "target/arm/psci.h"
>   #include "trace.h"
>   #include "migration/vmstate.h"
>   
> diff --git a/target/arm/tcg/op_helper.c b/target/arm/tcg/op_helper.c
> index 005f84082af..6e9db2e77e2 100644
> --- a/target/arm/tcg/op_helper.c
> +++ b/target/arm/tcg/op_helper.c
> @@ -26,6 +26,7 @@
>   #include "exec/exec-all.h"
>   #include "accel/tcg/cpu-ldst.h"
>   #include "target/arm/gtimer.h"
> +#include "target/arm/psci.h"
>   #include "cpregs.h"
>   
>   #define SIGNBIT (uint32_t)0x80000000
> diff --git a/target/arm/tcg/psci.c b/target/arm/tcg/psci.c
> index cabed43e8a8..0313cdd6ba2 100644
> --- a/target/arm/tcg/psci.c
> +++ b/target/arm/tcg/psci.c
> @@ -25,6 +25,7 @@
>   #include "internals.h"
>   #include "arm-powerctl.h"
>   #include "target/arm/multiprocessing.h"
> +#include "target/arm/psci.h"
>   
>   bool arm_is_psci_call(ARMCPU *cpu, int excp_type)
>   {

Re: [RFC PATCH-for-10.1 27/39] system/hvf: Expose hvf_enabled() to common code

[Pierrick Bouvier]

On 4/3/25 16:58, Philippe Mathieu-Daudé wrote:
> Currently hvf_enabled() is restricted to target-specific code.
> By defining CONFIG_HVF_IS_POSSIBLE we allow its use anywhere.
> 

Instead, we can simply make hvf_enabled present for common and target 
specific code, and link correct implementation, based on what we build.

I don't think *_IS_POSSIBLE was a good idea to start with.

> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
> ---
>   MAINTAINERS             |  1 +
>   include/system/hvf.h    | 14 +++++++++-----
>   accel/stubs/hvf-stub.c  | 12 ++++++++++++
>   accel/stubs/meson.build |  1 +
>   4 files changed, 23 insertions(+), 5 deletions(-)
>   create mode 100644 accel/stubs/hvf-stub.c
> 
> diff --git a/MAINTAINERS b/MAINTAINERS
> index c7083ab1d93..00ef33be0e2 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -525,6 +525,7 @@ R: Phil Dennis-Jordan <phil@philjordan.eu>
>   W: https://wiki.qemu.org/Features/HVF
>   S: Maintained
>   F: accel/hvf/
> +F: accel/stubs/hvf-stub.c
>   F: include/system/hvf.h
>   F: include/system/hvf_int.h
>   
> diff --git a/include/system/hvf.h b/include/system/hvf.h
> index d50049e1a1a..7b45a2e1988 100644
> --- a/include/system/hvf.h
> +++ b/include/system/hvf.h
> @@ -19,15 +19,19 @@
>   #include "qom/object.h"
>   
>   #ifdef COMPILING_PER_TARGET
> +# ifdef CONFIG_HVF
> +#  define CONFIG_HVF_IS_POSSIBLE
> +# endif /* !CONFIG_HVF */
> +#else
> +# define CONFIG_HVF_IS_POSSIBLE
> +#endif /* COMPILING_PER_TARGET */
>   
> -#ifdef CONFIG_HVF
> +#ifdef CONFIG_HVF_IS_POSSIBLE
>   extern bool hvf_allowed;
>   #define hvf_enabled() (hvf_allowed)
> -#else /* !CONFIG_HVF */
> +#else /* !CONFIG_HVF_IS_POSSIBLE */
>   #define hvf_enabled() 0
> -#endif /* !CONFIG_HVF */
> -
> -#endif /* COMPILING_PER_TARGET */
> +#endif /* !CONFIG_HVF_IS_POSSIBLE */
>   
>   #define TYPE_HVF_ACCEL ACCEL_CLASS_NAME("hvf")
>   
> diff --git a/accel/stubs/hvf-stub.c b/accel/stubs/hvf-stub.c
> new file mode 100644
> index 00000000000..42eadc5ca92
> --- /dev/null
> +++ b/accel/stubs/hvf-stub.c
> @@ -0,0 +1,12 @@
> +/*
> + * HVF stubs for QEMU
> + *
> + *  Copyright (c) Linaro
> + *
> + * SPDX-License-Identifier: GPL-2.0-or-later
> + */
> +
> +#include "qemu/osdep.h"
> +#include "system/hvf.h"
> +
> +bool hvf_allowed;
> diff --git a/accel/stubs/meson.build b/accel/stubs/meson.build
> index 91a2d219258..8ca1a4529e2 100644
> --- a/accel/stubs/meson.build
> +++ b/accel/stubs/meson.build
> @@ -2,5 +2,6 @@ system_stubs_ss = ss.source_set()
>   system_stubs_ss.add(when: 'CONFIG_XEN', if_false: files('xen-stub.c'))
>   system_stubs_ss.add(when: 'CONFIG_KVM', if_false: files('kvm-stub.c'))
>   system_stubs_ss.add(when: 'CONFIG_TCG', if_false: files('tcg-stub.c'))
> +system_stubs_ss.add(when: 'CONFIG_HVF', if_false: files('hvf-stub.c'))
>   
>   specific_ss.add_all(when: ['CONFIG_SYSTEM_ONLY'], if_true: system_stubs_ss)

Re: [RFC PATCH-for-10.1 28/39] exec: Do not poison hardware accelerators

[Pierrick Bouvier]

On 4/3/25 16:58, Philippe Mathieu-Daudé wrote:
> Hardware accelerators depends on the host, not the guest.
> 

While this is true, no we can't unpoison those define.
They are applied per target, and not in config-host. So unpoisoining 
them opens the possibility to miss something.

I would stick to clean up those ifdef instead, by exposing interface to 
all code, and link appropriate stubs depending on the variant built.

> Suggested-by: Richard Henderson <richard.henderson@linaro.org>
> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
> ---
>   include/exec/poison.h         | 4 ----
>   scripts/make-config-p	oison.sh | 4 ++++
>   2 files changed, 4 insertions(+), 4 deletions(-)
> 
> diff --git a/include/exec/poison.h b/include/exec/poison.h
> index 00aedc41d82..0574d683f6a 100644
> --- a/include/exec/poison.h
> +++ b/include/exec/poison.h
> @@ -62,11 +62,7 @@
>   #pragma GCC poison CONFIG_SPARC_DIS
>   #pragma GCC poison CONFIG_XTENSA_DIS
>   
> -#pragma GCC poison CONFIG_HVF
>   #pragma GCC poison CONFIG_LINUX_USER
> -#pragma GCC poison CONFIG_KVM
> -#pragma GCC poison CONFIG_WHPX
> -#pragma GCC poison CONFIG_XEN
>   
>   #ifndef COMPILING_SYSTEM_VS_USER
>   #pragma GCC poison CONFIG_USER_ONLY
> diff --git a/scripts/make-config-poison.sh b/scripts/make-config-poison.sh
> index 2b36907e239..09d2384745f 100755
> --- a/scripts/make-config-poison.sh
> +++ b/scripts/make-config-poison.sh
> @@ -8,6 +8,10 @@ fi
>   # but filter out several which are handled manually.
>   exec sed -n \
>     -e' /CONFIG_TCG/d' \
> +  -e' /CONFIG_HVF/d' \
> +  -e' /CONFIG_KVM/d' \
> +  -e' /CONFIG_WHPX/d' \
> +  -e' /CONFIG_XEN/d' \
>     -e '/CONFIG_USER_ONLY/d' \
>     -e '/CONFIG_SOFTMMU/d' \
>     -e '/^#define / {' \

Re: [RFC PATCH-for-10.1 35/39] hw/arm/virt: Replace TARGET_AARCH64 -> target_long_bits()

[Pierrick Bouvier]

On 4/3/25 16:58, Philippe Mathieu-Daudé wrote:
> Replace the target-specific TARGET_AARCH64 definition
> by a call to the generic target_long_bits() helper.
> 
> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
> ---
>   hw/arm/virt.c | 32 ++++++++++++++++----------------
>   1 file changed, 16 insertions(+), 16 deletions(-)
> 
> diff --git a/hw/arm/virt.c b/hw/arm/virt.c
> index e241e71e1c3..a020f1bd581 100644
> --- a/hw/arm/virt.c
> +++ b/hw/arm/virt.c
> @@ -3133,25 +3133,25 @@ static void virt_machine_class_init(ObjectClass *oc, void *data)
>   #ifdef CONFIG_TCG
>       machine_class_add_valid_cpu_type(mc, ARM_CPU_TYPE_NAME("cortex-a7"));
>       machine_class_add_valid_cpu_type(mc, ARM_CPU_TYPE_NAME("cortex-a15"));
> -#ifdef TARGET_AARCH64
> -    machine_class_add_valid_cpu_type(mc, ARM_CPU_TYPE_NAME("cortex-a35"));
> -    machine_class_add_valid_cpu_type(mc, ARM_CPU_TYPE_NAME("cortex-a55"));
> -    machine_class_add_valid_cpu_type(mc, ARM_CPU_TYPE_NAME("cortex-a72"));
> -    machine_class_add_valid_cpu_type(mc, ARM_CPU_TYPE_NAME("cortex-a76"));
> -    machine_class_add_valid_cpu_type(mc, ARM_CPU_TYPE_NAME("cortex-a710"));
> -    machine_class_add_valid_cpu_type(mc, ARM_CPU_TYPE_NAME("a64fx"));
> -    machine_class_add_valid_cpu_type(mc, ARM_CPU_TYPE_NAME("neoverse-n1"));
> -    machine_class_add_valid_cpu_type(mc, ARM_CPU_TYPE_NAME("neoverse-v1"));
> -    machine_class_add_valid_cpu_type(mc, ARM_CPU_TYPE_NAME("neoverse-n2"));
> -#endif /* TARGET_AARCH64 */
> +    if (target_long_bits() == 64) {

I would prefer if we introduce a true target_aarch64() function, and 
probably the same for other architectures when it will be needed.

If we start using target_long_bits(), we might enable something in 
common code that we are not supposed to do. And it will be much harder 
to find it later when we debug heterogenenous emulation.

> +        machine_class_add_valid_cpu_type(mc, ARM_CPU_TYPE_NAME("cortex-a35"));
> +        machine_class_add_valid_cpu_type(mc, ARM_CPU_TYPE_NAME("cortex-a55"));
> +        machine_class_add_valid_cpu_type(mc, ARM_CPU_TYPE_NAME("cortex-a72"));
> +        machine_class_add_valid_cpu_type(mc, ARM_CPU_TYPE_NAME("cortex-a76"));
> +        machine_class_add_valid_cpu_type(mc, ARM_CPU_TYPE_NAME("cortex-a710"));
> +        machine_class_add_valid_cpu_type(mc, ARM_CPU_TYPE_NAME("a64fx"));
> +        machine_class_add_valid_cpu_type(mc, ARM_CPU_TYPE_NAME("neoverse-n1"));
> +        machine_class_add_valid_cpu_type(mc, ARM_CPU_TYPE_NAME("neoverse-v1"));
> +        machine_class_add_valid_cpu_type(mc, ARM_CPU_TYPE_NAME("neoverse-n2"));
> +    }
>   #endif /* CONFIG_TCG */
> -#ifdef TARGET_AARCH64
> -    machine_class_add_valid_cpu_type(mc, ARM_CPU_TYPE_NAME("cortex-a53"));
> -    machine_class_add_valid_cpu_type(mc, ARM_CPU_TYPE_NAME("cortex-a57"));
> +    if (target_long_bits() == 64) {
> +        machine_class_add_valid_cpu_type(mc, ARM_CPU_TYPE_NAME("cortex-a53"));
> +        machine_class_add_valid_cpu_type(mc, ARM_CPU_TYPE_NAME("cortex-a57"));
>   #if defined(CONFIG_KVM) || defined(CONFIG_HVF)
> -    machine_class_add_valid_cpu_type(mc, ARM_CPU_TYPE_NAME("host"));
> +        machine_class_add_valid_cpu_type(mc, ARM_CPU_TYPE_NAME("host"));
>   #endif /* CONFIG_KVM || CONFIG_HVF */
> -#endif /* TARGET_AARCH64 */
> +    }
>       machine_class_add_valid_cpu_type(mc, ARM_CPU_TYPE_NAME("max"));
>   
>       mc->init = machvirt_init;

Re: [RFC PATCH-for-10.1 00/39] single-binary: Make hw/arm/ common

[Pierrick Bouvier]

On 4/4/25 11:04, Philippe Mathieu-Daudé wrote:
> On 4/4/25 19:12, Pierrick Bouvier wrote:
>> On 4/3/25 16:57, Philippe Mathieu-Daudé wrote:
>>> Hi,
>>>
>>> At this point this series is mostly a draft for Pierrick.
>>>
>>> After introducing the generic TargetInfo API [*], we implement
>>> the ARM variants, then use the API to remove target-specific code,
>>> allowing to eventually remove the target-specific arm_ss[] source
>>> set in meson.build, having all objects in arm_common_ss[].
>>> Various header cleanups are necessary before getting there.
>>>
>>
>> As there are some changes asked on this API, I think it's better if we
>> review this series later.
> 
> I think I misunderstood your comments in my series [*] reworking
> arm_cpu_has_feature(), I thought you wanted to see why it was for
> (completing your 'Make hw/arm/ common' effort).
> 

The assumption made in the current series is that we should remove 
dependency on cpu.h in target common code.
However, this assumption is false, and we can simply include cpu.h and 
do the same as before. For target/arm/cpu.h, it's possible because it 
was cleaned up previously to not have any target specific definition 
(removing any poisoned TARGET_ or CONFIG_ by exposing matching fields 
inconditionnally).

>> I'll still comment a few commits here that point some problems in the
>> approach.
> 
> Thanks!
> 
> [*]
> https://lore.kernel.org/qemu-devel/cecbab0f-56f2-434a-8508-8a4df2992259@linaro.org/
> 

Re: [RFC PATCH-for-10.1 00/39] single-binary: Make hw/arm/ common

[Pierrick Bouvier]

On 4/4/25 10:12, Pierrick Bouvier wrote:
> On 4/3/25 16:57, Philippe Mathieu-Daudé wrote:
>> Hi,
>>
>> At this point this series is mostly a draft for Pierrick.
>>
>> After introducing the generic TargetInfo API [*], we implement
>> the ARM variants, then use the API to remove target-specific code,
>> allowing to eventually remove the target-specific arm_ss[] source
>> set in meson.build, having all objects in arm_common_ss[].
>> Various header cleanups are necessary before getting there.
>>
> 
> As there are some changes asked on this API, I think it's better if we
> review this series later.
> 
> I'll still comment a few commits here that point some problems in the
> approach.
> 

To summarize the problems reported:
- It's not needed to remove cpu.h inclusion, as this header has been 
previously made target (variant) agnostic.
- No, we can't unpoison CONFIG_{accel}, we need to cleanup associated 
code instead.
- We need a target_aarch64() common function

>> Regards,
>>
>> Phil.
>>
>> Available here, based on tcg-next:
>> https://gitlab.com/philmd/qemu/-/tags/single-binary-hw-arm-rfc-v1
>>
>> [*] https://lore.kernel.org/qemu-devel/20250403234914.9154-1-philmd@linaro.org/
>>
>> Philippe Mathieu-Daudé (39):
>>     target/arm: Implement per-binary TargetInfo structures
>>     target/arm: Register TYPE_BINARY_QEMU_SYSTEM_ARM/AARCH64 interfaces
>>     target/arm: Filter CPU types for binary
>>     hw/arm: Filter machine types for binary
>>     hw/arm/aspeed: Filter machine types for binary
>>     hw/arm/aspeed: Build objects once
>>     hw/arm/raspi: Filter machine types for binary
>>     hw/arm/raspi: Build objects once
>>     target/arm/cpregs: Include missing 'target/arm/cpu.h' header
>>     hw/arm/boot: Include missing 'system/memory.h' header
>>     hw/arm: Use full "target/arm/cpu.h" path to include target's "cpu.h"
>>     target/arm/cpu-features: Include missing 'cpu.h' header
>>     target/arm/qmp: Include missing 'cpu.h' header
>>     target/arm/kvm: Include missing 'cpu-qom.h' header
>>     target/arm/hvf: Include missing 'cpu-qom.h' header
>>     hw/arm: Remove unnecessary 'cpu.h' header
>>     target/arm: Restrict inclusion of 'multiprocessing.h'
>>     target/arm: Move some definitions from 'cpu.h' to 'multiprocessing.h'
>>     hw/arm: Include missing 'target/arm/gtimer.h' header
>>     target/arm: Extract PSCI definitions to 'psci.h'
>>     target/arm: Extract feature definitions to 'cpu_has_feature.h' header
>>     target/arm: Add arm_cpu_has_feature() helper
>>     hw/arm/realview: Replace arm_feature() -> arm_cpu_has_feature()
>>     hw/arm/virt-acpi: Replace arm_feature() -> arm_cpu_has_feature()
>>     hw/arm: Build virt-acpi-build.c once
>>     system/hvf: Avoid including 'cpu.h'
>>     system/hvf: Expose hvf_enabled() to common code
>>     exec: Do not poison hardware accelerators
>>     hw/arm: Build sbsa-ref.c once
>>     target/arm: Replace target_ulong -> hwaddr in ARMMMUFaultInfo
>>     target/arm: Replace target_ulong -> uint64_t for HWBreakpoint
>>     target/arm: Replace target_ulong -> vaddr for CPUWatchpoint
>>     hw/core/machine: Allow dynamic registration of valid CPU types
>>     hw/arm/virt: Register valid CPU types dynamically
>>     hw/arm/virt: Replace TARGET_AARCH64 -> target_long_bits()
>>     target/arm: Expose Aarch64 helpers indistinctly
>>     hw/arm: Build virt.c once
>>     hw/arm: Move xen files to arm_common_ss[]
>>     hw/arm/meson: Remove arm_ss[] source set
>>
>>    MAINTAINERS                              |  1 +
>>    meson.build                              |  1 +
>>    include/exec/poison.h                    |  4 --
>>    include/hw/arm/boot.h                    |  3 +-
>>    include/hw/arm/digic.h                   |  2 +-
>>    include/hw/arm/fsl-imx6.h                |  2 +-
>>    include/hw/arm/fsl-imx6ul.h              |  2 +-
>>    include/hw/arm/fsl-imx7.h                |  2 +-
>>    include/hw/arm/fsl-imx8mp.h              |  2 +-
>>    include/hw/boards.h                      |  8 +++
>>    include/qemu/target_info-qom.h           | 20 ++++++
>>    include/system/hvf.h                     | 17 ++++--
>>    include/system/hvf_int.h                 |  2 +
>>    target/arm/cpregs.h                      |  1 +
>>    target/arm/cpu-features.h                |  1 +
>>    target/arm/cpu.h                         | 78 +-----------------------
>>    target/arm/cpu_has_feature.h             | 67 ++++++++++++++++++++
>>    target/arm/hvf_arm.h                     |  2 +-
>>    target/arm/internals.h                   | 22 +++----
>>    target/arm/kvm_arm.h                     |  1 +
>>    target/arm/multiprocessing.h             | 18 ++++++
>>    target/arm/psci.h                        | 18 ++++++
>>    accel/stubs/hvf-stub.c                   | 12 ++++
>>    hw/arm/aspeed.c                          | 30 ++++++---
>>    hw/arm/aspeed_ast2600.c                  |  1 +
>>    hw/arm/aspeed_ast27x0.c                  |  2 +
>>    hw/arm/b-l475e-iot01a.c                  |  1 +
>>    hw/arm/bananapi_m2u.c                    |  1 +
>>    hw/arm/bcm2836.c                         |  4 --
>>    hw/arm/bcm2838.c                         |  1 +
>>    hw/arm/boot.c                            |  2 +
>>    hw/arm/collie.c                          |  1 +
>>    hw/arm/exynos4210.c                      |  3 +-
>>    hw/arm/exynos4_boards.c                  |  1 +
>>    hw/arm/fby35.c                           |  1 +
>>    hw/arm/fsl-imx8mp.c                      |  1 +
>>    hw/arm/highbank.c                        |  4 +-
>>    hw/arm/imx8mp-evk.c                      |  1 +
>>    hw/arm/mcimx6ul-evk.c                    |  1 +
>>    hw/arm/mcimx7d-sabre.c                   |  1 +
>>    hw/arm/microbit.c                        |  1 +
>>    hw/arm/mps2-tz.c                         |  4 ++
>>    hw/arm/mps2.c                            |  4 ++
>>    hw/arm/mps3r.c                           |  3 +-
>>    hw/arm/musca.c                           |  2 +
>>    hw/arm/npcm8xx.c                         |  2 +
>>    hw/arm/omap_sx1.c                        |  2 +
>>    hw/arm/orangepi.c                        |  1 +
>>    hw/arm/raspi.c                           |  9 +--
>>    hw/arm/raspi4b.c                         |  1 +
>>    hw/arm/realview.c                        | 14 +++--
>>    hw/arm/sbsa-ref.c                        |  3 +
>>    hw/arm/smmuv3.c                          |  1 -
>>    hw/arm/stellaris.c                       |  3 +
>>    hw/arm/versatilepb.c                     |  1 +
>>    hw/arm/vexpress.c                        |  2 +
>>    hw/arm/virt-acpi-build.c                 |  4 +-
>>    hw/arm/virt.c                            | 44 +++++++------
>>    hw/arm/xilinx_zynq.c                     |  1 +
>>    hw/arm/xlnx-versal-virt.c                |  2 +
>>    hw/arm/xlnx-zcu102.c                     |  2 +
>>    hw/core/machine.c                        | 28 +++++++++
>>    hw/vmapple/vmapple.c                     |  3 +
>>    target/arm/arm-qmp-cmds.c                |  1 +
>>    target/arm/cpu.c                         | 10 +++
>>    target/arm/cpu64.c                       |  2 +
>>    target/arm/helper.c                      |  1 +
>>    target/arm/hvf/hvf.c                     |  1 +
>>    target/arm/hyp_gdbstub.c                 | 14 ++---
>>    target/arm/kvm.c                         |  1 +
>>    target/arm/target_info-aarch64-softmmu.c | 24 ++++++++
>>    target/arm/target_info-arm-softmmu.c     | 24 ++++++++
>>    target/arm/tcg/op_helper.c               |  2 +
>>    target/arm/tcg/psci.c                    |  1 +
>>    target_info-qom.c                        |  8 +++
>>    accel/stubs/meson.build                  |  1 +
>>    hw/arm/meson.build                       | 22 ++++---
>>    scripts/make-config-poison.sh            |  4 ++
>>    target/arm/meson.build                   |  5 ++
>>    79 files changed, 429 insertions(+), 171 deletions(-)
>>    create mode 100644 target/arm/cpu_has_feature.h
>>    create mode 100644 target/arm/psci.h
>>    create mode 100644 accel/stubs/hvf-stub.c
>>    create mode 100644 target/arm/target_info-aarch64-softmmu.c
>>    create mode 100644 target/arm/target_info-arm-softmmu.c
>>
> 

Re: [RFC PATCH-for-10.1 11/39] hw/arm: Use full "target/arm/cpu.h" path to include target's "cpu.h"

[Philippe Mathieu-Daudé]

On 4/4/25 20:20, Pierrick Bouvier wrote:
> On 4/3/25 16:57, Philippe Mathieu-Daudé wrote:
>> We would like to get rid of '-I target/$ARCH/' in the CPPFLAGS.
> 
> While this change is correct, this is not strictly needed.
> With the current approach, using a set of common files per architecture, 
> we can rely on this include to be present, and it does not block from 
> having common files.

Indeed, I rebased this commit from my heterogeneous branch.

I'll keeping carrying / rebasing it for various months, trying to
remember to not keeping posting it.

Or alternatively I'll post it in a separate "cleanup series", not
mentioning single-binary or heterogeneous emulation.

>> Use the full path to "cpu.h": "target/arm/cpu.h".
>>
>> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
>> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
>> ---
>>   include/hw/arm/digic.h      | 2 +-
>>   include/hw/arm/fsl-imx6.h   | 2 +-
>>   include/hw/arm/fsl-imx6ul.h | 2 +-
>>   include/hw/arm/fsl-imx7.h   | 2 +-
>>   include/hw/arm/fsl-imx8mp.h | 2 +-
>>   5 files changed, 5 insertions(+), 5 deletions(-)

Re: [RFC PATCH-for-10.1 20/39] target/arm: Extract PSCI definitions to 'psci.h'

[Philippe Mathieu-Daudé]

On 4/4/25 20:21, Pierrick Bouvier wrote:
> On 4/3/25 16:58, Philippe Mathieu-Daudé wrote:
>> Extract PSCI definitions (which are not target specific)
>> to the new "target/arm/psci.h", so code from hw/arm/ can
>> use them without having to include the target specific
>> "cpu.h" header.
>>
> 
> Including cpu.h is not a problem to have common code (per architecture), 
> so there is no need to do any change here.

Again, this is an old patch from my heterogeneous PoC branch.
I'll remove from this series to not distract you.

> 
>> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
>> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
>> ---
>>   include/hw/arm/boot.h      |  3 ++-
>>   target/arm/cpu.h           |  6 ------
>>   target/arm/psci.h          | 18 ++++++++++++++++++
>>   hw/arm/bananapi_m2u.c      |  1 +
>>   hw/arm/boot.c              |  1 +
>>   hw/arm/highbank.c          |  1 +
>>   hw/arm/imx8mp-evk.c        |  1 +
>>   hw/arm/mcimx6ul-evk.c      |  1 +
>>   hw/arm/mcimx7d-sabre.c     |  1 +
>>   hw/arm/orangepi.c          |  1 +
>>   hw/arm/sbsa-ref.c          |  1 +
>>   hw/arm/virt-acpi-build.c   |  1 +
>>   hw/arm/virt.c              |  1 +
>>   hw/arm/xlnx-versal-virt.c  |  1 +
>>   hw/arm/xlnx-zcu102.c       |  1 +
>>   hw/vmapple/vmapple.c       |  1 +
>>   target/arm/helper.c        |  1 +
>>   target/arm/hvf/hvf.c       |  1 +
>>   target/arm/tcg/op_helper.c |  1 +
>>   target/arm/tcg/psci.c      |  1 +
>>   20 files changed, 37 insertions(+), 7 deletions(-)
>>   create mode 100644 target/arm/psci.h

Re: [RFC PATCH-for-10.1 27/39] system/hvf: Expose hvf_enabled() to common code

[Philippe Mathieu-Daudé]

+Paolo

On 4/4/25 20:23, Pierrick Bouvier wrote:
> On 4/3/25 16:58, Philippe Mathieu-Daudé wrote:
>> Currently hvf_enabled() is restricted to target-specific code.
>> By defining CONFIG_HVF_IS_POSSIBLE we allow its use anywhere.
>>
> 
> Instead, we can simply make hvf_enabled present for common and target 
> specific code, and link correct implementation, based on what we build.
> 
> I don't think *_IS_POSSIBLE was a good idea to start with.

IIUC the point of *_IS_POSSIBLE is to elide code, which we
aren't interested anymore for host-related configs, so we
can also remove CONFIG_KVM_IS_POSSIBLE and CONFIG_XEN_IS_POSSIBLE.
Is that correct?

> 
>> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
>> ---
>>   MAINTAINERS             |  1 +
>>   include/system/hvf.h    | 14 +++++++++-----
>>   accel/stubs/hvf-stub.c  | 12 ++++++++++++
>>   accel/stubs/meson.build |  1 +
>>   4 files changed, 23 insertions(+), 5 deletions(-)
>>   create mode 100644 accel/stubs/hvf-stub.c
>>
>> diff --git a/MAINTAINERS b/MAINTAINERS
>> index c7083ab1d93..00ef33be0e2 100644
>> --- a/MAINTAINERS
>> +++ b/MAINTAINERS
>> @@ -525,6 +525,7 @@ R: Phil Dennis-Jordan <phil@philjordan.eu>
>>   W: https://wiki.qemu.org/Features/HVF
>>   S: Maintained
>>   F: accel/hvf/
>> +F: accel/stubs/hvf-stub.c
>>   F: include/system/hvf.h
>>   F: include/system/hvf_int.h
>> diff --git a/include/system/hvf.h b/include/system/hvf.h
>> index d50049e1a1a..7b45a2e1988 100644
>> --- a/include/system/hvf.h
>> +++ b/include/system/hvf.h
>> @@ -19,15 +19,19 @@
>>   #include "qom/object.h"
>>   #ifdef COMPILING_PER_TARGET
>> +# ifdef CONFIG_HVF
>> +#  define CONFIG_HVF_IS_POSSIBLE
>> +# endif /* !CONFIG_HVF */
>> +#else
>> +# define CONFIG_HVF_IS_POSSIBLE
>> +#endif /* COMPILING_PER_TARGET */
>> -#ifdef CONFIG_HVF
>> +#ifdef CONFIG_HVF_IS_POSSIBLE
>>   extern bool hvf_allowed;
>>   #define hvf_enabled() (hvf_allowed)
>> -#else /* !CONFIG_HVF */
>> +#else /* !CONFIG_HVF_IS_POSSIBLE */
>>   #define hvf_enabled() 0
>> -#endif /* !CONFIG_HVF */
>> -
>> -#endif /* COMPILING_PER_TARGET */
>> +#endif /* !CONFIG_HVF_IS_POSSIBLE */
>>   #define TYPE_HVF_ACCEL ACCEL_CLASS_NAME("hvf")
>> diff --git a/accel/stubs/hvf-stub.c b/accel/stubs/hvf-stub.c
>> new file mode 100644
>> index 00000000000..42eadc5ca92
>> --- /dev/null
>> +++ b/accel/stubs/hvf-stub.c
>> @@ -0,0 +1,12 @@
>> +/*
>> + * HVF stubs for QEMU
>> + *
>> + *  Copyright (c) Linaro
>> + *
>> + * SPDX-License-Identifier: GPL-2.0-or-later
>> + */
>> +
>> +#include "qemu/osdep.h"
>> +#include "system/hvf.h"
>> +
>> +bool hvf_allowed;
>> diff --git a/accel/stubs/meson.build b/accel/stubs/meson.build
>> index 91a2d219258..8ca1a4529e2 100644
>> --- a/accel/stubs/meson.build
>> +++ b/accel/stubs/meson.build
>> @@ -2,5 +2,6 @@ system_stubs_ss = ss.source_set()
>>   system_stubs_ss.add(when: 'CONFIG_XEN', if_false: files('xen-stub.c'))
>>   system_stubs_ss.add(when: 'CONFIG_KVM', if_false: files('kvm-stub.c'))
>>   system_stubs_ss.add(when: 'CONFIG_TCG', if_false: files('tcg-stub.c'))
>> +system_stubs_ss.add(when: 'CONFIG_HVF', if_false: files('hvf-stub.c'))
>>   specific_ss.add_all(when: ['CONFIG_SYSTEM_ONLY'], if_true: 
>> system_stubs_ss)
> 

Re: [RFC PATCH-for-10.1 28/39] exec: Do not poison hardware accelerators

[Philippe Mathieu-Daudé]

+Paolo

On 4/4/25 20:25, Pierrick Bouvier wrote:
> On 4/3/25 16:58, Philippe Mathieu-Daudé wrote:
>> Hardware accelerators depends on the host, not the guest.
>>
> 
> While this is true, no we can't unpoison those define.
> They are applied per target, and not in config-host. So unpoisoining 
> them opens the possibility to miss something.
> 
> I would stick to clean up those ifdef instead, by exposing interface to 
> all code, and link appropriate stubs depending on the variant built.

OK, so IIUC this is the same reasoning than previous patch comment,
always declare kvm_enabled() so code elision isn't possible anymore,
then remove all CONFIG_KVM #ifdef'ry?

> 
>> Suggested-by: Richard Henderson <richard.henderson@linaro.org>
>> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
>> ---
>>   include/exec/poison.h         | 4 ----
>>   scripts/make-config-p    oison.sh | 4 ++++
>>   2 files changed, 4 insertions(+), 4 deletions(-)
>>
>> diff --git a/include/exec/poison.h b/include/exec/poison.h
>> index 00aedc41d82..0574d683f6a 100644
>> --- a/include/exec/poison.h
>> +++ b/include/exec/poison.h
>> @@ -62,11 +62,7 @@
>>   #pragma GCC poison CONFIG_SPARC_DIS
>>   #pragma GCC poison CONFIG_XTENSA_DIS
>> -#pragma GCC poison CONFIG_HVF
>>   #pragma GCC poison CONFIG_LINUX_USER
>> -#pragma GCC poison CONFIG_KVM
>> -#pragma GCC poison CONFIG_WHPX
>> -#pragma GCC poison CONFIG_XEN
>>   #ifndef COMPILING_SYSTEM_VS_USER
>>   #pragma GCC poison CONFIG_USER_ONLY
>> diff --git a/scripts/make-config-poison.sh b/scripts/make-config- 
>> poison.sh
>> index 2b36907e239..09d2384745f 100755
>> --- a/scripts/make-config-poison.sh
>> +++ b/scripts/make-config-poison.sh
>> @@ -8,6 +8,10 @@ fi
>>   # but filter out several which are handled manually.
>>   exec sed -n \
>>     -e' /CONFIG_TCG/d' \
>> +  -e' /CONFIG_HVF/d' \
>> +  -e' /CONFIG_KVM/d' \
>> +  -e' /CONFIG_WHPX/d' \
>> +  -e' /CONFIG_XEN/d' \
>>     -e '/CONFIG_USER_ONLY/d' \
>>     -e '/CONFIG_SOFTMMU/d' \
>>     -e '/^#define / {' \
> 

Re: [RFC PATCH-for-10.1 35/39] hw/arm/virt: Replace TARGET_AARCH64 -> target_long_bits()

[Philippe Mathieu-Daudé]

On 4/4/25 20:28, Pierrick Bouvier wrote:
> On 4/3/25 16:58, Philippe Mathieu-Daudé wrote:
>> Replace the target-specific TARGET_AARCH64 definition
>> by a call to the generic target_long_bits() helper.
>>
>> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
>> ---
>>   hw/arm/virt.c | 32 ++++++++++++++++----------------
>>   1 file changed, 16 insertions(+), 16 deletions(-)
>>
>> diff --git a/hw/arm/virt.c b/hw/arm/virt.c
>> index e241e71e1c3..a020f1bd581 100644
>> --- a/hw/arm/virt.c
>> +++ b/hw/arm/virt.c
>> @@ -3133,25 +3133,25 @@ static void 
>> virt_machine_class_init(ObjectClass *oc, void *data)
>>   #ifdef CONFIG_TCG
>>       machine_class_add_valid_cpu_type(mc, ARM_CPU_TYPE_NAME("cortex- 
>> a7"));
>>       machine_class_add_valid_cpu_type(mc, ARM_CPU_TYPE_NAME("cortex- 
>> a15"));
>> -#ifdef TARGET_AARCH64
>> -    machine_class_add_valid_cpu_type(mc, ARM_CPU_TYPE_NAME("cortex- 
>> a35"));
>> -    machine_class_add_valid_cpu_type(mc, ARM_CPU_TYPE_NAME("cortex- 
>> a55"));
>> -    machine_class_add_valid_cpu_type(mc, ARM_CPU_TYPE_NAME("cortex- 
>> a72"));
>> -    machine_class_add_valid_cpu_type(mc, ARM_CPU_TYPE_NAME("cortex- 
>> a76"));
>> -    machine_class_add_valid_cpu_type(mc, ARM_CPU_TYPE_NAME("cortex- 
>> a710"));
>> -    machine_class_add_valid_cpu_type(mc, ARM_CPU_TYPE_NAME("a64fx"));
>> -    machine_class_add_valid_cpu_type(mc, ARM_CPU_TYPE_NAME("neoverse- 
>> n1"));
>> -    machine_class_add_valid_cpu_type(mc, ARM_CPU_TYPE_NAME("neoverse- 
>> v1"));
>> -    machine_class_add_valid_cpu_type(mc, ARM_CPU_TYPE_NAME("neoverse- 
>> n2"));
>> -#endif /* TARGET_AARCH64 */
>> +    if (target_long_bits() == 64) {
> 
> I would prefer if we introduce a true target_aarch64() function, and 
> probably the same for other architectures when it will be needed.
> 
> If we start using target_long_bits(), we might enable something in 
> common code that we are not supposed to do. And it will be much harder 
> to find it later when we debug heterogenenous emulation.

I get your point. Maybe we can register valid aa64 CPUs regardless,
and filter for registered QOM CPUs? OTOH your suggestion of
TARGET_AARCH64 -> target_aarch64() could be easier to review.
I''ll give it a try.

> 
>> +        machine_class_add_valid_cpu_type(mc, 
>> ARM_CPU_TYPE_NAME("cortex-a35"));
>> +        machine_class_add_valid_cpu_type(mc, 
>> ARM_CPU_TYPE_NAME("cortex-a55"));
>> +        machine_class_add_valid_cpu_type(mc, 
>> ARM_CPU_TYPE_NAME("cortex-a72"));
>> +        machine_class_add_valid_cpu_type(mc, 
>> ARM_CPU_TYPE_NAME("cortex-a76"));
>> +        machine_class_add_valid_cpu_type(mc, 
>> ARM_CPU_TYPE_NAME("cortex-a710"));
>> +        machine_class_add_valid_cpu_type(mc, 
>> ARM_CPU_TYPE_NAME("a64fx"));
>> +        machine_class_add_valid_cpu_type(mc, 
>> ARM_CPU_TYPE_NAME("neoverse-n1"));
>> +        machine_class_add_valid_cpu_type(mc, 
>> ARM_CPU_TYPE_NAME("neoverse-v1"));
>> +        machine_class_add_valid_cpu_type(mc, 
>> ARM_CPU_TYPE_NAME("neoverse-n2"));
>> +    }
>>   #endif /* CONFIG_TCG */
>> -#ifdef TARGET_AARCH64
>> -    machine_class_add_valid_cpu_type(mc, ARM_CPU_TYPE_NAME("cortex- 
>> a53"));
>> -    machine_class_add_valid_cpu_type(mc, ARM_CPU_TYPE_NAME("cortex- 
>> a57"));
>> +    if (target_long_bits() == 64) {
>> +        machine_class_add_valid_cpu_type(mc, 
>> ARM_CPU_TYPE_NAME("cortex-a53"));
>> +        machine_class_add_valid_cpu_type(mc, 
>> ARM_CPU_TYPE_NAME("cortex-a57"));
>>   #if defined(CONFIG_KVM) || defined(CONFIG_HVF)
>> -    machine_class_add_valid_cpu_type(mc, ARM_CPU_TYPE_NAME("host"));
>> +        machine_class_add_valid_cpu_type(mc, ARM_CPU_TYPE_NAME("host"));
>>   #endif /* CONFIG_KVM || CONFIG_HVF */
>> -#endif /* TARGET_AARCH64 */
>> +    }
>>       machine_class_add_valid_cpu_type(mc, ARM_CPU_TYPE_NAME("max"));
>>       mc->init = machvirt_init;
> 

Re: [RFC PATCH-for-10.1 11/39] hw/arm: Use full "target/arm/cpu.h" path to include target's "cpu.h"

[Pierrick Bouvier]

On 4/4/25 14:53, Philippe Mathieu-Daudé wrote:
> On 4/4/25 20:20, Pierrick Bouvier wrote:
>> On 4/3/25 16:57, Philippe Mathieu-Daudé wrote:
>>> We would like to get rid of '-I target/$ARCH/' in the CPPFLAGS.
>>
>> While this change is correct, this is not strictly needed.
>> With the current approach, using a set of common files per architecture,
>> we can rely on this include to be present, and it does not block from
>> having common files.
> 
> Indeed, I rebased this commit from my heterogeneous branch.
> 
> I'll keeping carrying / rebasing it for various months, trying to
> remember to not keeping posting it.
> 
> Or alternatively I'll post it in a separate "cleanup series", not
> mentioning single-binary or heterogeneous emulation.
> 

My point was not "please post that later", but simply to say those 
changes are not needed, now or in the future.
We can have a specific include path for various files without 
compromising the single binary/heterogenenous, as long as we compile it 
only once.

So we don't need to remove cpu.h inclusion in target related code.

>>> Use the full path to "cpu.h": "target/arm/cpu.h".
>>>
>>> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
>>> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
>>> ---
>>>    include/hw/arm/digic.h      | 2 +-
>>>    include/hw/arm/fsl-imx6.h   | 2 +-
>>>    include/hw/arm/fsl-imx6ul.h | 2 +-
>>>    include/hw/arm/fsl-imx7.h   | 2 +-
>>>    include/hw/arm/fsl-imx8mp.h | 2 +-
>>>    5 files changed, 5 insertions(+), 5 deletions(-)
> 

Re: [RFC PATCH-for-10.1 20/39] target/arm: Extract PSCI definitions to 'psci.h'

[Pierrick Bouvier]

On 4/4/25 14:54, Philippe Mathieu-Daudé wrote:
> On 4/4/25 20:21, Pierrick Bouvier wrote:
>> On 4/3/25 16:58, Philippe Mathieu-Daudé wrote:
>>> Extract PSCI definitions (which are not target specific)
>>> to the new "target/arm/psci.h", so code from hw/arm/ can
>>> use them without having to include the target specific
>>> "cpu.h" header.
>>>
>>
>> Including cpu.h is not a problem to have common code (per architecture),
>> so there is no need to do any change here.
> 
> Again, this is an old patch from my heterogeneous PoC branch.
> I'll remove from this series to not distract you.
> 

It's not distracting, but simply not needed.

>>
>>> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
>>> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
>>> ---
>>>    include/hw/arm/boot.h      |  3 ++-
>>>    target/arm/cpu.h           |  6 ------
>>>    target/arm/psci.h          | 18 ++++++++++++++++++
>>>    hw/arm/bananapi_m2u.c      |  1 +
>>>    hw/arm/boot.c              |  1 +
>>>    hw/arm/highbank.c          |  1 +
>>>    hw/arm/imx8mp-evk.c        |  1 +
>>>    hw/arm/mcimx6ul-evk.c      |  1 +
>>>    hw/arm/mcimx7d-sabre.c     |  1 +
>>>    hw/arm/orangepi.c          |  1 +
>>>    hw/arm/sbsa-ref.c          |  1 +
>>>    hw/arm/virt-acpi-build.c   |  1 +
>>>    hw/arm/virt.c              |  1 +
>>>    hw/arm/xlnx-versal-virt.c  |  1 +
>>>    hw/arm/xlnx-zcu102.c       |  1 +
>>>    hw/vmapple/vmapple.c       |  1 +
>>>    target/arm/helper.c        |  1 +
>>>    target/arm/hvf/hvf.c       |  1 +
>>>    target/arm/tcg/op_helper.c |  1 +
>>>    target/arm/tcg/psci.c      |  1 +
>>>    20 files changed, 37 insertions(+), 7 deletions(-)
>>>    create mode 100644 target/arm/psci.h
> 

Re: [RFC PATCH-for-10.1 27/39] system/hvf: Expose hvf_enabled() to common code

[Pierrick Bouvier]

On 4/4/25 14:56, Philippe Mathieu-Daudé wrote:
> +Paolo
> 
> On 4/4/25 20:23, Pierrick Bouvier wrote:
>> On 4/3/25 16:58, Philippe Mathieu-Daudé wrote:
>>> Currently hvf_enabled() is restricted to target-specific code.
>>> By defining CONFIG_HVF_IS_POSSIBLE we allow its use anywhere.
>>>
>>
>> Instead, we can simply make hvf_enabled present for common and target
>> specific code, and link correct implementation, based on what we build.
>>
>> I don't think *_IS_POSSIBLE was a good idea to start with.
> 
> IIUC the point of *_IS_POSSIBLE is to elide code, which we
> aren't interested anymore for host-related configs, so we
> can also remove CONFIG_KVM_IS_POSSIBLE and CONFIG_XEN_IS_POSSIBLE.
> Is that correct?
> 

Ideally, yes, we should not have any CONFIG_{accel}, of any 
CONFIG_{accel}_IS_POSSIBLE in the code.
It should only be used in build system to include selectively 
implementations based on host supporting it or not.

It's not needed to clean that right now, but if we can avoid to 
reproduce this for HVF, it's better.

>>
>>> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
>>> ---
>>>    MAINTAINERS             |  1 +
>>>    include/system/hvf.h    | 14 +++++++++-----
>>>    accel/stubs/hvf-stub.c  | 12 ++++++++++++
>>>    accel/stubs/meson.build |  1 +
>>>    4 files changed, 23 insertions(+), 5 deletions(-)
>>>    create mode 100644 accel/stubs/hvf-stub.c
>>>
>>> diff --git a/MAINTAINERS b/MAINTAINERS
>>> index c7083ab1d93..00ef33be0e2 100644
>>> --- a/MAINTAINERS
>>> +++ b/MAINTAINERS
>>> @@ -525,6 +525,7 @@ R: Phil Dennis-Jordan <phil@philjordan.eu>
>>>    W: https://wiki.qemu.org/Features/HVF
>>>    S: Maintained
>>>    F: accel/hvf/
>>> +F: accel/stubs/hvf-stub.c
>>>    F: include/system/hvf.h
>>>    F: include/system/hvf_int.h
>>> diff --git a/include/system/hvf.h b/include/system/hvf.h
>>> index d50049e1a1a..7b45a2e1988 100644
>>> --- a/include/system/hvf.h
>>> +++ b/include/system/hvf.h
>>> @@ -19,15 +19,19 @@
>>>    #include "qom/object.h"
>>>    #ifdef COMPILING_PER_TARGET
>>> +# ifdef CONFIG_HVF
>>> +#  define CONFIG_HVF_IS_POSSIBLE
>>> +# endif /* !CONFIG_HVF */
>>> +#else
>>> +# define CONFIG_HVF_IS_POSSIBLE
>>> +#endif /* COMPILING_PER_TARGET */
>>> -#ifdef CONFIG_HVF
>>> +#ifdef CONFIG_HVF_IS_POSSIBLE
>>>    extern bool hvf_allowed;
>>>    #define hvf_enabled() (hvf_allowed)
>>> -#else /* !CONFIG_HVF */
>>> +#else /* !CONFIG_HVF_IS_POSSIBLE */
>>>    #define hvf_enabled() 0
>>> -#endif /* !CONFIG_HVF */
>>> -
>>> -#endif /* COMPILING_PER_TARGET */
>>> +#endif /* !CONFIG_HVF_IS_POSSIBLE */
>>>    #define TYPE_HVF_ACCEL ACCEL_CLASS_NAME("hvf")
>>> diff --git a/accel/stubs/hvf-stub.c b/accel/stubs/hvf-stub.c
>>> new file mode 100644
>>> index 00000000000..42eadc5ca92
>>> --- /dev/null
>>> +++ b/accel/stubs/hvf-stub.c
>>> @@ -0,0 +1,12 @@
>>> +/*
>>> + * HVF stubs for QEMU
>>> + *
>>> + *  Copyright (c) Linaro
>>> + *
>>> + * SPDX-License-Identifier: GPL-2.0-or-later
>>> + */
>>> +
>>> +#include "qemu/osdep.h"
>>> +#include "system/hvf.h"
>>> +
>>> +bool hvf_allowed;
>>> diff --git a/accel/stubs/meson.build b/accel/stubs/meson.build
>>> index 91a2d219258..8ca1a4529e2 100644
>>> --- a/accel/stubs/meson.build
>>> +++ b/accel/stubs/meson.build
>>> @@ -2,5 +2,6 @@ system_stubs_ss = ss.source_set()
>>>    system_stubs_ss.add(when: 'CONFIG_XEN', if_false: files('xen-stub.c'))
>>>    system_stubs_ss.add(when: 'CONFIG_KVM', if_false: files('kvm-stub.c'))
>>>    system_stubs_ss.add(when: 'CONFIG_TCG', if_false: files('tcg-stub.c'))
>>> +system_stubs_ss.add(when: 'CONFIG_HVF', if_false: files('hvf-stub.c'))
>>>    specific_ss.add_all(when: ['CONFIG_SYSTEM_ONLY'], if_true:
>>> system_stubs_ss)
>>
> 

Re: [RFC PATCH-for-10.1 28/39] exec: Do not poison hardware accelerators

[Pierrick Bouvier]

On 4/4/25 15:00, Philippe Mathieu-Daudé wrote:
> +Paolo
> 
> On 4/4/25 20:25, Pierrick Bouvier wrote:
>> On 4/3/25 16:58, Philippe Mathieu-Daudé wrote:
>>> Hardware accelerators depends on the host, not the guest.
>>>
>>
>> While this is true, no we can't unpoison those define.
>> They are applied per target, and not in config-host. So unpoisoining
>> them opens the possibility to miss something.
>>
>> I would stick to clean up those ifdef instead, by exposing interface to
>> all code, and link appropriate stubs depending on the variant built.
> 
> OK, so IIUC this is the same reasoning than previous patch comment,
> always declare kvm_enabled() so code elision isn't possible anymore,
> then remove all CONFIG_KVM #ifdef'ry?
> 

Yes, right. And this CONFIG_{accel} will be used only in build system to 
select the host implementation or the stubbed one.

>>
>>> Suggested-by: Richard Henderson <richard.henderson@linaro.org>
>>> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
>>> ---
>>>    include/exec/poison.h         | 4 ----
>>>    scripts/make-config-p    oison.sh | 4 ++++
>>>    2 files changed, 4 insertions(+), 4 deletions(-)
>>>
>>> diff --git a/include/exec/poison.h b/include/exec/poison.h
>>> index 00aedc41d82..0574d683f6a 100644
>>> --- a/include/exec/poison.h
>>> +++ b/include/exec/poison.h
>>> @@ -62,11 +62,7 @@
>>>    #pragma GCC poison CONFIG_SPARC_DIS
>>>    #pragma GCC poison CONFIG_XTENSA_DIS
>>> -#pragma GCC poison CONFIG_HVF
>>>    #pragma GCC poison CONFIG_LINUX_USER
>>> -#pragma GCC poison CONFIG_KVM
>>> -#pragma GCC poison CONFIG_WHPX
>>> -#pragma GCC poison CONFIG_XEN
>>>    #ifndef COMPILING_SYSTEM_VS_USER
>>>    #pragma GCC poison CONFIG_USER_ONLY
>>> diff --git a/scripts/make-config-poison.sh b/scripts/make-config-
>>> poison.sh
>>> index 2b36907e239..09d2384745f 100755
>>> --- a/scripts/make-config-poison.sh
>>> +++ b/scripts/make-config-poison.sh
>>> @@ -8,6 +8,10 @@ fi
>>>    # but filter out several which are handled manually.
>>>    exec sed -n \
>>>      -e' /CONFIG_TCG/d' \
>>> +  -e' /CONFIG_HVF/d' \
>>> +  -e' /CONFIG_KVM/d' \
>>> +  -e' /CONFIG_WHPX/d' \
>>> +  -e' /CONFIG_XEN/d' \
>>>      -e '/CONFIG_USER_ONLY/d' \
>>>      -e '/CONFIG_SOFTMMU/d' \
>>>      -e '/^#define / {' \
>>
> 

Re: [RFC PATCH-for-10.1 35/39] hw/arm/virt: Replace TARGET_AARCH64 -> target_long_bits()

[Pierrick Bouvier]

On 4/4/25 15:05, Philippe Mathieu-Daudé wrote:
> On 4/4/25 20:28, Pierrick Bouvier wrote:
>> On 4/3/25 16:58, Philippe Mathieu-Daudé wrote:
>>> Replace the target-specific TARGET_AARCH64 definition
>>> by a call to the generic target_long_bits() helper.
>>>
>>> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
>>> ---
>>>    hw/arm/virt.c | 32 ++++++++++++++++----------------
>>>    1 file changed, 16 insertions(+), 16 deletions(-)
>>>
>>> diff --git a/hw/arm/virt.c b/hw/arm/virt.c
>>> index e241e71e1c3..a020f1bd581 100644
>>> --- a/hw/arm/virt.c
>>> +++ b/hw/arm/virt.c
>>> @@ -3133,25 +3133,25 @@ static void
>>> virt_machine_class_init(ObjectClass *oc, void *data)
>>>    #ifdef CONFIG_TCG
>>>        machine_class_add_valid_cpu_type(mc, ARM_CPU_TYPE_NAME("cortex-
>>> a7"));
>>>        machine_class_add_valid_cpu_type(mc, ARM_CPU_TYPE_NAME("cortex-
>>> a15"));
>>> -#ifdef TARGET_AARCH64
>>> -    machine_class_add_valid_cpu_type(mc, ARM_CPU_TYPE_NAME("cortex-
>>> a35"));
>>> -    machine_class_add_valid_cpu_type(mc, ARM_CPU_TYPE_NAME("cortex-
>>> a55"));
>>> -    machine_class_add_valid_cpu_type(mc, ARM_CPU_TYPE_NAME("cortex-
>>> a72"));
>>> -    machine_class_add_valid_cpu_type(mc, ARM_CPU_TYPE_NAME("cortex-
>>> a76"));
>>> -    machine_class_add_valid_cpu_type(mc, ARM_CPU_TYPE_NAME("cortex-
>>> a710"));
>>> -    machine_class_add_valid_cpu_type(mc, ARM_CPU_TYPE_NAME("a64fx"));
>>> -    machine_class_add_valid_cpu_type(mc, ARM_CPU_TYPE_NAME("neoverse-
>>> n1"));
>>> -    machine_class_add_valid_cpu_type(mc, ARM_CPU_TYPE_NAME("neoverse-
>>> v1"));
>>> -    machine_class_add_valid_cpu_type(mc, ARM_CPU_TYPE_NAME("neoverse-
>>> n2"));
>>> -#endif /* TARGET_AARCH64 */
>>> +    if (target_long_bits() == 64) {
>>
>> I would prefer if we introduce a true target_aarch64() function, and
>> probably the same for other architectures when it will be needed.
>>
>> If we start using target_long_bits(), we might enable something in
>> common code that we are not supposed to do. And it will be much harder
>> to find it later when we debug heterogenenous emulation.
> 
> I get your point. Maybe we can register valid aa64 CPUs regardless,
> and filter for registered QOM CPUs? OTOH your suggestion of
> TARGET_AARCH64 -> target_aarch64() could be easier to review.
> I''ll give it a try.
> 

I think it's better to customize the list creation directly, instead of 
adding another hook to filter things afterward.
As well, it's obvious when reading the code, the same way current ifdef 
are obvious when reading them.

>>
>>> +        machine_class_add_valid_cpu_type(mc,
>>> ARM_CPU_TYPE_NAME("cortex-a35"));
>>> +        machine_class_add_valid_cpu_type(mc,
>>> ARM_CPU_TYPE_NAME("cortex-a55"));
>>> +        machine_class_add_valid_cpu_type(mc,
>>> ARM_CPU_TYPE_NAME("cortex-a72"));
>>> +        machine_class_add_valid_cpu_type(mc,
>>> ARM_CPU_TYPE_NAME("cortex-a76"));
>>> +        machine_class_add_valid_cpu_type(mc,
>>> ARM_CPU_TYPE_NAME("cortex-a710"));
>>> +        machine_class_add_valid_cpu_type(mc,
>>> ARM_CPU_TYPE_NAME("a64fx"));
>>> +        machine_class_add_valid_cpu_type(mc,
>>> ARM_CPU_TYPE_NAME("neoverse-n1"));
>>> +        machine_class_add_valid_cpu_type(mc,
>>> ARM_CPU_TYPE_NAME("neoverse-v1"));
>>> +        machine_class_add_valid_cpu_type(mc,
>>> ARM_CPU_TYPE_NAME("neoverse-n2"));
>>> +    }
>>>    #endif /* CONFIG_TCG */
>>> -#ifdef TARGET_AARCH64
>>> -    machine_class_add_valid_cpu_type(mc, ARM_CPU_TYPE_NAME("cortex-
>>> a53"));
>>> -    machine_class_add_valid_cpu_type(mc, ARM_CPU_TYPE_NAME("cortex-
>>> a57"));
>>> +    if (target_long_bits() == 64) {
>>> +        machine_class_add_valid_cpu_type(mc,
>>> ARM_CPU_TYPE_NAME("cortex-a53"));
>>> +        machine_class_add_valid_cpu_type(mc,
>>> ARM_CPU_TYPE_NAME("cortex-a57"));
>>>    #if defined(CONFIG_KVM) || defined(CONFIG_HVF)
>>> -    machine_class_add_valid_cpu_type(mc, ARM_CPU_TYPE_NAME("host"));
>>> +        machine_class_add_valid_cpu_type(mc, ARM_CPU_TYPE_NAME("host"));
>>>    #endif /* CONFIG_KVM || CONFIG_HVF */
>>> -#endif /* TARGET_AARCH64 */
>>> +    }
>>>        machine_class_add_valid_cpu_type(mc, ARM_CPU_TYPE_NAME("max"));
>>>        mc->init = machvirt_init;
>>
> 

Re: [RFC PATCH-for-10.1 11/39] hw/arm: Use full "target/arm/cpu.h" path to include target's "cpu.h"

[Philippe Mathieu-Daudé]

On 5/4/25 03:03, Pierrick Bouvier wrote:
> On 4/4/25 14:53, Philippe Mathieu-Daudé wrote:
>> On 4/4/25 20:20, Pierrick Bouvier wrote:
>>> On 4/3/25 16:57, Philippe Mathieu-Daudé wrote:
>>>> We would like to get rid of '-I target/$ARCH/' in the CPPFLAGS.
>>>
>>> While this change is correct, this is not strictly needed.
>>> With the current approach, using a set of common files per architecture,
>>> we can rely on this include to be present, and it does not block from
>>> having common files.
>>
>> Indeed, I rebased this commit from my heterogeneous branch.
>>
>> I'll keeping carrying / rebasing it for various months, trying to
>> remember to not keeping posting it.
>>
>> Or alternatively I'll post it in a separate "cleanup series", not
>> mentioning single-binary or heterogeneous emulation.
>>
> 
> My point was not "please post that later", but simply to say those 
> changes are not needed, now or in the future.
> We can have a specific include path for various files without 
> compromising the single binary/heterogenenous, as long as we compile it 
> only once.

Incorrect, this is required for heterogenenous emulation.

> So we don't need to remove cpu.h inclusion in target related code.
> 
>>>> Use the full path to "cpu.h": "target/arm/cpu.h".
>>>>
>>>> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
>>>> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
>>>> ---
>>>>    include/hw/arm/digic.h      | 2 +-
>>>>    include/hw/arm/fsl-imx6.h   | 2 +-
>>>>    include/hw/arm/fsl-imx6ul.h | 2 +-
>>>>    include/hw/arm/fsl-imx7.h   | 2 +-
>>>>    include/hw/arm/fsl-imx8mp.h | 2 +-
>>>>    5 files changed, 5 insertions(+), 5 deletions(-)
>>
> 

Re: [RFC PATCH-for-10.1 20/39] target/arm: Extract PSCI definitions to 'psci.h'

[Philippe Mathieu-Daudé]

On 5/4/25 03:03, Pierrick Bouvier wrote:
> On 4/4/25 14:54, Philippe Mathieu-Daudé wrote:
>> On 4/4/25 20:21, Pierrick Bouvier wrote:
>>> On 4/3/25 16:58, Philippe Mathieu-Daudé wrote:
>>>> Extract PSCI definitions (which are not target specific)
>>>> to the new "target/arm/psci.h", so code from hw/arm/ can
>>>> use them without having to include the target specific
>>>> "cpu.h" header.
>>>>
>>>
>>> Including cpu.h is not a problem to have common code (per architecture),
>>> so there is no need to do any change here.
>>
>> Again, this is an old patch from my heterogeneous PoC branch.
>> I'll remove from this series to not distract you.
>>
> 
> It's not distracting, but simply not needed.

Not needed for single-binary, but needed for heterogeneous emulation,
as the same HW might use distinct architectures.

> 
>>>
>>>> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
>>>> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
>>>> ---
>>>>    include/hw/arm/boot.h      |  3 ++-
>>>>    target/arm/cpu.h           |  6 ------
>>>>    target/arm/psci.h          | 18 ++++++++++++++++++
>>>>    hw/arm/bananapi_m2u.c      |  1 +
>>>>    hw/arm/boot.c              |  1 +
>>>>    hw/arm/highbank.c          |  1 +
>>>>    hw/arm/imx8mp-evk.c        |  1 +
>>>>    hw/arm/mcimx6ul-evk.c      |  1 +
>>>>    hw/arm/mcimx7d-sabre.c     |  1 +
>>>>    hw/arm/orangepi.c          |  1 +
>>>>    hw/arm/sbsa-ref.c          |  1 +
>>>>    hw/arm/virt-acpi-build.c   |  1 +
>>>>    hw/arm/virt.c              |  1 +
>>>>    hw/arm/xlnx-versal-virt.c  |  1 +
>>>>    hw/arm/xlnx-zcu102.c       |  1 +
>>>>    hw/vmapple/vmapple.c       |  1 +
>>>>    target/arm/helper.c        |  1 +
>>>>    target/arm/hvf/hvf.c       |  1 +
>>>>    target/arm/tcg/op_helper.c |  1 +
>>>>    target/arm/tcg/psci.c      |  1 +
>>>>    20 files changed, 37 insertions(+), 7 deletions(-)
>>>>    create mode 100644 target/arm/psci.h
>>
> 

Re: [RFC PATCH-for-10.1 11/39] hw/arm: Use full "target/arm/cpu.h" path to include target's "cpu.h"

[Pierrick Bouvier]

On 4/5/25 07:27, Philippe Mathieu-Daudé wrote:
> On 5/4/25 03:03, Pierrick Bouvier wrote:
>> On 4/4/25 14:53, Philippe Mathieu-Daudé wrote:
>>> On 4/4/25 20:20, Pierrick Bouvier wrote:
>>>> On 4/3/25 16:57, Philippe Mathieu-Daudé wrote:
>>>>> We would like to get rid of '-I target/$ARCH/' in the CPPFLAGS.
>>>>
>>>> While this change is correct, this is not strictly needed.
>>>> With the current approach, using a set of common files per architecture,
>>>> we can rely on this include to be present, and it does not block from
>>>> having common files.
>>>
>>> Indeed, I rebased this commit from my heterogeneous branch.
>>>
>>> I'll keeping carrying / rebasing it for various months, trying to
>>> remember to not keeping posting it.
>>>
>>> Or alternatively I'll post it in a separate "cleanup series", not
>>> mentioning single-binary or heterogeneous emulation.
>>>
>>
>> My point was not "please post that later", but simply to say those
>> changes are not needed, now or in the future.
>> We can have a specific include path for various files without
>> compromising the single binary/heterogenenous, as long as we compile it
>> only once.
> 
> Incorrect, this is required for heterogenenous emulation.
> 

There are probably two different topics here.

If by "this", you mean the current change (include explicit 
target/X/cpu.h), then no, it's not required.
Changing include "cpu.h" to include "target/arm/cpu.h" has absolutely no 
effect for the common files in hw/arm, as they are already compiled with 
-I target/arm. It produces the exact same compilation unit.
I did the same change as you do here when working on hw/arm, and finally 
understood it had no effect, so I reverted it, and simply let the 
original include "cpu.h".

If you were talking about accessing arm/cpu.h features, then I still 
don't see why it's needed. There is no reason any code out of hw/arm or 
target/arm should access this. If I missed something, feel free to post 
a concrete example of where it's needed.

In any case, if any hw code relies on cpu.h inclusion, it will not 
compile when we make it common, because cpu.h won't be found.
At this time, and only at this time, then we'll extract the expected 
interface, and expose it to common code. But before we meet the 
situation, I don't think we should do any of those changes.

Pierrick

Re: [RFC PATCH-for-10.1 20/39] target/arm: Extract PSCI definitions to 'psci.h'

[Pierrick Bouvier]

On 4/5/25 07:43, Philippe Mathieu-Daudé wrote:
> On 5/4/25 03:03, Pierrick Bouvier wrote:
>> On 4/4/25 14:54, Philippe Mathieu-Daudé wrote:
>>> On 4/4/25 20:21, Pierrick Bouvier wrote:
>>>> On 4/3/25 16:58, Philippe Mathieu-Daudé wrote:
>>>>> Extract PSCI definitions (which are not target specific)
>>>>> to the new "target/arm/psci.h", so code from hw/arm/ can
>>>>> use them without having to include the target specific
>>>>> "cpu.h" header.
>>>>>
>>>>
>>>> Including cpu.h is not a problem to have common code (per architecture),
>>>> so there is no need to do any change here.
>>>
>>> Again, this is an old patch from my heterogeneous PoC branch.
>>> I'll remove from this series to not distract you.
>>>
>>
>> It's not distracting, but simply not needed.
> 
> Not needed for single-binary, but needed for heterogeneous emulation,
> as the same HW might use distinct architectures.
> 

In the list of files modified by the current change, the only 
potentially concerned file is hw/vmapple/vmapple.c, as all others are in 
hw/arm or target/arm, so cpu.h is not ambiguous, and already accessible.

As it's an implementation of "Apple aarch64 Virtual Machine", either:
- we can include target/arm/cpu.h explicitely (so QEMU_PSCI_* enum is 
visible).
- we can add it to arm_common_ss, so cpu.h becomes unambiguous.
- The most correct: it should be moved to hw/arm/vmapple/ and added to 
arm_common_ss.

I don't mind which solution we pick up among those three (personal 
preference for the third one).

That said, the current approach to extract code only to make it 
accessible for a single source file that is not correctly located in the 
codebase is not the right one.

>>
>>>>
>>>>> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
>>>>> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
>>>>> ---
>>>>>     include/hw/arm/boot.h      |  3 ++-
>>>>>     target/arm/cpu.h           |  6 ------
>>>>>     target/arm/psci.h          | 18 ++++++++++++++++++
>>>>>     hw/arm/bananapi_m2u.c      |  1 +
>>>>>     hw/arm/boot.c              |  1 +
>>>>>     hw/arm/highbank.c          |  1 +
>>>>>     hw/arm/imx8mp-evk.c        |  1 +
>>>>>     hw/arm/mcimx6ul-evk.c      |  1 +
>>>>>     hw/arm/mcimx7d-sabre.c     |  1 +
>>>>>     hw/arm/orangepi.c          |  1 +
>>>>>     hw/arm/sbsa-ref.c          |  1 +
>>>>>     hw/arm/virt-acpi-build.c   |  1 +
>>>>>     hw/arm/virt.c              |  1 +
>>>>>     hw/arm/xlnx-versal-virt.c  |  1 +
>>>>>     hw/arm/xlnx-zcu102.c       |  1 +
>>>>>     hw/vmapple/vmapple.c       |  1 +
>>>>>     target/arm/helper.c        |  1 +
>>>>>     target/arm/hvf/hvf.c       |  1 +
>>>>>     target/arm/tcg/op_helper.c |  1 +
>>>>>     target/arm/tcg/psci.c      |  1 +
>>>>>     20 files changed, 37 insertions(+), 7 deletions(-)
>>>>>     create mode 100644 target/arm/psci.h
>>>
>>
> 

Re: [RFC PATCH-for-10.1 26/39] system/hvf: Avoid including 'cpu.h'

[Philippe Mathieu-Daudé]

ping?

On 4/4/25 01:58, Philippe Mathieu-Daudé wrote:
> "system/hvf.h" doesn't need to include a full "cpu.h",
> only "exec/vaddr.h" and "qemu/queue.h" are required.
> 
> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
> ---
>   include/system/hvf.h     | 3 ++-
>   include/system/hvf_int.h | 2 ++
>   2 files changed, 4 insertions(+), 1 deletion(-)
> 
> diff --git a/include/system/hvf.h b/include/system/hvf.h
> index 730f927f034..d50049e1a1a 100644
> --- a/include/system/hvf.h
> +++ b/include/system/hvf.h
> @@ -14,10 +14,11 @@
>   #define HVF_H
>   
>   #include "qemu/accel.h"
> +#include "qemu/queue.h"
> +#include "exec/vaddr.h"
>   #include "qom/object.h"
>   
>   #ifdef COMPILING_PER_TARGET
> -#include "cpu.h"
>   
>   #ifdef CONFIG_HVF
>   extern bool hvf_allowed;
> diff --git a/include/system/hvf_int.h b/include/system/hvf_int.h
> index 42ae18433f0..8c8b84012d9 100644
> --- a/include/system/hvf_int.h
> +++ b/include/system/hvf_int.h
> @@ -11,6 +11,8 @@
>   #ifndef HVF_INT_H
>   #define HVF_INT_H
>   
> +#include "qemu/queue.h"
> +
>   #ifdef __aarch64__
>   #include <Hypervisor/Hypervisor.h>
>   typedef hv_vcpu_t hvf_vcpuid;

Re: [RFC PATCH-for-10.1 26/39] system/hvf: Avoid including 'cpu.h'

[Pierrick Bouvier]

On 5/6/25 7:14 AM, Philippe Mathieu-Daudé wrote:
> ping?
> 
> On 4/4/25 01:58, Philippe Mathieu-Daudé wrote:
>> "system/hvf.h" doesn't need to include a full "cpu.h",
>> only "exec/vaddr.h" and "qemu/queue.h" are required.
>>
>> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
>> ---
>>    include/system/hvf.h     | 3 ++-
>>    include/system/hvf_int.h | 2 ++
>>    2 files changed, 4 insertions(+), 1 deletion(-)

Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>