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From: "Philippe Mathieu-Daudé" <philmd@linaro.org>
To: qemu-devel@nongnu.org
Cc: "Richard Henderson" <richard.henderson@linaro.org>,
	"Philippe Mathieu-Daudé" <philmd@linaro.org>
Subject: [PATCH-for-10.1 v4 01/16] target/riscv: Remove AccelCPUClass::cpu_class_init need
Date: Sat,  5 Apr 2025 18:13:05 +0200	[thread overview]
Message-ID: <20250405161320.76854-2-philmd@linaro.org> (raw)
In-Reply-To: <20250405161320.76854-1-philmd@linaro.org>

Expose riscv_tcg_ops symbol, then directly set it as
CPUClass::tcg_ops in TYPE_RISCV_CPU's class_init(),
using CONFIG_TCG #ifdef'ry. No need for the
AccelCPUClass::cpu_class_init() handler anymore.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
 target/riscv/tcg/tcg-cpu.h |  2 ++
 target/riscv/cpu.c         |  3 +++
 target/riscv/tcg/tcg-cpu.c | 16 +---------------
 3 files changed, 6 insertions(+), 15 deletions(-)

diff --git a/target/riscv/tcg/tcg-cpu.h b/target/riscv/tcg/tcg-cpu.h
index ce94253fe42..a23716a5acf 100644
--- a/target/riscv/tcg/tcg-cpu.h
+++ b/target/riscv/tcg/tcg-cpu.h
@@ -26,6 +26,8 @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp);
 void riscv_tcg_cpu_finalize_features(RISCVCPU *cpu, Error **errp);
 bool riscv_cpu_tcg_compatible(RISCVCPU *cpu);
 
+extern const TCGCPUOps riscv_tcg_ops;
+
 struct DisasContext;
 struct RISCVCPUConfig;
 typedef struct RISCVDecoder {
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index ad534cee51f..2b830b33178 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -3054,6 +3054,9 @@ static void riscv_cpu_common_class_init(ObjectClass *c, void *data)
     cc->get_arch_id = riscv_get_arch_id;
 #endif
     cc->gdb_arch_name = riscv_gdb_arch_name;
+#ifdef CONFIG_TCG
+    cc->tcg_ops = &riscv_tcg_ops;
+#endif /* CONFIG_TCG */
 
     device_class_set_props(dc, riscv_cpu_properties);
 }
diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
index 5d0429b4d00..6a87367f239 100644
--- a/target/riscv/tcg/tcg-cpu.c
+++ b/target/riscv/tcg/tcg-cpu.c
@@ -139,7 +139,7 @@ static void riscv_restore_state_to_opc(CPUState *cs,
     env->excp_uw2 = data[2];
 }
 
-static const TCGCPUOps riscv_tcg_ops = {
+const TCGCPUOps riscv_tcg_ops = {
     .initialize = riscv_translate_init,
     .translate_code = riscv_translate_code,
     .synchronize_from_tb = riscv_cpu_synchronize_from_tb,
@@ -1524,24 +1524,10 @@ static void riscv_tcg_cpu_instance_init(CPUState *cs)
     }
 }
 
-static void riscv_tcg_cpu_init_ops(AccelCPUClass *accel_cpu, CPUClass *cc)
-{
-    /*
-     * All cpus use the same set of operations.
-     */
-    cc->tcg_ops = &riscv_tcg_ops;
-}
-
-static void riscv_tcg_cpu_class_init(CPUClass *cc)
-{
-    cc->init_accel_cpu = riscv_tcg_cpu_init_ops;
-}
-
 static void riscv_tcg_cpu_accel_class_init(ObjectClass *oc, void *data)
 {
     AccelCPUClass *acc = ACCEL_CPU_CLASS(oc);
 
-    acc->cpu_class_init = riscv_tcg_cpu_class_init;
     acc->cpu_instance_init = riscv_tcg_cpu_instance_init;
     acc->cpu_target_realize = riscv_tcg_cpu_realize;
 }
-- 
2.47.1



  reply	other threads:[~2025-04-05 16:14 UTC|newest]

Thread overview: 17+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-04-05 16:13 [PATCH-for-10.1 v4 00/16] tcg: philmd's queue Philippe Mathieu-Daudé
2025-04-05 16:13 ` Philippe Mathieu-Daudé [this message]
2025-04-05 16:13 ` [PATCH-for-10.1 v4 02/16] target/i386: Remove AccelCPUClass::cpu_class_init need Philippe Mathieu-Daudé
2025-04-05 16:13 ` [PATCH-for-10.1 v4 03/16] accel: Remove AccelCPUClass::cpu_class_init() callback Philippe Mathieu-Daudé
2025-04-05 16:13 ` [PATCH-for-10.1 v4 04/16] target/hexagon: Add memory order definition Philippe Mathieu-Daudé
2025-04-05 16:13 ` [PATCH-for-10.1 v4 05/16] tcg: Always define TCG_GUEST_DEFAULT_MO Philippe Mathieu-Daudé
2025-04-05 16:13 ` [PATCH-for-10.1 v4 06/16] tcg: Simplify tcg_req_mo() macro Philippe Mathieu-Daudé
2025-04-05 16:13 ` [PATCH-for-10.1 v4 07/16] tcg: Define guest_default_memory_order in TCGCPUOps Philippe Mathieu-Daudé
2025-04-05 16:13 ` [PATCH-for-10.1 v4 08/16] tcg: Remove use of TCG_GUEST_DEFAULT_MO in tb_gen_code() Philippe Mathieu-Daudé
2025-04-05 16:13 ` [PATCH-for-10.1 v4 09/16] tcg: Propagate CPUState argument to cpu_req_mo() Philippe Mathieu-Daudé
2025-04-05 16:13 ` [PATCH-for-10.1 v4 10/16] tcg: Have tcg_req_mo() use TCGCPUOps::guest_default_memory_order Philippe Mathieu-Daudé
2025-04-05 16:13 ` [PATCH-for-10.1 v4 11/16] tcg: Remove the TCG_GUEST_DEFAULT_MO definition globally Philippe Mathieu-Daudé
2025-04-05 16:13 ` [PATCH-for-10.1 v4 12/16] tcg: Move cpu_req_mo() macro to target-agnostic 'backend-ldst.h' Philippe Mathieu-Daudé
2025-04-05 16:13 ` [PATCH-for-10.1 v4 13/16] tcg: Move qemu_tcg_mttcg_enabled() to 'system/tcg.h' Philippe Mathieu-Daudé
2025-04-05 16:13 ` [PATCH-for-10.1 v4 14/16] tcg: Convert TCGState::mttcg_enabled to TriState Philippe Mathieu-Daudé
2025-04-05 16:13 ` [PATCH-for-10.1 v4 15/16] tcg: Factor mttcg_init() out Philippe Mathieu-Daudé
2025-04-05 16:13 ` [PATCH-for-10.1 v4 16/16] tcg: Convert TARGET_SUPPORTS_MTTCG to TCGCPUOps::mttcg_supported field Philippe Mathieu-Daudé

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