[PATCH 0/2] pl011: Refactor DR register handling in Rust implementation

[PATCH 0/2] pl011: Refactor DR register handling in Rust implementation

[Rakesh Jeyasingh]

This patch series refactors the rust PL011Registers read/write for DR:
Patch 1/2 extracts DR read logic
Patch 2/2 extracts DR write logic

Rakesh Jeyasingh (2):
  rust/hw/char/pl011: Extract extract DR read logic into separate
    function
  rust/hw/char/pl011: Extract DR write logic into separate function

 rust/hw/char/pl011/src/device.rs | 53 +++++++++++++++++---------------
 1 file changed, 28 insertions(+), 25 deletions(-)

-- 
2.43.0

[PATCH 1/2] rust/hw/char/pl011: Extract extract DR read logic into separate function

[Rakesh Jeyasingh]

- Split `read()` DR case into `read_data_register()`

Signed-off-by: Rakesh Jeyasingh <rakeshjb010@gmail.com>
---
 rust/hw/char/pl011/src/device.rs | 39 ++++++++++++++++----------------
 1 file changed, 20 insertions(+), 19 deletions(-)

diff --git a/rust/hw/char/pl011/src/device.rs b/rust/hw/char/pl011/src/device.rs
index bf88e0b00a..87153cdae1 100644
--- a/rust/hw/char/pl011/src/device.rs
+++ b/rust/hw/char/pl011/src/device.rs
@@ -190,25 +190,7 @@ pub(self) fn read(&mut self, offset: RegisterOffset) -> (bool, u32) {
 
         let mut update = false;
         let result = match offset {
-            DR => {
-                self.flags.set_receive_fifo_full(false);
-                let c = self.read_fifo[self.read_pos];
-                if self.read_count > 0 {
-                    self.read_count -= 1;
-                    self.read_pos = (self.read_pos + 1) & (self.fifo_depth() - 1);
-                }
-                if self.read_count == 0 {
-                    self.flags.set_receive_fifo_empty(true);
-                }
-                if self.read_count + 1 == self.read_trigger {
-                    self.int_level &= !Interrupt::RX.0;
-                }
-                // Update error bits.
-                self.receive_status_error_clear.set_from_data(c);
-                // Must call qemu_chr_fe_accept_input
-                update = true;
-                u32::from(c)
-            }
+            DR => self.read_data_register(&mut update),
             RSR => u32::from(self.receive_status_error_clear),
             FR => u32::from(self.flags),
             FBRD => self.fbrd,
@@ -306,6 +288,25 @@ pub(self) fn write(
         false
     }
 
+    fn read_data_register(&mut self, update: &mut bool) -> u32 {
+        self.flags.set_receive_fifo_full(false);
+        let c = self.read_fifo[self.read_pos];
+
+        if self.read_count > 0 {
+            self.read_count -= 1;
+            self.read_pos = (self.read_pos + 1) & (self.fifo_depth() - 1);
+        }
+        if self.read_count == 0 {
+            self.flags.set_receive_fifo_empty(true);
+        }
+        if self.read_count + 1 == self.read_trigger {
+            self.int_level &= !Interrupt::RX.0;
+        }
+        self.receive_status_error_clear.set_from_data(c);
+        *update = true;
+        u32::from(c)
+    }
+
     #[inline]
     #[must_use]
     fn loopback_tx(&mut self, value: registers::Data) -> bool {
-- 
2.43.0

[PATCH 2/2] rust/hw/char/pl011: Extract DR write logic into separate function

[Rakesh Jeyasingh]

- Split `write()` DR case into `write_data_register()`

Signed-off-by: Rakesh Jeyasingh <rakeshjb010@gmail.com>
---
 rust/hw/char/pl011/src/device.rs | 14 ++++++++------
 1 file changed, 8 insertions(+), 6 deletions(-)

diff --git a/rust/hw/char/pl011/src/device.rs b/rust/hw/char/pl011/src/device.rs
index 87153cdae1..bb2a0f207a 100644
--- a/rust/hw/char/pl011/src/device.rs
+++ b/rust/hw/char/pl011/src/device.rs
@@ -221,12 +221,7 @@ pub(self) fn write(
         // eprintln!("write offset {offset} value {value}");
         use RegisterOffset::*;
         match offset {
-            DR => {
-                // interrupts always checked
-                let _ = self.loopback_tx(value.into());
-                self.int_level |= Interrupt::TX.0;
-                return true;
-            }
+            DR => return self.write_data_register(value),
             RSR => {
                 self.receive_status_error_clear = 0.into();
             }
@@ -307,6 +302,13 @@ fn read_data_register(&mut self, update: &mut bool) -> u32 {
         u32::from(c)
     }
 
+    fn write_data_register(&mut self, value: u32) -> bool {
+        // interrupts always checked
+        let _ = self.loopback_tx(value.into());
+        self.int_level |= Interrupt::TX.0;
+        true
+    }
+
     #[inline]
     #[must_use]
     fn loopback_tx(&mut self, value: registers::Data) -> bool {
-- 
2.43.0

Re: [PATCH 0/2] pl011: Refactor DR register handling in Rust implementation

[Paolo Bonzini]

Queued, thanks.

Paolo