* [PATCH v3 1/2] target/riscv: Add BOSC's Xiangshan Kunminghu CPU
@ 2025-04-08 2:21 Huang Borong
2025-04-08 12:47 ` Daniel Henrique Barboza
2025-04-24 10:49 ` Alistair Francis
0 siblings, 2 replies; 4+ messages in thread
From: Huang Borong @ 2025-04-08 2:21 UTC (permalink / raw)
To: qemu-riscv
Cc: palmer, alistair.francis, liwei1518, dbarboza, zhiwei_liu,
qemu-devel, wangran, Huang Borong
Add a CPU entry for the Xiangshan Kunminghu CPU, an open-source,
high-performance RISC-V processor. More details can be found at:
https://github.com/OpenXiangShan/XiangShan
Note: The ISA extensions supported by the Xiangshan Kunminghu CPU are
categorized based on four RISC-V specifications: Volume I: Unprivileged
Architecture, Volume II: Privileged Architecture, AIA, and RVA23. The
extensions within each category are organized according to the chapter
order in the specifications.
Signed-off-by: Yu Hu <huyu@bosc.ac.cn>
Signed-off-by: Ran Wang <wangran@bosc.ac.cn>
Signed-off-by: Borong Huang <huangborong@bosc.ac.cn>
---
target/riscv/cpu-qom.h | 1 +
target/riscv/cpu.c | 72 ++++++++++++++++++++++++++++++++++++++++++
2 files changed, 73 insertions(+)
diff --git a/target/riscv/cpu-qom.h b/target/riscv/cpu-qom.h
index 4cfdb74891..f2908939e7 100644
--- a/target/riscv/cpu-qom.h
+++ b/target/riscv/cpu-qom.h
@@ -53,6 +53,7 @@
#define TYPE_RISCV_CPU_VEYRON_V1 RISCV_CPU_TYPE_NAME("veyron-v1")
#define TYPE_RISCV_CPU_TT_ASCALON RISCV_CPU_TYPE_NAME("tt-ascalon")
#define TYPE_RISCV_CPU_XIANGSHAN_NANHU RISCV_CPU_TYPE_NAME("xiangshan-nanhu")
+#define TYPE_RISCV_CPU_XIANGSHAN_KMH RISCV_CPU_TYPE_NAME("xiangshan-kunminghu")
#define TYPE_RISCV_CPU_HOST RISCV_CPU_TYPE_NAME("host")
OBJECT_DECLARE_CPU_TYPE(RISCVCPU, RISCVCPUClass, RISCV_CPU)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 09ded6829a..a076d9dc0c 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -697,6 +697,76 @@ static void rv64_xiangshan_nanhu_cpu_init(Object *obj)
#endif
}
+static void rv64_xiangshan_kmh_cpu_init(Object *obj)
+{
+ CPURISCVState *env = &RISCV_CPU(obj)->env;
+ RISCVCPU *cpu = RISCV_CPU(obj);
+
+ riscv_cpu_set_misa_ext(env, RVG | RVC | RVB | RVS | RVU | RVH | RVV);
+ env->priv_ver = PRIV_VERSION_1_13_0;
+
+ /* Enable ISA extensions */
+ cpu->cfg.mmu = true;
+ cpu->cfg.pmp = true;
+
+ /*
+ * The RISC-V Instruction Set Manual: Volume I
+ * Unprivileged Architecture
+ */
+ cpu->cfg.ext_zicntr = true;
+ cpu->cfg.ext_zihpm = true;
+ cpu->cfg.ext_zihintntl = true;
+ cpu->cfg.ext_zihintpause = true;
+ cpu->cfg.ext_zimop = true;
+ cpu->cfg.ext_zcmop = true;
+ cpu->cfg.ext_zicond = true;
+ cpu->cfg.ext_zawrs = true;
+ cpu->cfg.ext_zacas = true;
+ cpu->cfg.ext_zfh = true;
+ cpu->cfg.ext_zfa = true;
+ cpu->cfg.ext_zcb = true;
+ cpu->cfg.ext_zbc = true;
+ cpu->cfg.ext_zvfh = true;
+ cpu->cfg.ext_zkn = true;
+ cpu->cfg.ext_zks = true;
+ cpu->cfg.ext_zkt = true;
+ cpu->cfg.ext_zvbb = true;
+ cpu->cfg.ext_zvkt = true;
+
+ /*
+ * The RISC-V Instruction Set Manual: Volume II
+ * Privileged Architecture
+ */
+ cpu->cfg.ext_smstateen = true;
+ cpu->cfg.ext_smcsrind = true;
+ cpu->cfg.ext_sscsrind = true;
+ cpu->cfg.ext_svnapot = true;
+ cpu->cfg.ext_svpbmt = true;
+ cpu->cfg.ext_svinval = true;
+ cpu->cfg.ext_sstc = true;
+ cpu->cfg.ext_sscofpmf = true;
+ cpu->cfg.ext_ssdbltrp = true;
+ cpu->cfg.ext_ssnpm = true;
+ cpu->cfg.ext_smnpm = true;
+ cpu->cfg.ext_smmpm = true;
+ cpu->cfg.ext_sspm = true;
+ cpu->cfg.ext_supm = true;
+
+ /* The RISC-V Advanced Interrupt Architecture */
+ cpu->cfg.ext_smaia = true;
+ cpu->cfg.ext_ssaia = true;
+
+ /* RVA23 Profiles */
+ cpu->cfg.ext_zicbom = true;
+ cpu->cfg.ext_zicbop = true;
+ cpu->cfg.ext_zicboz = true;
+ cpu->cfg.ext_svade = true;
+
+#ifndef CONFIG_USER_ONLY
+ set_satp_mode_max_supported(cpu, VM_1_10_SV48);
+#endif
+}
+
#ifdef CONFIG_TCG
static void rv128_base_cpu_init(Object *obj)
{
@@ -3261,6 +3331,8 @@ static const TypeInfo riscv_cpu_type_infos[] = {
DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_VEYRON_V1, MXL_RV64, rv64_veyron_v1_cpu_init),
DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_XIANGSHAN_NANHU,
MXL_RV64, rv64_xiangshan_nanhu_cpu_init),
+ DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_XIANGSHAN_KMH,
+ MXL_RV64, rv64_xiangshan_kmh_cpu_init),
#ifdef CONFIG_TCG
DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_BASE128, MXL_RV128, rv128_base_cpu_init),
#endif /* CONFIG_TCG */
--
2.34.1
^ permalink raw reply related [flat|nested] 4+ messages in thread
* Re: [PATCH v3 1/2] target/riscv: Add BOSC's Xiangshan Kunminghu CPU
2025-04-08 2:21 [PATCH v3 1/2] target/riscv: Add BOSC's Xiangshan Kunminghu CPU Huang Borong
@ 2025-04-08 12:47 ` Daniel Henrique Barboza
2025-04-24 10:49 ` Alistair Francis
1 sibling, 0 replies; 4+ messages in thread
From: Daniel Henrique Barboza @ 2025-04-08 12:47 UTC (permalink / raw)
To: Huang Borong, qemu-riscv
Cc: palmer, alistair.francis, liwei1518, zhiwei_liu, qemu-devel,
wangran
On 4/7/25 11:21 PM, Huang Borong wrote:
> Add a CPU entry for the Xiangshan Kunminghu CPU, an open-source,
> high-performance RISC-V processor. More details can be found at:
> https://github.com/OpenXiangShan/XiangShan
>
> Note: The ISA extensions supported by the Xiangshan Kunminghu CPU are
> categorized based on four RISC-V specifications: Volume I: Unprivileged
> Architecture, Volume II: Privileged Architecture, AIA, and RVA23. The
> extensions within each category are organized according to the chapter
> order in the specifications.
>
> Signed-off-by: Yu Hu <huyu@bosc.ac.cn>
> Signed-off-by: Ran Wang <wangran@bosc.ac.cn>
> Signed-off-by: Borong Huang <huangborong@bosc.ac.cn>
> ---
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
> target/riscv/cpu-qom.h | 1 +
> target/riscv/cpu.c | 72 ++++++++++++++++++++++++++++++++++++++++++
> 2 files changed, 73 insertions(+)
>
> diff --git a/target/riscv/cpu-qom.h b/target/riscv/cpu-qom.h
> index 4cfdb74891..f2908939e7 100644
> --- a/target/riscv/cpu-qom.h
> +++ b/target/riscv/cpu-qom.h
> @@ -53,6 +53,7 @@
> #define TYPE_RISCV_CPU_VEYRON_V1 RISCV_CPU_TYPE_NAME("veyron-v1")
> #define TYPE_RISCV_CPU_TT_ASCALON RISCV_CPU_TYPE_NAME("tt-ascalon")
> #define TYPE_RISCV_CPU_XIANGSHAN_NANHU RISCV_CPU_TYPE_NAME("xiangshan-nanhu")
> +#define TYPE_RISCV_CPU_XIANGSHAN_KMH RISCV_CPU_TYPE_NAME("xiangshan-kunminghu")
> #define TYPE_RISCV_CPU_HOST RISCV_CPU_TYPE_NAME("host")
>
> OBJECT_DECLARE_CPU_TYPE(RISCVCPU, RISCVCPUClass, RISCV_CPU)
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index 09ded6829a..a076d9dc0c 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -697,6 +697,76 @@ static void rv64_xiangshan_nanhu_cpu_init(Object *obj)
> #endif
> }
>
> +static void rv64_xiangshan_kmh_cpu_init(Object *obj)
> +{
> + CPURISCVState *env = &RISCV_CPU(obj)->env;
> + RISCVCPU *cpu = RISCV_CPU(obj);
> +
> + riscv_cpu_set_misa_ext(env, RVG | RVC | RVB | RVS | RVU | RVH | RVV);
> + env->priv_ver = PRIV_VERSION_1_13_0;
> +
> + /* Enable ISA extensions */
> + cpu->cfg.mmu = true;
> + cpu->cfg.pmp = true;
> +
> + /*
> + * The RISC-V Instruction Set Manual: Volume I
> + * Unprivileged Architecture
> + */
> + cpu->cfg.ext_zicntr = true;
> + cpu->cfg.ext_zihpm = true;
> + cpu->cfg.ext_zihintntl = true;
> + cpu->cfg.ext_zihintpause = true;
> + cpu->cfg.ext_zimop = true;
> + cpu->cfg.ext_zcmop = true;
> + cpu->cfg.ext_zicond = true;
> + cpu->cfg.ext_zawrs = true;
> + cpu->cfg.ext_zacas = true;
> + cpu->cfg.ext_zfh = true;
> + cpu->cfg.ext_zfa = true;
> + cpu->cfg.ext_zcb = true;
> + cpu->cfg.ext_zbc = true;
> + cpu->cfg.ext_zvfh = true;
> + cpu->cfg.ext_zkn = true;
> + cpu->cfg.ext_zks = true;
> + cpu->cfg.ext_zkt = true;
> + cpu->cfg.ext_zvbb = true;
> + cpu->cfg.ext_zvkt = true;
> +
> + /*
> + * The RISC-V Instruction Set Manual: Volume II
> + * Privileged Architecture
> + */
> + cpu->cfg.ext_smstateen = true;
> + cpu->cfg.ext_smcsrind = true;
> + cpu->cfg.ext_sscsrind = true;
> + cpu->cfg.ext_svnapot = true;
> + cpu->cfg.ext_svpbmt = true;
> + cpu->cfg.ext_svinval = true;
> + cpu->cfg.ext_sstc = true;
> + cpu->cfg.ext_sscofpmf = true;
> + cpu->cfg.ext_ssdbltrp = true;
> + cpu->cfg.ext_ssnpm = true;
> + cpu->cfg.ext_smnpm = true;
> + cpu->cfg.ext_smmpm = true;
> + cpu->cfg.ext_sspm = true;
> + cpu->cfg.ext_supm = true;
> +
> + /* The RISC-V Advanced Interrupt Architecture */
> + cpu->cfg.ext_smaia = true;
> + cpu->cfg.ext_ssaia = true;
> +
> + /* RVA23 Profiles */
> + cpu->cfg.ext_zicbom = true;
> + cpu->cfg.ext_zicbop = true;
> + cpu->cfg.ext_zicboz = true;
> + cpu->cfg.ext_svade = true;
> +
> +#ifndef CONFIG_USER_ONLY
> + set_satp_mode_max_supported(cpu, VM_1_10_SV48);
> +#endif
> +}
> +
> #ifdef CONFIG_TCG
> static void rv128_base_cpu_init(Object *obj)
> {
> @@ -3261,6 +3331,8 @@ static const TypeInfo riscv_cpu_type_infos[] = {
> DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_VEYRON_V1, MXL_RV64, rv64_veyron_v1_cpu_init),
> DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_XIANGSHAN_NANHU,
> MXL_RV64, rv64_xiangshan_nanhu_cpu_init),
> + DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_XIANGSHAN_KMH,
> + MXL_RV64, rv64_xiangshan_kmh_cpu_init),
> #ifdef CONFIG_TCG
> DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_BASE128, MXL_RV128, rv128_base_cpu_init),
> #endif /* CONFIG_TCG */
^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: [PATCH v3 1/2] target/riscv: Add BOSC's Xiangshan Kunminghu CPU
2025-04-08 2:21 [PATCH v3 1/2] target/riscv: Add BOSC's Xiangshan Kunminghu CPU Huang Borong
2025-04-08 12:47 ` Daniel Henrique Barboza
@ 2025-04-24 10:49 ` Alistair Francis
2025-04-25 7:01 ` Ran Wang
1 sibling, 1 reply; 4+ messages in thread
From: Alistair Francis @ 2025-04-24 10:49 UTC (permalink / raw)
To: Huang Borong
Cc: qemu-riscv, palmer, alistair.francis, liwei1518, dbarboza,
zhiwei_liu, qemu-devel, wangran
On Tue, Apr 8, 2025 at 12:23 PM Huang Borong <huangborong@bosc.ac.cn> wrote:
>
> Add a CPU entry for the Xiangshan Kunminghu CPU, an open-source,
> high-performance RISC-V processor. More details can be found at:
> https://github.com/OpenXiangShan/XiangShan
>
> Note: The ISA extensions supported by the Xiangshan Kunminghu CPU are
> categorized based on four RISC-V specifications: Volume I: Unprivileged
> Architecture, Volume II: Privileged Architecture, AIA, and RVA23. The
> extensions within each category are organized according to the chapter
> order in the specifications.
>
> Signed-off-by: Yu Hu <huyu@bosc.ac.cn>
> Signed-off-by: Ran Wang <wangran@bosc.ac.cn>
> Signed-off-by: Borong Huang <huangborong@bosc.ac.cn>
> ---
> target/riscv/cpu-qom.h | 1 +
> target/riscv/cpu.c | 72 ++++++++++++++++++++++++++++++++++++++++++
> 2 files changed, 73 insertions(+)
>
> diff --git a/target/riscv/cpu-qom.h b/target/riscv/cpu-qom.h
> index 4cfdb74891..f2908939e7 100644
> --- a/target/riscv/cpu-qom.h
> +++ b/target/riscv/cpu-qom.h
> @@ -53,6 +53,7 @@
> #define TYPE_RISCV_CPU_VEYRON_V1 RISCV_CPU_TYPE_NAME("veyron-v1")
> #define TYPE_RISCV_CPU_TT_ASCALON RISCV_CPU_TYPE_NAME("tt-ascalon")
> #define TYPE_RISCV_CPU_XIANGSHAN_NANHU RISCV_CPU_TYPE_NAME("xiangshan-nanhu")
> +#define TYPE_RISCV_CPU_XIANGSHAN_KMH RISCV_CPU_TYPE_NAME("xiangshan-kunminghu")
> #define TYPE_RISCV_CPU_HOST RISCV_CPU_TYPE_NAME("host")
>
> OBJECT_DECLARE_CPU_TYPE(RISCVCPU, RISCVCPUClass, RISCV_CPU)
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index 09ded6829a..a076d9dc0c 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -697,6 +697,76 @@ static void rv64_xiangshan_nanhu_cpu_init(Object *obj)
> #endif
> }
>
> +static void rv64_xiangshan_kmh_cpu_init(Object *obj)
> +{
> + CPURISCVState *env = &RISCV_CPU(obj)->env;
> + RISCVCPU *cpu = RISCV_CPU(obj);
> +
> + riscv_cpu_set_misa_ext(env, RVG | RVC | RVB | RVS | RVU | RVH | RVV);
> + env->priv_ver = PRIV_VERSION_1_13_0;
> +
> + /* Enable ISA extensions */
> + cpu->cfg.mmu = true;
> + cpu->cfg.pmp = true;
> +
> + /*
> + * The RISC-V Instruction Set Manual: Volume I
> + * Unprivileged Architecture
> + */
> + cpu->cfg.ext_zicntr = true;
> + cpu->cfg.ext_zihpm = true;
> + cpu->cfg.ext_zihintntl = true;
> + cpu->cfg.ext_zihintpause = true;
> + cpu->cfg.ext_zimop = true;
> + cpu->cfg.ext_zcmop = true;
> + cpu->cfg.ext_zicond = true;
> + cpu->cfg.ext_zawrs = true;
> + cpu->cfg.ext_zacas = true;
> + cpu->cfg.ext_zfh = true;
> + cpu->cfg.ext_zfa = true;
> + cpu->cfg.ext_zcb = true;
> + cpu->cfg.ext_zbc = true;
> + cpu->cfg.ext_zvfh = true;
> + cpu->cfg.ext_zkn = true;
> + cpu->cfg.ext_zks = true;
> + cpu->cfg.ext_zkt = true;
> + cpu->cfg.ext_zvbb = true;
> + cpu->cfg.ext_zvkt = true;
> +
> + /*
> + * The RISC-V Instruction Set Manual: Volume II
> + * Privileged Architecture
> + */
> + cpu->cfg.ext_smstateen = true;
> + cpu->cfg.ext_smcsrind = true;
> + cpu->cfg.ext_sscsrind = true;
> + cpu->cfg.ext_svnapot = true;
> + cpu->cfg.ext_svpbmt = true;
> + cpu->cfg.ext_svinval = true;
> + cpu->cfg.ext_sstc = true;
> + cpu->cfg.ext_sscofpmf = true;
> + cpu->cfg.ext_ssdbltrp = true;
> + cpu->cfg.ext_ssnpm = true;
> + cpu->cfg.ext_smnpm = true;
> + cpu->cfg.ext_smmpm = true;
> + cpu->cfg.ext_sspm = true;
> + cpu->cfg.ext_supm = true;
> +
> + /* The RISC-V Advanced Interrupt Architecture */
> + cpu->cfg.ext_smaia = true;
> + cpu->cfg.ext_ssaia = true;
> +
> + /* RVA23 Profiles */
> + cpu->cfg.ext_zicbom = true;
> + cpu->cfg.ext_zicbop = true;
> + cpu->cfg.ext_zicboz = true;
> + cpu->cfg.ext_svade = true;
> +
> +#ifndef CONFIG_USER_ONLY
> + set_satp_mode_max_supported(cpu, VM_1_10_SV48);
> +#endif
> +}
> +
Sorry about this, but we just merged a new way of defining CPU types.
Can you please rebase on
https://github.com/alistair23/qemu/tree/riscv-to-apply.next to use the
new macros? It shouldn't be much work, just a little restructuring.
When sending a new version can you also include a cover letter [1]
1: https://www.qemu.org/docs/master/devel/submitting-a-patch.html#include-a-meaningful-cover-letter
Alistair
> #ifdef CONFIG_TCG
> static void rv128_base_cpu_init(Object *obj)
> {
> @@ -3261,6 +3331,8 @@ static const TypeInfo riscv_cpu_type_infos[] = {
> DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_VEYRON_V1, MXL_RV64, rv64_veyron_v1_cpu_init),
> DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_XIANGSHAN_NANHU,
> MXL_RV64, rv64_xiangshan_nanhu_cpu_init),
> + DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_XIANGSHAN_KMH,
> + MXL_RV64, rv64_xiangshan_kmh_cpu_init),
> #ifdef CONFIG_TCG
> DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_BASE128, MXL_RV128, rv128_base_cpu_init),
> #endif /* CONFIG_TCG */
> --
> 2.34.1
>
>
^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: [PATCH v3 1/2] target/riscv: Add BOSC's Xiangshan Kunminghu CPU
2025-04-24 10:49 ` Alistair Francis
@ 2025-04-25 7:01 ` Ran Wang
0 siblings, 0 replies; 4+ messages in thread
From: Ran Wang @ 2025-04-25 7:01 UTC (permalink / raw)
To: Alistair Francis, Huang Borong
Cc: qemu-riscv, palmer, alistair.francis, liwei1518, dbarboza,
zhiwei_liu, qemu-devel
Hi Alistair
On 2025/4/24 18:49, Alistair Francis wrote:
> On Tue, Apr 8, 2025 at 12:23 PM Huang Borong <huangborong@bosc.ac.cn> wrote:
>>
>> Add a CPU entry for the Xiangshan Kunminghu CPU, an open-source,
>> high-performance RISC-V processor. More details can be found at:
<snip>
>> + cpu->cfg.ext_ssaia = true;
>> +
>> + /* RVA23 Profiles */
>> + cpu->cfg.ext_zicbom = true;
>> + cpu->cfg.ext_zicbop = true;
>> + cpu->cfg.ext_zicboz = true;
>> + cpu->cfg.ext_svade = true;
>> +
>> +#ifndef CONFIG_USER_ONLY
>> + set_satp_mode_max_supported(cpu, VM_1_10_SV48);
>> +#endif
>> +}
>> +
>
> Sorry about this, but we just merged a new way of defining CPU types.
> Can you please rebase on
> https://github.com/alistair23/qemu/tree/riscv-to-apply.next to use the
> new macros? It shouldn't be much work, just a little restructuring.
>
> When sending a new version can you also include a cover letter [1]
>
> 1: https://www.qemu.org/docs/master/devel/submitting-a-patch.html#include-a-meaningful-cover-letter
Sure, Borong just left BOSC and I will take over his job and send out
next version patch mail later.
Thanks & Regards,
Ran
> Alistair
>
>> #ifdef CONFIG_TCG
>> static void rv128_base_cpu_init(Object *obj)
>> {
>> @@ -3261,6 +3331,8 @@ static const TypeInfo riscv_cpu_type_infos[] = {
>> DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_VEYRON_V1, MXL_RV64, rv64_veyron_v1_cpu_init),
>> DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_XIANGSHAN_NANHU,
>> MXL_RV64, rv64_xiangshan_nanhu_cpu_init),
>> + DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_XIANGSHAN_KMH,
>> + MXL_RV64, rv64_xiangshan_kmh_cpu_init),
>> #ifdef CONFIG_TCG
>> DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_BASE128, MXL_RV128, rv128_base_cpu_init),
>> #endif /* CONFIG_TCG */
>> --
>> 2.34.1
>>
>>
^ permalink raw reply [flat|nested] 4+ messages in thread
end of thread, other threads:[~2025-04-25 11:45 UTC | newest]
Thread overview: 4+ messages (download: mbox.gz follow: Atom feed
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2025-04-08 2:21 [PATCH v3 1/2] target/riscv: Add BOSC's Xiangshan Kunminghu CPU Huang Borong
2025-04-08 12:47 ` Daniel Henrique Barboza
2025-04-24 10:49 ` Alistair Francis
2025-04-25 7:01 ` Ran Wang
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