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x86_64-redhat-linux-gnu) MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=170.10.133.124; envelope-from=alex.williamson@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H5=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On Thu, 17 Apr 2025 01:41:22 +0800 Tomita Moeko wrote: > On 4/17/25 00:10, Alex Williamson wrote: > > On Wed, 16 Apr 2025 23:45:08 +0800 > > Tomita Moeko wrote: > > > >> On 4/16/25 03:04, Alex Williamson wrote: > >>> On Wed, 16 Apr 2025 01:36:15 +0800 > >>> Tomita Moeko wrote: > >>>> > >>>> The generation register also exists on discrete GPUs. In the new xe > >>>> driver [1], the Battlemage discrete GPU shares the same logic reading > >>>> GMD_ID_DISPLAY register. The driver itself uses is_dgfx bit mapped to > >>>> device id. In QEMU, we need to know whether the device is a supported > >>>> IGD device first before applying the IGD-specific quirk, especially > >>>> for legacy mode. > >>>> > >>>> The most feasible way is to check if kernel exposes VFIO_REGION_SUBTYPE_ > >>>> INTEL_IGD_OPREGION on that device I think, as only IGD has OpRegion. > >>>> > >>>> i915 driver [2] and Arrow Lake datasheet [3] shows that Intel has > >>>> removed the BDSM register by making the DSM range part of BAR2 since > >>>> Meteor Lake and onwards. QEMU only need to quirk on the register for > >>>> IGD devices until Raptor Lake, meaning that the device list is fixed > >>>> for now. > >>>> > >>>> By the way, for legacy mode, I think we should only support it until > >>>> Gen 9, as Intel only provide VBIOS or CSM support until that generation, > >>>> and seabios cannot handle 64 bit BDSM register. I'm also wondering if > >>>> VGA really works on newer generations. > >>> > >>> If it's a VGA class device, it really should, but without CSM I could > >>> see why you have doubts. > >> > >> Without CSM/VBIOS there is no pre-boot video, but when it booted to OS, > >> driver is used for video rather than VGA. Though it claims itself as > >> VGA class, it does not have VGA compatiblity. A770 even does not have > >> IO BAR, definitely it cannot handle VGA decoding. > > > > VGA ranges are implicit in a VGA class device, they're not backed by > > BARs. Lack of CSM support makes it more difficult to prove whether VGA > > support is present since we can't easily initialize the device for a > > legacy OS, but I don't think lack of CSM necessary proves the hardware > > doesn't support VGA. If we really cared, we could probably do some low > > level experiments writing into the VGA frame buffer range to test if > > it's present and behaves as expected relative to memory and IO enable > > bits. > > Sorry for my misunderstanding. The bridge control register in PCI bridge > config space determines forwarding VGA IO/MMIO accesses to which device, > BAR is not related in this process. > > As device initialization (by legacy VBIOS) is required for booting > legacy OS with seabios, limiting legacy mode to gen9 and older sounds > resonable. > > Trying VGA framebuffer would be difficult we have to disable EFI GOP and > manually instruct the device to enter VGA mode without VBIOS routines. > It's not a major problem here, let's skip it for now? This is only a curiosity as far as I'm concerned, I agree with your proposal that we can drop legacy mode where the bare metal system doesn't even support CSM. Thanks, Alex